CN109240405B - Self-adaptive LDO circuit - Google Patents

Self-adaptive LDO circuit Download PDF

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CN109240405B
CN109240405B CN201811397485.7A CN201811397485A CN109240405B CN 109240405 B CN109240405 B CN 109240405B CN 201811397485 A CN201811397485 A CN 201811397485A CN 109240405 B CN109240405 B CN 109240405B
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CN109240405A (en
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李勃
钱永学
叶晓斌
王鑫
孟浩
黄鑫
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Beijing Angrui Microelectronics Technology Co.,Ltd.
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Beijing Angrui Microelectronics Technology Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

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Abstract

The application provides a self-adaptation LDO circuit, include: the circuit comprises a main circuit, a detection circuit and a compensation circuit, wherein the main circuit is used for regulating input voltage according to reference voltage to obtain output voltage; the detection circuit is used for detecting the load current of the main circuit and obtaining compensation current information according to the load current; the compensation circuit is used for adjusting the zero pole and the loop bandwidth of the main circuit according to the compensation current information so as to ensure the stability of the loop, and the zero pole comprises a dominant pole, a first dominant pole and a second dominant pole. According to the self-adaptive LDO circuit, the compensation current information is obtained through the detection circuit according to the load current, so that the compensation circuit adjusts the zero pole and the loop bandwidth of the main circuit according to the compensation current information, and the stability of the loop is guaranteed. The application provides a self-adaptation LDO circuit, when increaseing LDO loop bandwidth, improve transient response, guaranteed the high stability of loop.

Description

Self-adaptive LDO circuit
Technical Field
The application relates to the technical field of integrated circuits, in particular to a self-adaptive LDO circuit.
Background
In recent years, various portable electronic products have been popularized and product functions have been enriched, so that the development of power management IC technology has been promoted, and a high-performance and low-cost power management chip has been more and more favored by users. Integrated voltage regulators are moving in three directions of high power density, high reliability and high efficiency, and when the load changes rapidly, the transient characteristics are a great challenge in the design of the integrated voltage regulators.
The conventional LDO circuit structure is shown in FIG. 1, and the circuit includes only two poles of zero, the major pole is at point A, the minor major pole is at point B, and the frequency of the major pole
Figure BDA0001875519890000011
Frequency of the secondary dominant pole:
Figure BDA0001875519890000012
where Rout represents the output resistance at point A and Cload represents the output resistance at point AOut-of-chip capacitance, rout represents the output resistance at point B, and Cgs1 represents the gate-source capacitance of MP 1. At present, a large capacitor Cload is usually added outside a chip to enhance the transient characteristic of the LDO, so that when the current of the LDO load is in a transient state, the voltage change on the capacitor is small, and the ripple voltage of the LDO is reduced.
However, as the load current increases, the frequency of the main pole of the circuit increases, and the position of the sub-main pole is not changed, so that the loop bandwidth GBW of the circuit increases, the phase margin decreases, and the loop stability is deteriorated.
In view of this, how to improve the transient response of the LDO and ensure high stability of the loop is an urgent problem to be solved by those skilled in the art.
Disclosure of Invention
In view of this, the present application provides an adaptive LDO circuit, which can improve the transient response of the LDO circuit and ensure high stability of the loop.
In order to achieve the above object, the present application provides the following technical solutions:
an adaptive LDO circuit, comprising: a main body circuit, a detection circuit and a compensation circuit, wherein,
the main circuit is used for regulating the input voltage according to the reference voltage to obtain an output voltage;
the detection circuit is used for detecting the load current of the main circuit and obtaining compensation current information according to the load current;
the compensation circuit is used for adjusting the zero pole and the loop bandwidth of the main circuit according to the compensation current information so as to ensure the stability of the loop, and the zero pole comprises a dominant pole, a first dominant pole and a second dominant pole.
Preferably, the main body circuit includes: the circuit comprises a differential amplifier, a buffer, a voltage divider and a power tube.
Preferably, the differential amplifier includes: a first PMOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a first N-type MOS transistor MN1, and a second N-type MOS transistor MN 2;
the buffer includes: a fifth P-type MOS transistor MP5 and a sixth P-type MOS transistor MP 6;
the voltage divider includes: an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, and an eleventh P-type MOS transistor MP 11;
the power tube includes: a seventh P-type MOS transistor MP 7;
the grid and the drain of the first P-type MOS tube MP1 are connected with a current source, and the source is connected with the power supply;
the gate of the second P-type MOS transistor MP2 and the gate of the fifth P-type MOS transistor MP5 are both connected to the gate of the first P-type MOS transistor MP1, the source of the second P-type MOS transistor MP2 and the source of the fifth P-type MOS transistor MP5 are both connected to the power supply, the drain of the second P-type MOS transistor MP2 is connected to the source of the third P-type MOS transistor MP3 and the source of the fourth P-type MOS transistor MP4, and the drain of the fifth P-type MOS transistor MP5 is connected to the source of the sixth P-type MOS transistor MP6 and the gate of the seventh P-type MOS transistor MP 7;
the gate of the third P-type MOS transistor MP3 is connected to the gate and the drain of the ninth P-type MOS transistor MP9, and the drain of the third P-type MOS transistor MP3 is connected to the drain and the gate of the first N-type MOS transistor MN1 and the gate of the second N-type MOS transistor MN 2;
the gate of the fourth P-type MOS transistor MP4 is connected to the reference voltage, and the drain of the fourth P-type MOS transistor MP 3578 and the drain of the second N-type MOS transistor MN2 are connected to the gate of the sixth P-type MOS transistor MP 6;
the source electrode of the first N-type MOS transistor MN1, the source electrode of the second N-type MOS transistor MN2 and the drain electrode of the sixth P-type MOS transistor MP6 are all grounded;
the source electrode of the seventh P-type MOS transistor MP7 is connected to the power supply, and the drain electrode is connected to the source electrode of the eighth P-type MOS transistor MP 8;
the gate and the drain of the eighth P-type MOS transistor MP8 are connected to the source of the ninth P-type MOS transistor MP 9;
the gate and the drain of the ninth P-type MOS transistor MP9 are connected to the source of the tenth P-type MOS transistor MP 10;
the drain of the tenth P-type MOS transistor MP10 is connected to the source of the eleventh P-type MOS transistor MP11, and the gate of the tenth P-type MOS transistor MP10 and the gate and the drain of the eleventh P-type MOS transistor MP11 are both grounded.
Preferably, the differential amplifier includes: a first PMOS transistor MP1, a second P-type MOS transistor MP2, an eighteenth P-type MOS transistor MP18, a nineteenth P-type MOS transistor MP19, a twentieth P-type MOS transistor MP20, a twenty-first P-type MOS transistor MP21, a twenty-second P-type MOS transistor MP22, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, an eighth N-type MOS transistor MN8, and a ninth N-type MOS transistor MN 9;
the buffer includes: a fifth P-type MOS transistor MP5 and a sixth P-type MOS transistor MP 6;
the voltage divider includes: a first resistor R1 and a second resistor R2;
the power tube includes: a seventh P-type MOS transistor MP 7;
the grid and the drain of the first P-type MOS tube MP1 are connected with a current source, and the source is connected with the power supply;
the gate of the second P-type MOS transistor MP2, the gate of the eighteenth P-type MOS transistor MP18, the gate of the first P-type MOS transistor MP1 and the gate of the fifth P-type MOS transistor MP5 are connected, the source of the second P-type MOS transistor MP2, the source of the fifth P-type MOS transistor MP5, the source of the seventh P-type MOS transistor MP7, the source of the eighteenth P-type MOS transistor MP18, the source of the nineteenth P-type MOS transistor MP19 and the source of the twenty-second P-type MOS transistor MP22 are all connected to the power supply, and the drain of the second P-type MOS transistor MP2 is connected to the drain, the gate of the first N-type MOS transistor MN1 and the gate of the second N-type MOS transistor MN 2;
the drain of the second N-type MOS transistor MN2 is connected to the source of the sixth N-type MOS transistor MN6 and the source of the ninth N-type MOS transistor MN9, and the source of the first N-type MOS transistor MN1 and the source of the second N-type MOS transistor MN2 are both grounded;
the drain electrode of the eighteenth P-type MOS transistor MP18 is connected to the source electrode of the twentieth P-type MOS transistor MP20 and the source electrode of the twenty-first P-type MOS transistor MP 21;
the gate of the twentieth P-type MOS transistor MP20 is connected to the gate and the drain of the nineteenth P-type MOS transistor MP19 and the drain of the sixth N-type MOS transistor MN6, the drain of the twentieth P-type MOS transistor MP20 is connected to the gate and the drain of the seventh N-type MOS transistor MN7 and the gate of the eighth N-type MOS transistor MN8, and the gate of the sixth N-type MOS transistor MN6 is connected to the reference voltage;
a drain electrode of the eighth N-type MOS transistor MN8 is connected to a drain electrode of the twenty-first P-type MOS transistor MP21 and a gate electrode of the sixth P-type MOS transistor MP6, and a source electrode of the eighth N-type MOS transistor MN8 and a source electrode of the seventh N-type MOS transistor MN7 are both grounded;
the gate of the twenty-first P-type MOS transistor MP21 is connected to the drain of the ninth N-type MOS transistor MN9 and the gate and the drain of the twenty-second P-type MOS transistor MP 22;
the drain of the fifth P-type MOS transistor MP5 is connected to the source of the sixth P-type MOS transistor MP6 and the gate of the seventh P-type MOS transistor MP7, the drain of the sixth P-type MOS transistor MP6 is grounded, and the drain of the seventh P-type MOS transistor MP7 is grounded through the first resistor R1 and the second resistor R2 in sequence;
the gate of the ninth N-type MOS transistor MN9 is connected to an end of the first resistor R1 away from the drain of the seventh P-type MOS transistor MP 7.
Preferably, the detection circuit includes: a twelfth P-type MOS transistor MP12, a thirteenth P-type MOS transistor MP13, a fourteenth P-type MOS transistor MP14, a third N-type MOS transistor MN3, and a fourth N-type MOS transistor MN 4;
a gate of the twelfth P-type MOS transistor MP12 is connected to a gate of the seventh P-type MOS transistor MP7, a source of the twelfth P-type MOS transistor MP12 is connected to the power supply, and a drain of the twelfth P-type MOS transistor MP12 is connected to a source of the thirteenth P-type MOS transistor MP 13;
a drain of the thirteenth P-type MOS transistor MP13 is connected to a gate and a drain of the third N-type MOS transistor MN3 and a gate of the fourth N-type MOS transistor MN4, a gate of the thirteenth P-type MOS transistor MP13 is connected to a gate and a drain of the fourteenth P-type MOS transistor MP14 and a drain of the fourth N-type MOS transistor MN4, and a source of the fourteenth P-type MOS transistor MP14 is connected to a drain of the seventh P-type MOS transistor MP 7;
the source electrode of the third N-type MOS transistor MN3 and the source electrode of the fourth N-type MOS transistor MN4 are both grounded.
Preferably, the compensation circuit includes: a fifth N-type MOS transistor MN5, a fifteenth P-type MOS transistor MP15, a sixteenth P-type MOS transistor MP16, and a seventeenth P-type MOS transistor MP 17;
the source electrode of the fifteenth P-type MOS transistor MP15, the source electrode of the sixteenth P-type MOS transistor MP16 and the source electrode of the seventeenth P-type MOS transistor MP17 are all connected to the power supply;
the gate and the drain of the fifteenth P-type MOS transistor MP15 are connected to the drain of the fifth N-type MOS transistor MN5, the gate of the seventeenth P-type MOS transistor MP17 and the gate of the sixteenth P-type MOS transistor MP 16;
the drain electrode of the sixteenth P-type MOS tube MP16 is connected with the compensation input end of the main body circuit;
the drain electrode of the seventeenth P-type MOS transistor MP17 is connected to the drain electrode of the fifth P-type MOS transistor MP5 and the source electrode of the sixth P-type MOS transistor MP 6;
the grid electrode of the fifth N-type MOS transistor MN5 is connected with the compensation current information output end of the detection circuit, and the source electrode is grounded.
According to the technical scheme, the application provides a high-stability self-adaptive LDO circuit composed of a main circuit, a detection circuit and a compensation circuit, and compensation current information is obtained through the detection circuit according to load current, so that the compensation circuit adjusts the zero pole and the loop bandwidth of the main circuit according to the compensation current information, and the stability of a loop is guaranteed. The application provides a this self-adaptation LDO circuit, when increaseing LDO loop bandwidth, improve transient response, guaranteed the high stability of loop.
Drawings
In order to more clearly illustrate the embodiments of the present invention and the technical solutions in the prior art, the drawings used in the description of the embodiments and the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a block diagram of a conventional LDO circuit;
fig. 2 is a block diagram of an adaptive LDO circuit according to an embodiment of the present application;
fig. 3 is a structural diagram of an adaptive LDO circuit according to a second embodiment of the present application;
fig. 4 is a structural diagram of an adaptive LDO circuit according to a third embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For the transient response that improves LDO, can guarantee the high stability of loop, this application provides a self-adaptation LDO circuit of high stability, and the concrete scheme is as follows:
example one
An embodiment of the present application provides a self-adaptive LDO circuit, as shown in fig. 2, fig. 2 is a structural diagram of the self-adaptive LDO circuit according to an embodiment of the present application. The adaptive LDO circuit includes: a main body circuit 101, a detection circuit 102, and a compensation circuit 103, wherein,
the main body circuit 101 is used for regulating the input voltage according to the reference voltage to obtain an output voltage;
the detection circuit 102 is configured to detect a load current of the main circuit, and obtain compensation current information according to the load current;
the compensation circuit 103 is configured to adjust a zero pole and a loop bandwidth of the main circuit according to the compensation current information to ensure stability of the loop, where the zero pole includes a dominant pole, a first dominant pole, and a second dominant pole.
As can be seen from the above technical solutions, the adaptive LDO circuit provided in the first embodiment of the present application includes: the main circuit, the detection circuit and the compensation circuit obtain compensation current information according to the load current through the detection circuit, so that the compensation circuit adjusts the zero pole and the loop bandwidth of the main circuit according to the compensation current information, and the stability of the loop is guaranteed. The application provides a this self-adaptation LDO circuit has very low static consumption when no-load, and detection circuitry can follow load current's change at any time, adjusts zero pole and loop bandwidth according to load current's change to when increaseing LDO loop bandwidth, improving transient response, guaranteed the high stability of loop.
Example two
On the basis of the first embodiment, a specific circuit structure is provided in the second embodiment of the present application, and as shown in fig. 3, a structure diagram of an adaptive LDO circuit provided in the second embodiment of the present application is provided. The adaptive LDO circuit includes: the circuit comprises a main circuit, a detection circuit and a compensation circuit.
Specifically, the main body circuit includes: the circuit comprises a differential amplifier, a buffer, a voltage divider and a power tube. The differential amplifier realizes comparison between reference voltage VREF and feedback voltage; the buffer is used as a part different from the traditional circuit and is used for splitting the secondary main pole into two poles, so that the phase margin is improved. In the circuit shown in fig. 3, the voltage divider is implemented by PMOS transistors, which reduces the chip area and has extremely low static power consumption under light load.
Specifically, as shown in fig. 3, the differential amplifier includes: a first PMOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a first N-type MOS transistor MN1, and a second N-type MOS transistor MN 2;
the buffer includes: a fifth P-type MOS transistor MP5 and a sixth P-type MOS transistor MP 6;
the voltage divider includes: an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, and an eleventh P-type MOS transistor MP 11;
the power tube includes: a seventh P-type MOS transistor MP 7;
the grid and the drain of the first P-type MOS tube MP1 are connected with a current source, and the source is connected with the power supply;
the grid electrode of the second P-type MOS tube MP2 and the grid electrode of the fifth P-type MOS tube MP5 are both connected with the grid electrode of the first P-type MOS tube MP1, the source electrode of the second P-type MOS tube MP2 and the source electrode of the fifth P-type MOS tube MP5 are both connected with the power supply, the drain electrode of the second P-type MOS tube MP2 is connected with the source electrode of the third P-type MOS tube MP3 and the source electrode of the fourth P-type MOS tube MP4, and the drain electrode of the fifth P-type MOS tube MP5 is connected with the source electrode of the sixth P-type MOS tube MP6 and the grid electrode of the seventh P-type MOS tube MP 7;
the grid electrode of the third P-type MOS tube MP3 is connected with the grid electrode and the drain electrode of the ninth P-type MOS tube MP9, and the drain electrode of the third P-type MOS tube MP3 is connected with the drain electrode and the grid electrode of the first N-type MOS tube MN1 and the grid electrode of the second N-type MOS tube MN 2;
the grid electrode of the fourth P-type MOS tube MP4 is connected with the reference voltage, and the drain electrode of the fourth P-type MOS tube MP4 and the drain electrode of the second N-type MOS tube MN2 are simultaneously connected with the grid electrode of the sixth P-type MOS tube MP 6;
the source electrode of the first N-type MOS transistor MN1, the source electrode of the second N-type MOS transistor MN2 and the drain electrode of the sixth P-type MOS transistor MP6 are all grounded;
the source electrode of the seventh P-type MOS tube MP7 is connected with the power supply, and the drain electrode is connected with the source electrode of the eighth P-type MOS tube MP 8;
the gate and the drain of the eighth P-type MOS transistor MP8 are connected to the source of the ninth P-type MOS transistor MP 9;
the grid electrode and the drain electrode of the ninth P-type MOS transistor MP9 are simultaneously connected with the source electrode of the tenth P-type MOS transistor MP 10;
the drain of the tenth P-type MOS transistor MP10 is connected to the source of the eleventh P-type MOS transistor MP11, and the gate of the tenth P-type MOS transistor MP10 and the gate and the drain of the eleventh P-type MOS transistor MP11 are both grounded.
The detection circuit includes: a twelfth P-type MOS transistor MP12, a thirteenth P-type MOS transistor MP13, a fourteenth P-type MOS transistor MP14, a third N-type MOS transistor MN3, and a fourth N-type MOS transistor MN 4;
the grid electrode of the twelfth P-type MOS tube MP12 is connected with the grid electrode of the seventh P-type MOS tube MP7, the source electrode of the twelfth P-type MOS tube MP12 is connected with the power supply, and the drain electrode of the twelfth P-type MOS tube MP12 is connected with the source electrode of the thirteenth P-type MOS tube MP 13;
the drain electrode of the thirteenth P-type MOS transistor MP13 is connected to the gate electrode and the drain electrode of the third N-type MOS transistor MN3 and the gate electrode of the fourth N-type MOS transistor MN4, the gate electrode of the thirteenth P-type MOS transistor MP13 is connected to the gate electrode and the drain electrode of the fourteenth P-type MOS transistor MP14 and the drain electrode of the fourth N-type MOS transistor MN4, and the source electrode of the fourteenth P-type MOS transistor MP14 is connected to the drain electrode of the seventh P-type MOS transistor MP 7;
the source of the third N-type MOS transistor MN3 and the source of the fourth N-type MOS transistor MN4 are both grounded.
The compensation circuit includes: a fifth N-type MOS transistor MN5, a fifteenth P-type MOS transistor MP15, a sixteenth P-type MOS transistor MP16, and a seventeenth P-type MOS transistor MP 17;
the source electrode of the fifteenth P-type MOS transistor MP15, the source electrode of the sixteenth P-type MOS transistor MP16 and the source electrode of the seventeenth P-type MOS transistor MP17 are all connected with a power supply;
the grid and the drain of the fifteenth P-type MOS tube MP15 are connected with the drain of the fifth N-type MOS tube MN5, the grid of the seventeenth P-type MOS tube MP17 and the grid of the sixteenth P-type MOS tube MP 16;
the drain electrode of the sixteenth P-type MOS tube MP16 is connected with the compensation input end of the main circuit; in this embodiment, the drain of the sixteenth P-type MOS transistor MP16 is connected to the drain of the second P-type MOS transistor MP2, the source of the third P-type MOS transistor MP3 and the source of the fourth P-type MOS transistor MP 4;
the drain electrode of the seventeenth P-type MOS transistor MP17 is connected with the drain electrode of the fifth P-type MOS transistor MP5 and the source electrode of the sixth P-type MOS transistor MP 6;
the grid electrode of the fifth N-type MOS transistor MN5 is connected with the compensation current information output end of the detection circuit, and the source electrode is grounded.
As shown in fig. 3, there are three poles-zero, i.e., one dominant pole and two secondary dominant poles, which can be expressed as:
the A node generates a dominant pole, the frequency of which
Figure BDA0001875519890000091
The node B generates a first dominant pole, the frequency of which
Figure BDA0001875519890000092
The C node generates a second dominant pole, the frequency of which
Figure BDA0001875519890000093
Wherein Rout represents the output resistance of the node A, ro2 and ro4 represent the output resistances of MN2 and MP4 at the node B respectively, Cgs6 represents the gate-source capacitance of MP6, gm6 represents the transconductance of MP6, and Cgs7 represents the gate-source capacitance of MP 7;
when the load current increases, P1 increases and GBW of the loop increases, and if the secondary dominant pole is not increased in time, the loop stability becomes worse when the dominant pole and the secondary dominant pole are close to each other. According to the circuit provided by the invention, when the load current is increased, the LDO detection circuit detects the increase of the load current, the mirror current in the LDO compensation circuit is increased, and the output resistance of the differential amplifier in the LDO main circuit is increased
Figure BDA0001875519890000094
Decrease, P2 increase; the current of the buffer increases, gm6 increases, then P3 increases. Therefore, the load current is increased, the loop bandwidth GBW is increased, and the stability is optimized, so that the transient response change is good and the output voltage ripple is small when the load has step current.
As can be seen from the above technical solutions, the adaptive LDO circuit provided in the second embodiment of the present application includes: the main circuit, the detection circuit and the compensation circuit obtain compensation current information according to the load current through the detection circuit, so that the compensation circuit adjusts the zero pole and the loop bandwidth of the main circuit according to the compensation current information, and the stability of the loop is guaranteed. The application provides a this self-adaptation LDO circuit has extremely low static power consumption when no-load, under the heavy load condition and when load current appears great step, detection circuitry can follow load current's change at any time, adjusts pole-zero and loop bandwidth according to load current's change to when increaseing LDO loop bandwidth, improve transient response, guaranteed the high stability of loop. Moreover, the circuit provided by the application is simple in structure, only needs to be modified on the basis of a traditional structure, and design complexity is reduced.
EXAMPLE III
On the basis of the first embodiment, a third embodiment of the present application provides another specific circuit structure, and as shown in fig. 4, is a structural diagram of an adaptive LDO circuit provided in the third embodiment of the present application. The adaptive LDO circuit includes: the circuit comprises a main circuit, a detection circuit and a compensation circuit.
Specifically, the main body circuit includes: the circuit comprises a differential amplifier, a buffer, a voltage divider and a power tube. In this embodiment, compared with the second embodiment, the main difference is that the input operational amplifier buffer adopts an NMOS transistor for input, and meanwhile, the MOS resistor in the main body circuit is replaced with a conventional polysilicon resistor, so as to meet different requirements of various situations.
As shown in fig. 4, the differential amplifier includes: a first PMOS transistor MP1, a second P-type MOS transistor MP2, an eighteenth P-type MOS transistor MP18, a nineteenth P-type MOS transistor MP19, a twentieth P-type MOS transistor MP20, a twenty-first P-type MOS transistor MP21, a twenty-second P-type MOS transistor MP22, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, an eighth N-type MOS transistor MN8, and a ninth N-type MOS transistor MN 9;
the buffer includes: a fifth P-type MOS transistor MP5 and a sixth P-type MOS transistor MP 6;
the voltage divider includes: a first resistor R1 and a second resistor R2;
the power tube includes: a seventh P-type MOS transistor MP 7;
the grid and the drain of the first P-type MOS tube MP1 are connected with a current source, and the source is connected with the power supply;
the grid electrode of the second P-type MOS tube MP2 and the grid electrode of the eighteenth P-type MOS tube MP18 are connected with the grid electrode of the first P-type MOS tube MP1 and the grid electrode of the fifth P-type MOS tube MP5, the source electrode of the second P-type MOS tube MP2, the source electrode of the fifth P-type MOS tube MP5, the source electrode of the seventh P-type MOS tube MP7, the source electrode of the eighteenth P-type MOS tube MP18, the source electrode of the nineteenth P-type MOS tube MP19 and the source electrode of the twenty-second P-type MOS tube MP22 are all connected with a power supply, and the drain electrode of the second P-type MOS tube MP2 is connected with the drain electrode and the grid electrode of the first N-type MOS tube MN1 and the grid electrode of the second N-type MOS tube MN 2;
the drain electrode of the second N-type MOS transistor MN2 is connected to the source electrode of the sixth N-type MOS transistor MN6 and the source electrode of the ninth N-type MOS transistor MN9, and the source electrode of the first N-type MOS transistor MN1 and the source electrode of the second N-type MOS transistor MN2 are both grounded;
the drain electrode of the eighteenth P-type MOS tube MP18 is simultaneously connected with the source electrode of the twentieth P-type MOS tube MP20 and the source electrode of the twenty-first P-type MOS tube MP 21;
the gate of the twentieth P-type MOS transistor MP20 is connected to the gate and the drain of the nineteenth P-type MOS transistor MP19 and the drain of the sixth N-type MOS transistor MN6, the drain of the twentieth P-type MOS transistor MP20 is connected to the gate and the drain of the seventh N-type MOS transistor MN7 and the gate of the eighth N-type MOS transistor MN8, and the gate of the sixth N-type MOS transistor MN6 is connected to the reference voltage;
the drain electrode of the eighth N-type MOS transistor MN8 is connected to the drain electrode of the twenty-first P-type MOS transistor MP21 and the gate electrode of the sixth P-type MOS transistor MP6, and the source electrode of the eighth N-type MOS transistor MN8 and the source electrode of the seventh N-type MOS transistor MN7 are both grounded;
the grid electrode of the twenty-first P-type MOS tube MP21 is connected with the drain electrode of the ninth N-type MOS tube MN9 and the grid electrode and the drain electrode of the twenty-second P-type MOS tube MP 22;
the drain electrode of the fifth P-type MOS transistor MP5 is connected to the source electrode of the sixth P-type MOS transistor MP6 and the gate electrode of the seventh P-type MOS transistor MP7, the drain electrode of the sixth P-type MOS transistor MP6 is grounded, and the drain electrode of the seventh P-type MOS transistor MP7 is grounded through the first resistor R1 and the second resistor R2 in sequence;
the gate of the ninth N-type MOS transistor MN9 is connected to the end of the first resistor R1 away from the drain of the seventh P-type MOS transistor MP 7.
The detection circuit includes: a twelfth P-type MOS transistor MP12, a thirteenth P-type MOS transistor MP13, a fourteenth P-type MOS transistor MP14, a third N-type MOS transistor MN3, and a fourth N-type MOS transistor MN 4;
the grid electrode of the twelfth P-type MOS tube MP12 is connected with the grid electrode of the seventh P-type MOS tube MP7, the source electrode of the twelfth P-type MOS tube MP12 is connected with the power supply, and the drain electrode of the twelfth P-type MOS tube MP12 is connected with the source electrode of the thirteenth P-type MOS tube MP 13;
the drain electrode of the thirteenth P-type MOS transistor MP13 is connected to the gate electrode and the drain electrode of the third N-type MOS transistor MN3 and the gate electrode of the fourth N-type MOS transistor MN4, the gate electrode of the thirteenth P-type MOS transistor MP13 is connected to the gate electrode and the drain electrode of the fourteenth P-type MOS transistor MP14 and the drain electrode of the fourth N-type MOS transistor MN4, and the source electrode of the fourteenth P-type MOS transistor MP14 is connected to the drain electrode of the seventh P-type MOS transistor MP 7;
the source of the third N-type MOS transistor MN3 and the source of the fourth N-type MOS transistor MN4 are both grounded.
The compensation circuit includes: a fifth N-type MOS transistor MN5, a fifteenth P-type MOS transistor MP15, a sixteenth P-type MOS transistor MP16, and a seventeenth P-type MOS transistor MP 17;
the source electrode of the fifteenth P-type MOS transistor MP15, the source electrode of the sixteenth P-type MOS transistor MP16 and the source electrode of the seventeenth P-type MOS transistor MP17 are all connected with a power supply;
the grid and the drain of the fifteenth P-type MOS tube MP15 are connected with the drain of the fifth N-type MOS tube MN5, the grid of the seventeenth P-type MOS tube MP17 and the grid of the sixteenth P-type MOS tube MP 16;
the drain electrode of the sixteenth P-type MOS tube MP16 is connected with the compensation input end of the main circuit; in this embodiment, the drain of the sixteenth P-type MOS transistor MP16 is connected to the source of the twenty-first P-type MOS transistor MP21, the source of the twentieth P-type MOS transistor MP20 and the drain of the eighteenth P-type MOS transistor MP 18;
the drain electrode of the seventeenth P-type MOS transistor MP17 is connected with the drain electrode of the fifth P-type MOS transistor MP5 and the source electrode of the sixth P-type MOS transistor MP 6;
the grid electrode of the fifth N-type MOS transistor MN5 is connected with the compensation current information output end of the detection circuit, and the source electrode is grounded.
In this circuit, there are three poles-zero points as well, which can be expressed as:
the A node generates a dominant pole, the frequency of which
Figure BDA0001875519890000121
The node B generates a first dominant pole, the frequency of which
Figure BDA0001875519890000122
The C node generates a second dominant pole, the frequency of which
Figure BDA0001875519890000123
Wherein Rout represents the output resistance of the node A, ro2 and ro4 represent the output resistances of MN8 and MP21 at the node B respectively, Cgs6 represents the gate-source capacitance of MP6, gm6 represents the transconductance of MP6, and Cgs7 represents the gate-source capacitance of MP 7;
when the load current increases, P1 increases and GBW of the loop increases, and if the secondary dominant pole is not increased in time, the loop stability becomes worse when the dominant pole and the secondary dominant pole are close to each other. According to the circuit provided by the invention, when the load current is increased, the LDO detection circuit detects the increase of the load current, the mirror current in the LDO compensation circuit is increased, and the output resistance of the differential amplifier in the LDO main circuit is increased
Figure BDA0001875519890000124
Decrease, P2 increase; the current of the buffer increases, gm6 increases, then P3 increases. Therefore, the load current is increased, the loop bandwidth GBW is increased, and the stability is optimized, so that the transient response change is good and the output voltage ripple is small when the load has step current.
As can be seen from the above technical solutions, the adaptive LDO circuit provided in the third embodiment of the present application includes: the main circuit, the detection circuit and the compensation circuit obtain compensation current information according to the load current through the detection circuit, so that the compensation circuit adjusts the zero pole and the loop bandwidth of the main circuit according to the compensation current information, and the stability of the loop is guaranteed. The application provides a this self-adaptation LDO circuit, when load current appears great step, detection circuitry can follow load current's change at any time, adjusts zero pole and loop bandwidth according to load current's change to when improving LDO's transient response, guaranteed the high stability of loop. Moreover, the circuit provided by the application is simple in structure, only needs to be modified on the basis of a traditional structure, and design complexity is reduced.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (2)

1. An adaptive LDO circuit, comprising: a main body circuit, a detection circuit and a compensation circuit, wherein,
the main circuit is used for regulating the input voltage according to the reference voltage to obtain an output voltage;
the detection circuit is used for detecting the load current of the main circuit and obtaining compensation current information according to the load current;
the compensation circuit is used for adjusting the zero pole and the loop bandwidth of the main circuit according to the compensation current information so as to ensure the stability of a loop, wherein the zero pole comprises a dominant pole, a first dominant pole and a second dominant pole;
wherein the main body circuit includes: the circuit comprises a differential amplifier, a buffer, a voltage divider and a power tube;
the differential amplifier includes: a first PMOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a first N-type MOS transistor MN1, and a second N-type MOS transistor MN 2;
the buffer includes: a fifth P-type MOS transistor MP5 and a sixth P-type MOS transistor MP 6;
the voltage divider includes: an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, and an eleventh P-type MOS transistor MP 11;
the power tube includes: a seventh P-type MOS transistor MP 7;
the grid and the drain of the first P-type MOS tube MP1 are connected with a current source, and the source is connected with the power supply;
the gate of the second P-type MOS transistor MP2 and the gate of the fifth P-type MOS transistor MP5 are both connected to the gate of the first P-type MOS transistor MP1, the source of the second P-type MOS transistor MP2 and the source of the fifth P-type MOS transistor MP5 are both connected to the power supply, the drain of the second P-type MOS transistor MP2 is connected to the source of the third P-type MOS transistor MP3 and the source of the fourth P-type MOS transistor MP4, and the drain of the fifth P-type MOS transistor MP5 is connected to the source of the sixth P-type MOS transistor MP6 and the gate of the seventh P-type MOS transistor MP 7;
the gate of the third P-type MOS transistor MP3 is connected to the gate and the drain of the ninth P-type MOS transistor MP9, and the drain of the third P-type MOS transistor MP3 is connected to the drain and the gate of the first N-type MOS transistor MN1 and the gate of the second N-type MOS transistor MN 2;
the gate of the fourth P-type MOS transistor MP4 is connected to the reference voltage, and the drain of the fourth P-type MOS transistor MP 3578 and the drain of the second N-type MOS transistor MN2 are connected to the gate of the sixth P-type MOS transistor MP 6;
the source electrode of the first N-type MOS transistor MN1, the source electrode of the second N-type MOS transistor MN2 and the drain electrode of the sixth P-type MOS transistor MP6 are all grounded;
the source electrode of the seventh P-type MOS transistor MP7 is connected to the power supply, and the drain electrode is connected to the source electrode of the eighth P-type MOS transistor MP 8;
the gate and the drain of the eighth P-type MOS transistor MP8 are connected to the source of the ninth P-type MOS transistor MP 9;
the gate and the drain of the ninth P-type MOS transistor MP9 are connected to the source of the tenth P-type MOS transistor MP 10;
the drain of the tenth P-type MOS transistor MP10 is connected to the source of the eleventh P-type MOS transistor MP11, and the gate of the tenth P-type MOS transistor MP10 and the gate and the drain of the eleventh P-type MOS transistor MP11 are both grounded;
alternatively, the differential amplifier includes: a first PMOS transistor MP1, a second P-type MOS transistor MP2, an eighteenth P-type MOS transistor MP18, a nineteenth P-type MOS transistor MP19, a twentieth P-type MOS transistor MP20, a twenty-first P-type MOS transistor MP21, a twenty-second P-type MOS transistor MP22, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, an eighth N-type MOS transistor MN8, and a ninth N-type MOS transistor MN 9;
the buffer includes: a fifth P-type MOS transistor MP5 and a sixth P-type MOS transistor MP 6;
the voltage divider includes: a first resistor R1 and a second resistor R2;
the power tube includes: a seventh P-type MOS transistor MP 7;
the grid and the drain of the first P-type MOS tube MP1 are connected with a current source, and the source is connected with the power supply;
the gate of the second P-type MOS transistor MP2, the gate of the eighteenth P-type MOS transistor MP18, the gate of the first P-type MOS transistor MP1 and the gate of the fifth P-type MOS transistor MP5 are connected, the source of the second P-type MOS transistor MP2, the source of the fifth P-type MOS transistor MP5, the source of the seventh P-type MOS transistor MP7, the source of the eighteenth P-type MOS transistor MP18, the source of the nineteenth P-type MOS transistor MP19 and the source of the twenty-second P-type MOS transistor MP22 are all connected to the power supply, and the drain of the second P-type MOS transistor MP2 is connected to the drain, the gate of the first N-type MOS transistor MN1 and the gate of the second N-type MOS transistor MN 2;
the drain of the second N-type MOS transistor MN2 is connected to the source of the sixth N-type MOS transistor MN6 and the source of the ninth N-type MOS transistor MN9, and the source of the first N-type MOS transistor MN1 and the source of the second N-type MOS transistor MN2 are both grounded;
the drain electrode of the eighteenth P-type MOS transistor MP18 is connected to the source electrode of the twentieth P-type MOS transistor MP20 and the source electrode of the twenty-first P-type MOS transistor MP 21;
the gate of the twentieth P-type MOS transistor MP20 is connected to the gate and the drain of the nineteenth P-type MOS transistor MP19 and the drain of the sixth N-type MOS transistor MN6, the drain of the twentieth P-type MOS transistor MP20 is connected to the gate and the drain of the seventh N-type MOS transistor MN7 and the gate of the eighth N-type MOS transistor MN8, and the gate of the sixth N-type MOS transistor MN6 is connected to the reference voltage;
a drain electrode of the eighth N-type MOS transistor MN8 is connected to a drain electrode of the twenty-first P-type MOS transistor MP21 and a gate electrode of the sixth P-type MOS transistor MP6, and a source electrode of the eighth N-type MOS transistor MN8 and a source electrode of the seventh N-type MOS transistor MN7 are both grounded;
the gate of the twenty-first P-type MOS transistor MP21 is connected to the drain of the ninth N-type MOS transistor MN9 and the gate and the drain of the twenty-second P-type MOS transistor MP 22;
the drain of the fifth P-type MOS transistor MP5 is connected to the source of the sixth P-type MOS transistor MP6 and the gate of the seventh P-type MOS transistor MP7, the drain of the sixth P-type MOS transistor MP6 is grounded, and the drain of the seventh P-type MOS transistor MP7 is grounded through the first resistor R1 and the second resistor R2 in sequence;
the gate of the ninth N-type MOS transistor MN9 is connected to one end of the first resistor R1, which is far away from the drain of the seventh P-type MOS transistor MP 7;
the compensation circuit includes: a fifth N-type MOS transistor MN5, a fifteenth P-type MOS transistor MP15, a sixteenth P-type MOS transistor MP16, and a seventeenth P-type MOS transistor MP 17;
the source electrode of the fifteenth P-type MOS transistor MP15, the source electrode of the sixteenth P-type MOS transistor MP16 and the source electrode of the seventeenth P-type MOS transistor MP17 are all connected to the power supply;
the gate and the drain of the fifteenth P-type MOS transistor MP15 are connected to the drain of the fifth N-type MOS transistor MN5, the gate of the seventeenth P-type MOS transistor MP17 and the gate of the sixteenth P-type MOS transistor MP 16;
the drain electrode of the sixteenth P-type MOS tube MP16 is connected with the compensation input end of the main body circuit;
the drain electrode of the seventeenth P-type MOS transistor MP17 is connected to the drain electrode of the fifth P-type MOS transistor MP5 and the source electrode of the sixth P-type MOS transistor MP 6;
the grid electrode of the fifth N-type MOS transistor MN5 is connected with the compensation current information output end of the detection circuit, and the source electrode is grounded.
2. The adaptive LDO circuit of claim 1, wherein the detection circuit comprises: a twelfth P-type MOS transistor MP12, a thirteenth P-type MOS transistor MP13, a fourteenth P-type MOS transistor MP14, a third N-type MOS transistor MN3, and a fourth N-type MOS transistor MN 4;
a gate of the twelfth P-type MOS transistor MP12 is connected to a gate of the seventh P-type MOS transistor MP7, a source of the twelfth P-type MOS transistor MP12 is connected to the power supply, and a drain of the twelfth P-type MOS transistor MP12 is connected to a source of the thirteenth P-type MOS transistor MP 13;
a drain of the thirteenth P-type MOS transistor MP13 is connected to a gate and a drain of the third N-type MOS transistor MN3 and a gate of the fourth N-type MOS transistor MN4, a gate of the thirteenth P-type MOS transistor MP13 is connected to a gate and a drain of the fourteenth P-type MOS transistor MP14 and a drain of the fourth N-type MOS transistor MN4, and a source of the fourteenth P-type MOS transistor MP14 is connected to a drain of the seventh P-type MOS transistor MP 7;
the source electrode of the third N-type MOS transistor MN3 and the source electrode of the fourth N-type MOS transistor MN4 are both grounded.
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