CN114023278B

CN114023278B - Drive Buffer circuit without external capacitor and Buffer

Info

Publication number: CN114023278B
Application number: CN202111279630.3A
Authority: CN
Inventors: 许建超; 孙添平; 戴贵荣; 陈世超; 戴庆田
Original assignee: Shenzhen Aixiesheng Technology Co Ltd
Current assignee: Shenzhen Aixiesheng Technology Co Ltd
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2022-12-27
Anticipated expiration: 2041-10-28
Also published as: CN114023278A

Abstract

The invention provides a driving Buffer circuit without an external capacitor and a Buffer, which comprise an operational amplifier, a plurality of resistors and a multiplexer, wherein the operational amplifier is of a two-stage structure and comprises an input stage and an output stage, the output stage is provided with a plurality of output ends, each output end is respectively provided with an independent enabling switch and is respectively connected with resistor branches with different resistance values, input pins of the multiplexer are respectively connected with the resistor branches, and output pins are connected with the operational amplifier. When the invention drives a large capacitive load, the off-chip capacitor is not used, and the stability and the response speed can be kept very good.

Description

Drive Buffer circuit without external capacitor and Buffer

Technical Field

The present invention relates to a driving Buffer circuit, and more particularly, to a driving Buffer circuit and a Buffer without an external capacitor.

Background

Fig. 1 is a schematic diagram of a typical LCD Driver driving circuit in the prior art. Without loss of generality, only a small portion of the pixel points are drawn in the figure: each row has only 2 pixels for a total of 4 rows; where each pixel has 3 tft switches and capacitors (i.e., liquid crystal molecules) corresponding to R, G, B, respectively. The gates of each row of mos switches are controlled uniformly by a gck signal, which is a high voltage control signal, called gate line, typically +/-12V. One end of each column of mos switches is controlled by one s-line, and each s-line is driven by one buffer, which is called a data line. The voltage of each s-line is changed by continuously sending data, thereby realizing the display and refresh of the picture.

The other terminals of all the pixel capacitors, all connected together, are called VCOM terminal (common terminal), driven by one large Buffer, called VCOM _ Buffer. Of course, VCOM has the heaviest loading, since the capacitances (useful and parasitic) of the entire panel are all relative to this common terminal of VCOM. In general, the small panel total capacitance is on the order of 5-10nF and the medium panel total capacitance is 50-100nF. When the screen works, the panel capacitor is charged and discharged continuously, and the VCOM _ Buffer has large current drawing and sinking behaviors, so that high requirements are provided for the load carrying capacity and the response speed of the VCOM _ Buffer. Generally speaking, VCOM _ Buffer must have an off-chip capacitor to provide sufficient transient response capability, as shown in fig. 1, which is the mainstream solution.

However, off-chip capacitors pose cost, reliability, and PCB routing and area issues, and the current technological trend is to minimize the use of off-chip devices. Especially, the wearable equipment with small size has very tight space, needs to simplify materials as much as possible, and aims to achieve zero capacitance. Because the total panel capacitance is relatively small, small size screens are also most likely to achieve the "zero capacitance" goal.

Fig. 1 only illustrates the problem by taking VCOM buffer in LCD _ Driver chip as an example, and similar examples also include VREF _ TP buffer, VCG _ TP buffer, etc. in touch chip. For example, in an analog front-end detection circuit of a touch screen, the detection circuit is an array composed of hundreds of CA amplifiers and integrators, the CA amplifiers and the integrators are all switched capacitor circuits, and the CA amplifiers and the integrators use the same driving Buffer, so that the Buffer has a very large capacitive load.

Therefore, a driving Buffer circuit that does not use off-chip capacitance and can solve the problems of stability and transient response speed is urgently required.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a driving Buffer circuit and a Buffer without an external capacitor, so that when a large capacitive load is driven, an off-chip capacitor can not be used, and good stability and response speed can still be kept.

In order to achieve the purpose, the invention adopts the following specific technical scheme:

the utility model provides a drive Buffer circuit of no external electric capacity, includes that fortune is put, a plurality of resistance and multiplexer, fortune is put for the secondary structure, including input stage and output stage, and the output stage is equipped with a plurality of outputs, and every output is equipped with independent enabling switch respectively, is connected with the resistance branch road of different resistance values respectively, each resistance branch road is connected respectively to multiplexer's input pin, output pin with fortune is put and is connected.

Preferably, the operational amplifier is a class-AB operational amplifier.

Preferably, the resistance branch comprises a branch without resistance.

Preferably, the multiplexer includes a plurality of switches connected to the input pin, and different feedback points are selected by turning off the switches.

Preferably, the resistances of the resistors are the same.

Preferably, the resistances of the resistors are different.

Preferably, the number of the resistors isnThe output stage of the operational amplifier hasnAn output terminal, an input pin of the multiplexer is provided withnAnd (4) respectively.

A Buffer comprises any one of the driving Buffer circuits without external capacitors.

Preferably, the buffer is a VCOM buffer in an LCD _ Driver chip or a VREF _ TP buffer, a VCG _ TP buffer in a touch chip.

The invention has the beneficial effects that: when a large capacitive load is driven, off-chip capacitors are not used, and good stability and response speed can still be kept.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram of a typical LCD Driver driving circuit in the prior art;

FIG. 2 is the present inventionInvention of the inventionA schematic structural diagram of an embodiment of a driving Buffer circuit without an external capacitor;

FIG. 3 is a schematic view ofHaving 3 outputsThe circuit structure schematic diagram of the class-AB operational amplifier;

fig. 4 is a schematic diagram of one of the switching strategies of fig. 2 and its corresponding small-signal equivalent circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Other embodiments, which can be derived by one of ordinary skill in the art from the embodiments given herein without any creative effort, shall fall within the protection scope of the present invention.

The invention provides a driving Buffer circuit without an external capacitor, which comprises an operational amplifier, a plurality of resistors and a multi-path selector, wherein the operational amplifier is of a two-stage structure and comprises an input stage and an output stage, the output stage is provided with a plurality of output ends, each output end is respectively provided with an independent enabling switch and is respectively connected with resistor branches with different resistance values, input pins of the multi-path selector are respectively connected with the resistor branches, and output pins are connected with the operational amplifier.

Preferably, the operational amplifier is a class-AB operational amplifier.

Preferably, the resistive branch comprises a branch without resistance. The resistances of the resistors are the same or different.Resistance (RC) N, the output stage of the operational amplifier has n output terminals, n input pins of the multiplexer are provided, and n is greater than 1 An integer number.

Preferably, the multiplexer includes a plurality of switches, the switches being connected to the input pins, and different feedback points are selected by turning off the switches.

The present invention is explained in detail below by way of example, as shown in fig. 2-3.

The invention provides a circuit for driving a Buffer without an external capacitor, which consists of a class-AB operational amplifier with 3 outputs, a plurality of resistors (R0/R1/R2 in the figure) and a multiplexer. Wherein the operational amplifier of class-AB is a 2-level structure: the circuit comprises an input stage and an output stage (also called a driving stage), wherein the output stage is provided with 3 outputs, each output is identical in size and is provided with an independent enabling switch, and a specific circuit is shown in figure 3.

The enable switch of the output stage drv0 is s0 and the output is resistor-free.

The enable switch of the output stage drv1 is s1 and outputs the series resistance R0.

The enable switch of output stage drv2 is s2, the output is connected in series with resistors R1 and R2.

s3/s4/s5 constitutes a 3.

The resistor connected in series on the output path aims to form a zero point of a left half plane with a load capacitor (which is large and is 2 orders of magnitude smaller than an off-chip capacitor) so as to realize zero point compensation. The zero point can increase the phase margin and the bandwidth, and the stability problem under the condition of no external capacitor is solved.

Therefore, 3 switches s0/s1/s2 are used for selecting the output stage, 3 switches s3/s4/s5 are used for selecting different feedback points, and the 6 switches are completely independent, so that flexible and changeable configuration modes can be realized to adapt to different load capacitance sizes and occasions. For example, assume R0= R1= R2=30Ohm:

for the structure shown in fig. 2 of the present invention, at least one branch without a resistor is included, and zero-point compensation is also achieved by selecting the combination of number 1, that is, the switching combination of s0+ s3, but in this configuration, the power tube output has no any resistor, and there is no problem that the power tube is limited by the resistor, so that the structure shown in fig. 2 has a faster charging and discharging speed under the same power tube size.

When the combination of s0+ s3 is only one set of power tubes drv0 and the charge and discharge speed is not yet sufficient, a combination of s0+ s1+ s3 or s0+ s1+ s2+ s3 may be further selected. Although the drv1 output has a reduced over-current capability due to the resistor R0 connected in series, and the drv2 output has a reduced over-current capability due to the resistor R1+ R2 connected in series, the reduction is only relative. By connecting drv0+ drv1+ drv2 in parallel, the driving capability can be greatly improved, although 3x effect is not available and > 2x effect can be achieved.

Likewise, fig. 2 may select number 4, i.e., s1+ s4, when a 30Ohm zero point compensation resistance scheme is desired. The invention has no redundant resistor connected in series on the power tube path, and has stronger overcurrent capacity and faster charge-discharge speed.

Theoretical analysis was performed on the zero compensation resistance of No. 5 as follows:

as shown in fig. 4 (a), the circuit of fig. 2 is configured to employ the switching strategy of number 5. Fig. 4 (b) is a corresponding small-signal equivalent circuit, in which the input stage parameters are denoted by the reference numeral "1" and the output stage parameters are denoted by the reference numeral "2". Derived, the loop gain expression is as follows:

wherein:

A0＝gm1·gm2·ro1·ro2

here, p1 is the dominant pole, located inside the operational amplifier (output of the input stage); p2 is the secondary pole and is located outside the op-amp (the output of the driver stage). ro2 is the drive stage power tube internal resistance, typically in the order of hundreds of ohms, while R is in the order of tens of ohms.

As can be seen from the expression, the whole effect is equivalent to that 2 power tubes are connected in parallel (therefore, the output impedance is halved by ro 2/2), and the zero compensation resistor is equivalent to halved by (R/2).

By simple derivation, the expression of the phase margin can be proved as follows:

assume that for the combination of number 4 (s 1+ s 4):

wz =2gbw, wp2= gbw/4, pm =90 ° + atan (1/2) -atran (4) =40.6 ° f

When switching to the combination of number 5 (s 1+ s0+ s 4) is:

wz =4gbw, wp2= gbw/2, pm =90 ° + atan (1/4) -atran (2) =40.6 °

It can be seen that when switching to the combination No. 5, although the equivalent zero resistance is halved, resulting in a doubling of the zero frequency, the phase margin is not reduced, since the pole frequency p2 is also likewise doubled!

The core idea of the patent is illustrated in fig. 2 by taking 3 output branches as an example, and is not limited to the number of branches in practice, 2 or n branches are all possible, and the multiplexer needs to be changed accordingly.

The invention also provides a Buffer which comprises any one of the driving Buffer circuits without the external capacitor. The buffer is a VCOM buffer in an LCD _ Driver chip or a VREF _ TP buffer and a VCG _ TP buffer in a touch chip.

The invention has the beneficial effects that:

1) The zero capacitance design of the driving buffer is realized;

2) The size of the zero point can be flexibly controlled to adapt to different sizes of load capacitors;

3) The number of the driving tubes can be flexibly controlled to meet different requirements on the building speed;

4) No redundant resistor is connected in series with the current path of the power tube, so that the driving capability is lossless;

5) The scheme is simple and easy to implement, and the power consumption/area cost is low.

In light of the foregoing description of the preferred embodiments of the present invention, those skilled in the art can now make various alterations and modifications without departing from the scope of the invention. The technical scope of the present invention is not limited to the contents of the specification, and must be determined according to the scope of the claims.

Claims

1. A driving Buffer circuit without an external capacitor is characterized by comprising an operational amplifier, a plurality of resistors and a multi-path selector, wherein the operational amplifier is of a two-stage structure and comprises an input stage and an output stage, the output stage is provided with a plurality of output ends, each output end is respectively provided with an independent enable switch and is respectively connected with resistor branches with different resistance values, input pins of the multi-path selector are respectively connected with the resistor branches, and output pins are connected with the operational amplifier;

the output stage has 3 outputs, the enable switch of the output stage drv0 is s0, and the outputs have no resistance; the enable switch of the output stage drv1 is s1, and the output is connected with a resistor R0 in series; the enable switch of the output stage drv2 is s2, and the output is connected with resistors R1 and R2 in series; s3/s4/s5 forms a multi-way selection switch of 3.

2. The driving Buffer circuit without external capacitor as claimed in claim 1, wherein the operational amplifier is a class-AB operational amplifier.

3. The driving Buffer circuit without external capacitors as claimed in claim 1, wherein the resistive branch comprises a branch without resistors.

4. The driving Buffer circuit without external capacitors as claimed in claim 1, wherein the multiplexer comprises a plurality of switches, the switches are connected to the input pins, and different feedback points are selected by turning off the switches.

5. The driving Buffer circuit without the external capacitor as claimed in claim 1, wherein the resistances of the resistors are the same.

6. The driving Buffer circuit without external capacitors as claimed in claim 1, wherein the resistors have different resistances.

7. The driving Buffer circuit without external capacitors as claimed in any one of claims 1 to 6, wherein the number of the resistors is n, the output stage of the operational amplifier has n output terminals, and the input pins of the multiplexer are n.

8. A Buffer comprising the driving Buffer circuit without external capacitors as claimed in any one of claims 1 to 6.

9. The buffer of claim 8, wherein the buffer is a VCOM buffer in an LCD Driver chip or a VREF _ TP buffer, VCG _ TP buffer in a touch chip.