WO2024001429A1 - System-on-wafer packaging structure - Google Patents

System-on-wafer packaging structure Download PDF

Info

Publication number
WO2024001429A1
WO2024001429A1 PCT/CN2023/088509 CN2023088509W WO2024001429A1 WO 2024001429 A1 WO2024001429 A1 WO 2024001429A1 CN 2023088509 W CN2023088509 W CN 2023088509W WO 2024001429 A1 WO2024001429 A1 WO 2024001429A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
rewiring
plastic
chip
rewiring structure
Prior art date
Application number
PCT/CN2023/088509
Other languages
French (fr)
Chinese (zh)
Inventor
***
曹立强
Original Assignee
华进半导体封装先导技术研发中心有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华进半导体封装先导技术研发中心有限公司 filed Critical 华进半导体封装先导技术研发中心有限公司
Publication of WO2024001429A1 publication Critical patent/WO2024001429A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

Definitions

  • the present application relates to the field of wafer integration technology, and specifically to an on-wafer system packaging structure.
  • the number of I/Os on the core computing wafer of the on-chip system is huge, reaching more than one million levels, which is more than two orders of magnitude higher than the current advanced packaging, and the heterogeneous prefabricated parts integrated with the core computing wafer have a variety of digital/analog power supplies. Therefore, taking into account the practical problems of coexistence of massive wiring and multiple power planes, on-wafer systems have fine interconnection requirements across the chip scale. At the same time, the number of wiring layers on the carrier wafer has extremely high requirements.
  • the technical problem to be solved by this application is to overcome the limitations of the on-wafer system packaging structure in the prior art. Defects with poor reliability are thus provided, thereby providing an on-wafer system packaging structure.
  • the present application provides a system-on-wafer packaging structure, which includes: a plastic wafer having a receiving groove; a bridge chip located in the receiving groove; and a heavy-duty chip located on one side of the plastic wafer and the bridge chip.
  • a wiring structure, the rewiring structure is connected to the front side of the bridge chip; a plurality of first chips located on the side of the rewiring structure away from the plastic wafer; at least partially between the adjacent first chips Chip interconnects via rewiring structures and bridges.
  • the front surface of the bridge chip is provided with a first bonding pad and a second bonding pad
  • the rewiring structure includes a first wiring path and a second wiring path arranged at intervals, and the first wiring path is connected to the first bonding path respectively.
  • the pad is electrically connected to one of the adjacent first chips
  • the second wiring path is electrically connected to the second pad and the other of the adjacent first chips respectively.
  • the rewiring structure includes several rewiring layers arranged in a direction perpendicular to the surface of the plastic wafer, and the number of the rewiring layers is less than or equal to 5 layers.
  • system-on-wafer packaging structure further includes: a plastic sealing layer located on a side of the rewiring structure away from the plastic sealing wafer, and the plastic sealing layer covers the first chip.
  • the system-on-wafer packaging structure further includes: a conductive member located in the plastic wafer; a power supply unit located on a side of the plastic wafer away from the rewiring structure; the conductive member is respectively connected to the The rewiring structure is electrically connected to the power supply unit.
  • system-on-wafer packaging structure further includes: a heat dissipation unit located on a side of the plastic encapsulation layer facing away from the rewiring structure.
  • the on-wafer system packaging structure further includes: a conductive member located in the plastic sealing layer on the side of the first chip; a power supply unit located on the side of the plastic sealing layer away from the rewiring structure; the on-chip system packaging structure
  • the conductive member is electrically connected to the rewiring structure and the power supply unit respectively. connect.
  • system-on-wafer packaging structure further includes: a heat dissipation unit located on a side of the plastic package wafer facing away from the rewiring structure.
  • the rewiring structure includes: several photolithography wiring areas; several first chips are provided on the side of each photolithography wiring area facing away from the plastic wafer; non-adjacent photolithography wiring areas The adjacent first chips are interconnected through a rewiring structure and a bridge chip.
  • the on-wafer system packaging structure includes: a plastic wafer with a receiving groove; a bridge chip located in the receiving groove; and a bridging chip located on one side of the plastic wafer and the bridge chip.
  • a rewiring structure, the rewiring structure is connected to the front side of the bridge chip; a plurality of first chips located on the side of the rewiring structure away from the plastic wafer; at least part of the adjacent first chips They are interconnected through rewiring structures and bridge chips.
  • the adjacent first chips are interconnected through bridge chips, and the bridge chips are used to replace part of the signal interconnections, which reduces the number of layers of the rewiring structure, avoids warping and bending of the on-wafer system packaging structure, and at the same time avoids on-wafer
  • the splicing interface between different photolithography areas in the system improves the reliability of the on-wafer system packaging structure.
  • Figure 1 is a schematic diagram of the packaging structure of a system on a chip in an embodiment of the present application
  • Figure 2 is a schematic diagram of the packaging structure of the on-wafer system in Embodiment 2 of the present application;
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components.
  • connection or integral connection
  • connection or integral connection
  • connection can be a mechanical connection or an electrical connection
  • it can be a direct connection or an indirect connection through an intermediate medium
  • it can be an internal connection between two components.
  • specific meanings of the above terms in this application can be understood on a case-by-case basis.
  • this embodiment provides a system-on-wafer packaging structure, including: a plastic wafer 1 having an accommodating groove; a bridge chip 2 located in the accommodating groove; The rewiring structure 5A on the side of the circle 1 and the bridge chip 2 is connected to the front side of the bridge chip 2; several rewiring structures 5A are located on the side facing away from the plastic wafer 1.
  • One chip 3; at least part of the adjacent first chips 3 are interconnected through the rewiring structure 5A and the bridge chip 2.
  • the adjacent first chips 3 are interconnected through the bridge chip 2, and the bridge chip 2 is used to replace part of the signal interconnection, thereby reducing the number of layers of the rewiring structure 5A and avoiding the on-wafer system packaging structure. Warping and bending improve the reliability of the on-chip system packaging structure.
  • the first chip 3 includes a computing chip.
  • the front surface of the bridge chip 2 is provided with a first bonding pad and a second bonding pad
  • the rewiring structure 5A includes a first wiring path and a second wiring path arranged at intervals.
  • the first wiring paths are respectively The first bonding pad is electrically connected to one of the adjacent first chips 3, and the second wiring path is respectively connected to the second bonding pad and the other of the adjacent first chips 3.
  • One chip has 3 electrical connections. In this way, the electrical path of the adjacent first chips 3 interconnected through the rewiring structure 5A and the bridge chip 2 is: one first chip 3 is electrically connected to the first pad, and then enters the bridge chip 2 from the first pad. The second pad comes out and is electrically connected to another first chip 3 .
  • the front surface of the first chip 3 has second micro-bumps, and the side surface of the rewiring structure 5A facing away from the plastic wafer 1 is provided with first micro-bumps, first micro-bumps and second micro-bumps. spot welding together.
  • the system-on-wafer packaging structure further includes: an underfill layer 4 located between the first chip 3 and the redistribution structure 5A and surrounding the first micro-bumps and the second micro-bumps.
  • the rewiring structure 5A includes several rewiring layers arranged in a direction perpendicular to the surface of the plastic wafer 1 .
  • the number of rewiring layers is less than or equal to 5 layers, for example Be 1st floor, 2nd floor, 3rd floor, 4th floor or 5th floor.
  • the system-on-wafer packaging structure also includes: a plastic packaging layer 6 located on the side of the rewiring structure 5A away from the plastic packaging wafer 1 , and the plastic packaging layer 6 covers the first chip 3 .
  • the plastic sealing layer 6 also covers the underfill rubber layer 4 .
  • the on-wafer system packaging structure also includes: a conductive member 7A located in the plastic wafer 1; a power supply unit 8A located on the side of the plastic wafer 1 away from the rewiring structure 5A; the conductive member 7A is respectively connected to The rewiring structure 5A and the power supply unit 8A are electrically connected.
  • the system-on-wafer packaging structure further includes: a heat dissipation unit 9A located on the side of the plastic encapsulation layer 6 facing away from the rewiring structure 5A.
  • the heat dissipation unit 9A includes a plurality of spaced heat dissipation fins.
  • the rewiring structure 5A includes: several photolithography wiring areas; several first chips 3 are provided on the side of each photolithography wiring area away from the plastic wafer 1; for adjacent The adjacent first chips 3 are interconnected through the rewiring structure 5A and the bridge chip 2 on the photolithography wiring area.
  • a photolithography wiring area refers to the area where one photolithography is performed during the process of forming the rewiring structure 5A. The formation of the rewiring structure requires multiple photolithography, and the corresponding pattern of each photolithography is consistent.
  • the interconnections of the rewiring structure 5A Since the number of rewiring layers in the rewiring structure 5A is reduced, the interconnections of the rewiring structure 5A The density is reduced, and fine interconnections in different photolithography wiring areas can be satisfied. There is no splicing interface for graphics in different photolithography wiring areas, which improves the accuracy of the circuit.
  • the on-wafer system packaging structure also includes: a conductive member 7B located in the plastic sealing layer 6 on the side of the first chip 3; The power supply unit 8B on one side of the rewiring structure 5B; the conductive member 7B is electrically connected to the rewiring structure 5B and the power supply unit 8B respectively.
  • system-on-wafer packaging structure further includes: a heat dissipation unit 9B located on the side of the plastic wafer 1 away from the rewiring structure 5B.
  • the heat dissipation unit 9B covers one side of the entire plastic wafer 1.
  • the heat dissipation unit 9B can reduce the heat of the plastic wafer 1 in time when the chips in the plastic wafer 1 are interconnected, ensuring that Signal interconnections between on-wafer system-on-chip prefabs operate normally.
  • the rewiring structure 5B includes several rewiring layers arranged in a direction perpendicular to the surface of the plastic wafer 1 .
  • the number of rewiring layers is less than or equal to 5 layers, for example Be 1st floor, 2nd floor, 3rd floor, 4th floor or 5th floor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Packaging Frangible Articles (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present application provides a system-on-wafer packaging structure, comprising: a plastic package wafer provided with an accommodating groove; a bridging chip located in the accommodating groove; a rewiring structure located on one side of the plastic package wafer and one side of the bridging chip and connected to the front surface of the bridging chip; and a plurality of first chips located on the side of the rewiring structure away from the plastic package wafer, wherein at least some adjacent first chips are interconnected by means of the rewiring structure and the bridging chip. The reliability of the system-on-wafer packaging structure provided by the present application can be improved.

Description

一种晶上***封装结构A kind of on-wafer system packaging structure
相关申请的交叉引用Cross-references to related applications
本申请要求在2022年06月30日提交中国专利局、申请号为202210770601.5、申请名称为“一种晶上***封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims priority to the Chinese patent application filed with the China Patent Office on June 30, 2022, with the application number 202210770601.5 and the application title "A kind of on-chip system packaging structure", the entire content of which is incorporated into this application by reference. .
技术领域Technical field
本申请涉及晶圆集成技术领域，具体涉及一种晶上***封装结构。The present application relates to the field of wafer integration technology, and specifically to an on-wafer system packaging structure.
背景技术Background technique
超级计算机和人工智能的不断发展，对于高效运算(HPC)芯片的升级渴求从未停歇，同时***集成技术和晶圆级封装工艺也在近些年成为主流芯片厂商的重点发展方向，在这种需求与技术共同驱使下，晶上***(system on wafer)的概念近期得到超算领域的较大关注。简单来说，晶上***就是将一定数量的计算芯片集成到一整张晶圆上作为一个整体，形成具有超高效能(HPC)芯片***。晶上***的核心计算晶圆I/O数量庞大，达百万以上级别，较目前先进封装高出两个数量级以上，且核心计算晶圆集成的异构预制件存在多种数字/模拟的电源等级需求，因此综合考虑到海量布线与多电源平面共存的现实问题，晶上***存在着跨越芯片尺度的精细互连需求，同时载板晶圆的布线层数有着极高的要求。With the continuous development of supercomputers and artificial intelligence, the desire for high-efficiency computing (HPC) chip upgrades has never stopped. At the same time, system integration technology and wafer-level packaging technology have also become the key development directions of mainstream chip manufacturers in recent years. In this kind of Driven by both demand and technology, the concept of system on wafer has recently received greater attention in the supercomputing field. Simply put, an on-wafer system integrates a certain number of computing chips onto a whole wafer as a whole to form an ultra-high performance (HPC) chip system. The number of I/Os on the core computing wafer of the on-chip system is huge, reaching more than one million levels, which is more than two orders of magnitude higher than the current advanced packaging, and the heterogeneous prefabricated parts integrated with the core computing wafer have a variety of digital/analog power supplies. Therefore, taking into account the practical problems of coexistence of massive wiring and multiple power planes, on-wafer systems have fine interconnection requirements across the chip scale. At the same time, the number of wiring layers on the carrier wafer has extremely high requirements.
当传统的2.5D转接板的再布线层数达到5层以后，翘曲值会增大，导致工艺无法正常进行，无法实现更高复杂度的信号互连，会产生严重的可靠性问题。When the number of rewiring layers of a traditional 2.5D adapter board reaches 5, the warpage value will increase, causing the process to fail to proceed normally, making it impossible to achieve higher-complexity signal interconnections, and causing serious reliability problems.
发明内容Contents of the invention
本申请要解决的技术问题在于克服现有技术中晶上***封装结构的可 靠性较差的缺陷，从而提供一种晶上***封装结构。The technical problem to be solved by this application is to overcome the limitations of the on-wafer system packaging structure in the prior art. Defects with poor reliability are thus provided, thereby providing an on-wafer system packaging structure.
本申请提供一种晶上***封装结构，包括：塑封晶圆，所述塑封晶圆中具有容纳槽；位于所述容纳槽中的桥接芯片；位于所述塑封晶圆和桥接芯片一侧的重布线结构，所述重布线结构与所述桥接芯片的正面连接；位于所述重布线结构背离所述塑封晶圆一侧的若干个第一芯片；至少部分相邻的所述第一芯片之间通过重布线结构和桥接芯片互连。The present application provides a system-on-wafer packaging structure, which includes: a plastic wafer having a receiving groove; a bridge chip located in the receiving groove; and a heavy-duty chip located on one side of the plastic wafer and the bridge chip. A wiring structure, the rewiring structure is connected to the front side of the bridge chip; a plurality of first chips located on the side of the rewiring structure away from the plastic wafer; at least partially between the adjacent first chips Chip interconnects via rewiring structures and bridges.
可选的，所述桥接芯片的正面设置有第一焊盘和第二焊盘，所述重布线结构包括间隔设置的第一布线路径和第二布线路径，第一布线路径分别与第一焊盘和相邻的所述第一芯片中的一个第一芯片电连接，第二布线路径分别与第二焊盘和相邻的所述第一芯片中的另一个第一芯片电连接。Optionally, the front surface of the bridge chip is provided with a first bonding pad and a second bonding pad, and the rewiring structure includes a first wiring path and a second wiring path arranged at intervals, and the first wiring path is connected to the first bonding path respectively. The pad is electrically connected to one of the adjacent first chips, and the second wiring path is electrically connected to the second pad and the other of the adjacent first chips respectively.
可选的，所述重布线结构包括垂直于所述塑封晶圆表面的方向上设置的若干层重布线层，所述若干层重布线层的层数小于或等于5层。Optionally, the rewiring structure includes several rewiring layers arranged in a direction perpendicular to the surface of the plastic wafer, and the number of the rewiring layers is less than or equal to 5 layers.
可选的，晶上***封装结构还包括：位于所述重布线结构背离所述塑封晶圆一侧的塑封层，塑封层包覆所述第一芯片。Optionally, the system-on-wafer packaging structure further includes: a plastic sealing layer located on a side of the rewiring structure away from the plastic sealing wafer, and the plastic sealing layer covers the first chip.
可选的，晶上***封装结构还包括：位于所述塑封晶圆中的导电件；位于所述塑封晶圆背离所述重布线结构一侧的电源供给单元；所述导电件分别与所述重布线结构和所述电源供给单元电连接。Optionally, the system-on-wafer packaging structure further includes: a conductive member located in the plastic wafer; a power supply unit located on a side of the plastic wafer away from the rewiring structure; the conductive member is respectively connected to the The rewiring structure is electrically connected to the power supply unit.
可选的，晶上***封装结构还包括：位于所述塑封层背离所述重布线结构一侧的散热单元。Optionally, the system-on-wafer packaging structure further includes: a heat dissipation unit located on a side of the plastic encapsulation layer facing away from the rewiring structure.
可选的，晶上***封装结构还包括：位于所述第一芯片侧部的塑封层中的导电件；位于所述塑封层背离所述重布线结构一侧电源供给单元；晶上***封装结构所述导电件分别与所述重布线结构和所述电源供给单元电 连接。Optionally, the on-wafer system packaging structure further includes: a conductive member located in the plastic sealing layer on the side of the first chip; a power supply unit located on the side of the plastic sealing layer away from the rewiring structure; the on-chip system packaging structure The conductive member is electrically connected to the rewiring structure and the power supply unit respectively. connect.
可选的，晶上***封装结构还包括：位于所述塑封晶圆背离所述重布线结构一侧的散热单元。Optionally, the system-on-wafer packaging structure further includes: a heat dissipation unit located on a side of the plastic package wafer facing away from the rewiring structure.
可选的，所述重布线结构包括：若干个光刻布线区域；每个光刻布线区域背离所述塑封晶圆的一侧均设置有若干个第一芯片；不相邻的光刻布线区域上的相邻的第一芯片，对于相邻的所述第一芯片之间通过重布线结构和桥接芯片互连。Optionally, the rewiring structure includes: several photolithography wiring areas; several first chips are provided on the side of each photolithography wiring area facing away from the plastic wafer; non-adjacent photolithography wiring areas The adjacent first chips are interconnected through a rewiring structure and a bridge chip.
本申请的有益效果在于：The beneficial effects of this application are:
本申请技术方案提供的晶上***封装结构，包括：塑封晶圆，所述塑封晶圆中具有容纳槽；位于所述容纳槽中的桥接芯片；位于所述塑封晶圆和桥接芯片一侧的重布线结构，所述重布线结构与所述桥接芯片的正面连接；位于所述重布线结构背离所述塑封晶圆一侧的若干个第一芯片；至少部分相邻的所述第一芯片之间通过重布线结构和桥接芯片互连。将相邻的所述第一芯片通过桥接芯片互连，用桥接芯片代替部分的信号互连，减少了重布线结构的层数，避免晶上***封装结构翘起弯曲，同时，避免了晶上***内不同光刻区域间的拼接界面，提高了晶上***封装结构的可靠性。The on-wafer system packaging structure provided by the technical solution of this application includes: a plastic wafer with a receiving groove; a bridge chip located in the receiving groove; and a bridging chip located on one side of the plastic wafer and the bridge chip. A rewiring structure, the rewiring structure is connected to the front side of the bridge chip; a plurality of first chips located on the side of the rewiring structure away from the plastic wafer; at least part of the adjacent first chips They are interconnected through rewiring structures and bridge chips. The adjacent first chips are interconnected through bridge chips, and the bridge chips are used to replace part of the signal interconnections, which reduces the number of layers of the rewiring structure, avoids warping and bending of the on-wafer system packaging structure, and at the same time avoids on-wafer The splicing interface between different photolithography areas in the system improves the reliability of the on-wafer system packaging structure.
附图说明Description of drawings
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly explain the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description The drawings illustrate some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.
图1为本申请实施例中1晶上***封装结构的示意图； Figure 1 is a schematic diagram of the packaging structure of a system on a chip in an embodiment of the present application;
图2为本申请实施例2中晶上***封装结构的示意图；Figure 2 is a schematic diagram of the packaging structure of the on-wafer system in Embodiment 2 of the present application;
附图标记说明：
1-塑封晶圆；2-桥接芯片；3-第一芯片；4-底填胶层；5A-重布线结构；
6-塑封层；7A-导电件；8A-电源供给单元；9A-散热单元；5B-重布线结构；7B-导电件；8B-电源供给单元；9B-散热单元。Explanation of reference symbols:
1-Plastic wafer; 2-Bridge chip; 3-First chip; 4-Underfill layer; 5A-Rewiring structure;
6-Plastic sealing layer; 7A-Conductive parts; 8A-Power supply unit; 9A-Heat dissipation unit; 5B-Rewiring structure; 7B-Conductive parts; 8B-Power supply unit; 9B-Heat dissipation unit.
具体实施方式Detailed ways
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms “first”, “second” and “third” are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。 In the description of this application, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood on a case-by-case basis.
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
实施例1Example 1
参考图1，本实施例提供一种晶上***封装结构，包括：塑封晶圆1，所述塑封晶圆1中具有容纳槽；位于所述容纳槽中的桥接芯片2；位于所述塑封晶圆1和桥接芯片2一侧的重布线结构5A，所述重布线结构5A与所述桥接芯片2的正面连接；位于所述重布线结构5A背离所述塑封晶圆1一侧的若干个第一芯片3；至少部分相邻的所述第一芯片3之间通过重布线结构5A和桥接芯片2互连。Referring to Figure 1 , this embodiment provides a system-on-wafer packaging structure, including: a plastic wafer 1 having an accommodating groove; a bridge chip 2 located in the accommodating groove; The rewiring structure 5A on the side of the circle 1 and the bridge chip 2 is connected to the front side of the bridge chip 2; several rewiring structures 5A are located on the side facing away from the plastic wafer 1. One chip 3; at least part of the adjacent first chips 3 are interconnected through the rewiring structure 5A and the bridge chip 2.
在本实施例中，将相邻的所述第一芯片3通过桥接芯片2互连，用桥接芯片2代替部分的信号互连，减少了重布线结构5A的层数，避免晶上***封装结构翘起弯曲，提高了晶上***封装结构的可靠性。In this embodiment, the adjacent first chips 3 are interconnected through the bridge chip 2, and the bridge chip 2 is used to replace part of the signal interconnection, thereby reducing the number of layers of the rewiring structure 5A and avoiding the on-wafer system packaging structure. Warping and bending improve the reliability of the on-chip system packaging structure.
在一个实施例中，所述第一芯片3包括计算芯片。In one embodiment, the first chip 3 includes a computing chip.
在一个实施例中，所述桥接芯片2的正面设置有第一焊盘和第二焊盘，所述重布线结构5A包括间隔设置的第一布线路径和第二布线路径，第一布线路径分别与第一焊盘和相邻的所述第一芯片3中的一个第一芯片3电连接，第二布线路径分别与第二焊盘和相邻的所述第一芯片3中的另一个第一芯片3电连接。这样通过重布线结构5A和桥接芯片2互连的相邻的所述第一芯片3的电学路径为：一个第一芯片3电连接第一焊盘，从第一焊盘进入桥接芯片2之后从第二焊盘出来，再电连接另一个第一芯片3。In one embodiment, the front surface of the bridge chip 2 is provided with a first bonding pad and a second bonding pad, and the rewiring structure 5A includes a first wiring path and a second wiring path arranged at intervals. The first wiring paths are respectively The first bonding pad is electrically connected to one of the adjacent first chips 3, and the second wiring path is respectively connected to the second bonding pad and the other of the adjacent first chips 3. One chip has 3 electrical connections. In this way, the electrical path of the adjacent first chips 3 interconnected through the rewiring structure 5A and the bridge chip 2 is: one first chip 3 is electrically connected to the first pad, and then enters the bridge chip 2 from the first pad. The second pad comes out and is electrically connected to another first chip 3 .
所述第一芯片3的正面具有第二微凸点，所述重布线结构5A背离所述塑封晶圆1的一侧表面设置有第一微凸点，第一微凸点和第二微凸点焊接 在一起。The front surface of the first chip 3 has second micro-bumps, and the side surface of the rewiring structure 5A facing away from the plastic wafer 1 is provided with first micro-bumps, first micro-bumps and second micro-bumps. spot welding together.
所述晶上***封装结构还包括：位于所述第一芯片3和所述重布线结构5A之间且包围所述第一微凸点和第二微凸点的底填胶层4。The system-on-wafer packaging structure further includes: an underfill layer 4 located between the first chip 3 and the redistribution structure 5A and surrounding the first micro-bumps and the second micro-bumps.
所述重布线结构5A包括垂直于所述塑封晶圆1表面的方向上设置的若干层重布线层，在一个实施例中，所述若干层重布线层的层数小于或等于5层，例如为1层、2层、3层、4层或5层。The rewiring structure 5A includes several rewiring layers arranged in a direction perpendicular to the surface of the plastic wafer 1 . In one embodiment, the number of rewiring layers is less than or equal to 5 layers, for example Be 1st floor, 2nd floor, 3rd floor, 4th floor or 5th floor.
晶上***封装结构还包括：位于所述重布线结构5A背离所述塑封晶圆1一侧的塑封层6，塑封层6包覆所述第一芯片3。所述塑封层6还包覆底填胶层4。The system-on-wafer packaging structure also includes: a plastic packaging layer 6 located on the side of the rewiring structure 5A away from the plastic packaging wafer 1 , and the plastic packaging layer 6 covers the first chip 3 . The plastic sealing layer 6 also covers the underfill rubber layer 4 .
晶上***封装结构还包括：位于所述塑封晶圆1中的导电件7A；位于所述塑封晶圆1背离所述重布线结构5A一侧的电源供给单元8A；所述导电件7A分别与所述重布线结构5A和所述电源供给单元8A电连接。The on-wafer system packaging structure also includes: a conductive member 7A located in the plastic wafer 1; a power supply unit 8A located on the side of the plastic wafer 1 away from the rewiring structure 5A; the conductive member 7A is respectively connected to The rewiring structure 5A and the power supply unit 8A are electrically connected.
在一个实施例中，晶上***封装结构还包括：位于所述塑封层6背离所述重布线结构5A一侧的散热单元9A。所述散热单元9A包括若干个间隔的散热鳍片。In one embodiment, the system-on-wafer packaging structure further includes: a heat dissipation unit 9A located on the side of the plastic encapsulation layer 6 facing away from the rewiring structure 5A. The heat dissipation unit 9A includes a plurality of spaced heat dissipation fins.
在一个实施例中，所述重布线结构5A包括：若干个光刻布线区域；每个光刻布线区域背离所述塑封晶圆1的一侧均设置有若干个第一芯片3；对于相邻的光刻布线区域上的相邻的第一芯片3，相邻的所述第一芯片3之间通过重布线结构5A和桥接芯片2互连。一个光刻布线区域指的是：在形成重布线结构5A的过程中，一次光刻所在的区域。重布线结构的形成需要进行多次光刻，每一次光刻对应的图形一致。In one embodiment, the rewiring structure 5A includes: several photolithography wiring areas; several first chips 3 are provided on the side of each photolithography wiring area away from the plastic wafer 1; for adjacent The adjacent first chips 3 are interconnected through the rewiring structure 5A and the bridge chip 2 on the photolithography wiring area. A photolithography wiring area refers to the area where one photolithography is performed during the process of forming the rewiring structure 5A. The formation of the rewiring structure requires multiple photolithography, and the corresponding pattern of each photolithography is consistent.
由于重布线结构5A中的重布线层的数量减少，重布线结构5A的互连 密度降低，不同的光刻布线区域的精细互连能得到满足，不同的光刻布线区域的图形不存在拼接界面，提高线路的精度。Since the number of rewiring layers in the rewiring structure 5A is reduced, the interconnections of the rewiring structure 5A The density is reduced, and fine interconnections in different photolithography wiring areas can be satisfied. There is no splicing interface for graphics in different photolithography wiring areas, which improves the accuracy of the circuit.
实施例2Example 2
参考图2，本实施例与实施例1的区别在于：晶上***封装结构还包括：位于所述第一芯片3侧部的塑封层6中的导电件7B；位于所述塑封层6背离所述重布线结构5B一侧电源供给单元8B；所述导电件7B分别与所述重布线结构5B和所述电源供给单元8B电连接。Referring to Figure 2, the difference between this embodiment and Embodiment 1 is that the on-wafer system packaging structure also includes: a conductive member 7B located in the plastic sealing layer 6 on the side of the first chip 3; The power supply unit 8B on one side of the rewiring structure 5B; the conductive member 7B is electrically connected to the rewiring structure 5B and the power supply unit 8B respectively.
在一个实施例中，晶上***封装结构还包括：位于所述塑封晶圆1背离所述重布线结构5B一侧的散热单元9B。In one embodiment, the system-on-wafer packaging structure further includes: a heat dissipation unit 9B located on the side of the plastic wafer 1 away from the rewiring structure 5B.
参考图2，所述散热单元9B布满整个塑封晶圆1的一侧，所述散热单元9B能够在所述塑封晶圆1内芯片实现互连工作时及时降低塑封晶圆1的热量，保证晶上***芯片预制件之间的信号互连正常运行。Referring to Figure 2, the heat dissipation unit 9B covers one side of the entire plastic wafer 1. The heat dissipation unit 9B can reduce the heat of the plastic wafer 1 in time when the chips in the plastic wafer 1 are interconnected, ensuring that Signal interconnections between on-wafer system-on-chip prefabs operate normally.
所述重布线结构5B包括垂直于所述塑封晶圆1表面的方向上设置的若干层重布线层，在一个实施例中，所述若干层重布线层的层数小于或等于5层，例如为1层、2层、3层、4层或5层。The rewiring structure 5B includes several rewiring layers arranged in a direction perpendicular to the surface of the plastic wafer 1 . In one embodiment, the number of rewiring layers is less than or equal to 5 layers, for example Be 1st floor, 2nd floor, 3rd floor, 4th floor or 5th floor.
关于本实施例与前一实施例相同的内容，不再详述。The same contents between this embodiment and the previous embodiment will not be described in detail.
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。 Obviously, the above-mentioned embodiments are only examples for clear explanation and are not intended to limit the implementation. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. An exhaustive list of all implementations is not necessary or possible. The obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims (9)

  1. 一种晶上***封装结构，其特征在于，包括：A system packaging structure on a chip, which is characterized by including:
    塑封晶圆，所述塑封晶圆中具有容纳槽；Plastic wafer, the plastic wafer has a receiving groove;
    位于所述容纳槽中的桥接芯片；a bridge chip located in the receiving slot;
    位于所述塑封晶圆和桥接芯片一侧的重布线结构，所述重布线结构与所述桥接芯片的正面连接；A rewiring structure located on one side of the plastic wafer and the bridge chip, the rewiring structure being connected to the front side of the bridge chip;
    位于所述重布线结构背离所述塑封晶圆一侧的若干个第一芯片；至少部分相邻的所述第一芯片之间通过重布线结构和桥接芯片互连。Several first chips are located on the side of the rewiring structure away from the plastic wafer; at least part of the adjacent first chips are interconnected through the rewiring structure and the bridge chip.
  2. 根据权利要求1所述的晶上***封装结构，其特征在于，所述桥接芯片的正面设置有第一焊盘和第二焊盘，所述重布线结构包括间隔设置的第一布线路径和第二布线路径，第一布线路径分别与第一焊盘和相邻的所述第一芯片中的一个第一芯片电连接，第二布线路径分别与第二焊盘和相邻的所述第一芯片中的另一个第一芯片电连接。The on-wafer system packaging structure according to claim 1, characterized in that the front surface of the bridge chip is provided with a first bonding pad and a second bonding pad, and the rewiring structure includes a first wiring path and a third wiring path arranged at intervals. Two wiring paths, the first wiring path is electrically connected to the first bonding pad and one of the adjacent first chips respectively, and the second wiring path is respectively connected to the second bonding pad and the adjacent first chip. Another first chip of the chips is electrically connected.
  3. 根据权利要求1所述的晶上***封装结构，其特征在于，所述重布线结构包括垂直于所述塑封晶圆表面的方向上设置的若干层重布线层，所述若干层重布线层的层数小于或等于5层。The on-wafer system packaging structure according to claim 1, wherein the rewiring structure includes a plurality of rewiring layers arranged in a direction perpendicular to the surface of the plastic wafer, and the rewiring layers of the rewiring layers are The number of layers is less than or equal to 5 layers.
  4. 根据权利要求1所述的晶上***封装结构，其特征在于，还包括：位于所述重布线结构背离所述塑封晶圆一侧的塑封层，塑封层包覆所述第一芯片。The system-on-wafer packaging structure according to claim 1, further comprising: a plastic sealing layer located on the side of the rewiring structure facing away from the plastic sealing wafer, and the plastic sealing layer covers the first chip.
  5. 根据权利要求4所述的晶上***封装结构，其特征在于，还包括：位于所述塑封晶圆中的导电件；位于所述塑封晶圆背离所述重布线结构一侧的电源供给单元；所述导电件分别与所述重布线结构和所述电源供给单元 电连接。The on-wafer system packaging structure according to claim 4, further comprising: a conductive member located in the plastic wafer; a power supply unit located on the side of the plastic wafer away from the rewiring structure; The conductive member is connected to the rewiring structure and the power supply unit respectively. Electrical connection.
  6. 根据权利要求4或5所述的晶上***封装结构，其特征在于，还包括：位于所述塑封层背离所述重布线结构一侧的散热单元。The on-wafer system packaging structure according to claim 4 or 5, further comprising: a heat dissipation unit located on the side of the plastic sealing layer away from the rewiring structure.
  7. 根据权利要求4所述的晶上***封装结构，其特征在于，还包括：位于所述第一芯片侧部的塑封层中的导电件；位于所述塑封层背离所述重布线结构一侧电源供给单元；所述导电件分别与所述重布线结构和所述电源供给单元电连接。The on-wafer system packaging structure according to claim 4, further comprising: a conductive member located in the plastic sealing layer on the side of the first chip; a power supply located on the side of the plastic sealing layer away from the rewiring structure. Supply unit; the conductive member is electrically connected to the redistribution structure and the power supply unit respectively.
  8. 根据权利要求4或7所述的晶上***封装结构，其特征在于，还包括：位于所述塑封晶圆背离所述重布线结构一侧的散热单元。The system-on-wafer packaging structure according to claim 4 or 7, further comprising: a heat dissipation unit located on the side of the plastic wafer facing away from the rewiring structure.
  9. 根据权利要求1所述的晶上***封装结构，其特征在于，所述重布线结构包括：若干个光刻布线区域；每个光刻布线区域背离所述塑封晶圆的一侧均设置有若干个第一芯片；The on-wafer system packaging structure according to claim 1, wherein the rewiring structure includes: several photolithography wiring areas; each photolithography wiring area is provided with several the first chip;
    对于相邻的光刻布线区域上的相邻的第一芯片，相邻的所述第一芯片之间通过重布线结构和桥接芯片互连。 For adjacent first chips on adjacent photolithographic wiring areas, the adjacent first chips are interconnected through a rewiring structure and a bridge chip.
PCT/CN2023/088509 2022-06-30 2023-04-14 System-on-wafer packaging structure WO2024001429A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210770601.5 2022-06-30
CN202210770601.5A CN115101518A (en) 2022-06-30 2022-06-30 On-chip system packaging structure

Publications (1)

Publication Number Publication Date
WO2024001429A1 true WO2024001429A1 (en) 2024-01-04

Family

ID=83294116

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/088509 WO2024001429A1 (en) 2022-06-30 2023-04-14 System-on-wafer packaging structure

Country Status (2)

Country Link
CN (1) CN115101518A (en)
WO (1) WO2024001429A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115101518A (en) * 2022-06-30 2022-09-23 华进半导体封装先导技术研发中心有限公司 On-chip system packaging structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128914A (en) * 2019-12-25 2020-05-08 上海先方半导体有限公司 Low-warpage multi-chip packaging structure and manufacturing method thereof
CN111863641A (en) * 2020-07-28 2020-10-30 南通通富微电子有限公司 Chip packaging method
CN112635451A (en) * 2020-12-11 2021-04-09 上海先方半导体有限公司 Chip packaging structure and packaging method thereof
US20210159211A1 (en) * 2019-11-27 2021-05-27 International Business Machines Corporation Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices
CN114361153A (en) * 2022-01-04 2022-04-15 华进半导体封装先导技术研发中心有限公司 Semiconductor packaging structure and preparation method
CN115101518A (en) * 2022-06-30 2022-09-23 华进半导体封装先导技术研发中心有限公司 On-chip system packaging structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210159211A1 (en) * 2019-11-27 2021-05-27 International Business Machines Corporation Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices
CN111128914A (en) * 2019-12-25 2020-05-08 上海先方半导体有限公司 Low-warpage multi-chip packaging structure and manufacturing method thereof
CN111863641A (en) * 2020-07-28 2020-10-30 南通通富微电子有限公司 Chip packaging method
CN112635451A (en) * 2020-12-11 2021-04-09 上海先方半导体有限公司 Chip packaging structure and packaging method thereof
CN114361153A (en) * 2022-01-04 2022-04-15 华进半导体封装先导技术研发中心有限公司 Semiconductor packaging structure and preparation method
CN115101518A (en) * 2022-06-30 2022-09-23 华进半导体封装先导技术研发中心有限公司 On-chip system packaging structure

Also Published As

Publication number Publication date
CN115101518A (en) 2022-09-23

Similar Documents

Publication Publication Date Title
US20140131854A1 (en) Multi-chip module connection by way of bridging blocks
US9252091B2 (en) Semiconductor device having penetrating electrodes each penetrating through semiconductor chip
US7388295B2 (en) Multi-chip module
WO2024001429A1 (en) System-on-wafer packaging structure
KR100843213B1 (en) High I/O semiconductor chip with the memory chip connected to processor chip by through electrode arranged in scribe lane and method for fabricating the same
CN103620774A (en) Flip-chip, face-up and face-down wirebond combination package
US8456025B2 (en) Semiconductor chip having staggered arrangement of bonding pads
US10043789B2 (en) Semiconductor packages including an adhesive pattern
US10141289B2 (en) Semiconductor packages having package-on-package structures
CN102034780A (en) Integrated circuit chip and method of manufacturing the same and flip chip package having the integrated chip and method of manufacturing the same
US20130256908A1 (en) Inter-die connection within an integrated circuit formed of a stack of circuit dies
JP2010141080A (en) Semiconductor device
US6911844B2 (en) Electronic circuit apparatus and integrated circuit device
CN103681524A (en) Semiconductor package and fabrication method thereof
WO2024045329A9 (en) Semiconductor structure and method for manufacturing same
JP7514530B2 (en) Stacked semiconductor device
JP4658529B2 (en) Structure of integrated circuit module
CN217847954U (en) Packaging structure
JP2003273321A (en) Semiconductor module
TWI806343B (en) Semiconductor package and manufacturing method thereof
WO2023025064A1 (en) Chip, three-dimensional chip, and chip preparation method
US20230069294A1 (en) Multi-die communications couplings using a single bridge die
US20240038721A1 (en) Semiconductor devices and methods of manufacturing thereof
CN115662979A (en) Chip based on double-layer stacked packaging structure of Chiplet
KR20220106042A (en) Arrangement of power-grounds in package structures

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23829619

Country of ref document: EP

Kind code of ref document: A1