CN103413798A - Chip structure and chip packaging structure - Google Patents
Chip structure and chip packaging structure Download PDFInfo
- Publication number
- CN103413798A CN103413798A CN2013103358593A CN201310335859A CN103413798A CN 103413798 A CN103413798 A CN 103413798A CN 2013103358593 A CN2013103358593 A CN 2013103358593A CN 201310335859 A CN201310335859 A CN 201310335859A CN 103413798 A CN103413798 A CN 103413798A
- Authority
- CN
- China
- Prior art keywords
- chip
- conductive trough
- contact pad
- insulating barrier
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 230000004888 barrier function Effects 0.000 claims description 68
- 239000011347 resin Substances 0.000 claims description 25
- 229920005989 resin Polymers 0.000 claims description 25
- 230000005611 electricity Effects 0.000 claims description 20
- 230000002209 hydrophobic effect Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 230000010148 water-pollination Effects 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000004381 surface treatment Methods 0.000 claims description 4
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 7
- 238000013461 design Methods 0.000 abstract description 6
- 239000000853 adhesive Substances 0.000 abstract 3
- 230000001070 adhesive effect Effects 0.000 abstract 3
- 238000003466 welding Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 description 45
- 238000005520 cutting process Methods 0.000 description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 229910052710 silicon Inorganic materials 0.000 description 28
- 239000010703 silicon Substances 0.000 description 28
- 235000012431 wafers Nutrition 0.000 description 22
- 230000008569 process Effects 0.000 description 19
- 238000005530 etching Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 10
- 239000013078 crystal Substances 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000003292 glue Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000000608 laser ablation Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000005864 Sulphur Substances 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000006664 bond formation reaction Methods 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000016 photochemical curing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Provided are a chip structure and a chip packaging structure. The chip packaging structure comprises at least two chip structures and conductive adhesives located in conductive grooves, wherein the side walls of the chip structures are provided with the conductive grooves, the chip structures are stacked, the conductive grooves of the stacked chip structures correspond in position, and circuits in the stacked chip structures are electrically connected through the conductive adhesives. Due to the fact that the conductive grooves are formed in the side walls of insulating layers, the conductive adhesives formed in the conductive grooves later cannot be in direct contact with chips, and short-circuit phenomena cannot occur; due to the fact that the conductive grooves and contact welding plates are connected through metal interconnection layers on the surfaces of the insulating layers, the insulating layers cannot influence layout design of other metal interconnection structures in the chips, the practice that extra metal interconnection structures are designed due to positions of the contact welding plates is needless, the chip area occupied by the metal interconnection structures can be saved, and the component integration degree of the chips can be beneficially improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of chip structure, chip-packaging structure.
Background technology
Along with the semiconductor technology development, the characteristic size of semiconductor device has become very little at present, hope increases semiconductor device in two-dimentional chip structure quantity becomes more and more difficult, so three-dimension packaging, being about to a plurality of chip stack packages becomes a kind of method that can effectively improve chip integration.Current three-dimension packaging comprises chip-stacked (Die Stacking) based on Bonding, encapsulation stacking (Package Stacking) and three-dimensional stacked based on silicon through hole (Through Silicon Via, TSV).Wherein, utilize the three-dimensional stacked technology of silicon through hole to have following three advantages: (1) High Density Integration; (2) shorten significantly the length of electrical interconnection, thereby can solve well the problems such as signal delay that appear in two-dimentional system level chip (SOC) technology; (3) utilize silicon through hole technology, can integrate to realize the multi-functional of packaged chip to the chip with difference in functionality (as radio frequency, internal memory, logic, MEMS etc.).Therefore, the described three-dimensional stacked technology of silicon through hole interconnect structure of utilizing becomes a kind of comparatively popular chip encapsulation technology day by day.More three-dimensional stacked technology about the silicon through hole please refer to the american documentation literature that publication number is US2012/0083116A1.
But because the three-dimensional stacked Technology Need based on the silicon through hole forms some silicon through holes in chip, need to be by chip thinning while forming described silicon through hole, but after attenuate, the mechanical strength of chip is poor, is easy to deform even damaged; Simultaneously because the metal material of filling in described silicon through hole is copper, the thermal coefficient of expansion of the silicon base of copper and chip differs greatly, therefore can form stressed zone at the chip position near the silicon through hole, described stress can affect the electric property of semiconductor device, therefore in described stressed zone, semiconductor device can not be formed, the waste of chip area can be caused; Because the technological requirement that forms the silicon through hole is higher, process costs is larger simultaneously.
Summary of the invention
The problem that the present invention solves is to provide a kind of chip structure, chip-packaging structure, can realize that three-dimension packaging and technique are simple.
For addressing the above problem, the invention provides a kind of chip structure, comprising: chip, described chip have first surface and the second surface relative with first surface, and the first surface of described chip has contact pad; Be positioned at the insulating barrier of described chip sidewall, the sidewall of described insulating barrier has conductive trough, and the position of described conductive trough is corresponding with the position of contact pad, and the quantity of described conductive trough is corresponding with the quantity of contact pad; Be positioned at the metal interconnecting layer of described conductive trough sidewall surfaces, contact pad surface and surface of insulating layer, and described conductive trough, contact pad are connected by described metal interconnecting layer.
Optionally, described insulating barrier also covers the first surface of chip, and described insulating layer exposing goes out described contact pad.
Optionally, described insulating barrier is the hydrophilic resin layer.
Optionally, described insulating barrier is the hydrophobic resin layer, and the surface of described hydrophobic resin layer has hydrophily through surface treatment.
Optionally, the material of described metal interconnecting layer is copper, aluminium or aluminium copper.
The present invention also provides a kind of chip-packaging structure, comprising: at least two described chip structures, and the sidewall of described chip structure has conductive trough, and the conductive trough position of the stacking setting of described chip structure and stacking chip structure is corresponding; Be positioned at the conducting resinl of described conductive trough, utilize described conducting resinl that the circuit electricity in stacking chip structure is connected.
Optionally, also comprise: be positioned at the load film of described stacking chip structure, utilize described load film that different chip structures is bonding.
Compared with prior art, technical scheme of the present invention has the following advantages:
Due to described conductive trough, be positioned at the sidewall of insulating barrier, therefore follow-up conducting resinl in being formed on described conductive trough can directly not contact with chip, can the circuit for generating short circuit, and be connected by the metal interconnecting layer that is positioned at surface of insulating layer due between described conductive trough and contact pad, described insulating barrier can not affect the layout design of other metal interconnect structures in chip, do not need to design extra metal interconnect structure because of the position of considering contact pad, can save the occupied chip area of metal interconnect structure, be conducive to improve the device integrated level of chip.
When described at least two chip structure stacked package, owing in described conductive trough, being filled with conducting resinl, utilize described conducting resinl that the circuit electricity in different chip structures is connected, do not need to form the silicon through hole and can make different chip stack packages, alignment precision to chip-stacked equipment requires to reduce, and process costs is lower, and does not need additionally to carry out Bonding, and the number of plies of chip stack package can be larger, be conducive to improve the encapsulation and integration degree of chip-packaging structure.
The accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the chip cutting method of the embodiment of the present invention;
Fig. 2～Figure 13 is the process schematic diagram of the chip cutting method of the embodiment of the present invention;
Figure 14 and Figure 15 are the structural representation of the chip structure of the embodiment of the present invention;
Figure 16 is the schematic flow sheet of the chip packaging method of the embodiment of the present invention;
Figure 17～Figure 20 is the process schematic diagram of the chip packaging method of the embodiment of the present invention.
Embodiment
Because the three-dimensional stacked technical matters cost based on the silicon through hole is larger, can cause the waste of chip area, and need to be by chip thinning, make the mechanical strength variation of chip, therefore the invention provides a kind of chip structure, chip-packaging structure, utilize the sidewall of the formed chip structure of described cutting method to have conductive trough, when by a plurality of chip structures are stacking while arranging, in described conductive trough, fill full conducting resinl, utilize described conducting resinl to make the circuit electricity in different chip structures connect, form chip-packaging structure.Because the present invention need to not form the silicon through hole in chip, can save the technique that forms the silicon through hole, reduce costs; Simultaneously, due to described conductive trough, be formed on the sidewall of chip structure, in the process of encapsulation, only need in conductive trough, the circuit electricity in different chip structures be connected filled conductive glue, to the alignment precision requirement reduction of chip-stacked equipment, packaging technology be simple; And when utilizing the silicon through hole to carry out three-dimension packaging, existing chip usually need to again customize domain according to the position of silicon through hole, and around the silicon through hole, has stressed zone, can cause the waste of chip area, and the present invention is owing to need in chip, not forming the silicon through hole, can more effectively utilize the area of chip, be conducive to improve chip integration; And the metal interconnecting layer that between described conductive trough and contact pad, electricity is connected is positioned at surface of insulating layer, and described metal interconnecting layer does not need to occupy the area of chip, is conducive to improve the device integrated level of chip.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
At first the embodiment of the present invention provides a kind of chip cutting method, please refer to Fig. 1, and the schematic flow sheet for the chip cutting method of the present embodiment specifically comprises:
Step S101, provide wafer, and described wafer comprises some chips and the Cutting Road between chip, and described chip has first surface and the second surface relative with first surface, and the first surface of chip has contact pad;
Step S102, stick the first scribing film at crystal column surface corresponding to described chip second surface;
Step S103, carry out the first cutting along Cutting Road to the chip of wafer, between different chips, forms the groove that runs through whole wafer thickness;
Step S104, form insulating barrier with the first surface of chip in described groove;
Step S105, form and run through the through hole of described insulating barrier in insulating barrier corresponding to groove, until expose the first scribing film, the position of described through hole is corresponding with the position of contact pad, and the quantity of described through hole is corresponding with the quantity of contact pad;
Step S106, form metal interconnecting layer on described contact pad surface, surface of insulating layer and through-hole side wall surface, utilizes described metal interconnecting layer to make contact pad be connected with through-hole side wall;
Step S107, carry out the second cutting along the central point of described through hole to the insulating barrier in described groove, and described wafer is cut into discrete chip structure, and described through hole forms conductive trough at described chip structure sidewall after by the second cutting.
Concrete, please refer to Fig. 2 and Fig. 3, Fig. 2 is the plan structure schematic diagram of described wafer, Fig. 3 is the cut-away section structural representation of described wafer, wafer 10 is provided, described wafer 10 comprises some chip 100 and Cutting Roads between chip 100 120 that matrix is arranged that are, and described chip 100 has first surface 101 and second surface on the other side 102, and the first surface 101 of chip 100 has contact pad 103.
Described wafer 10 comprises some chip 100 and Cutting Roads between chip 100 120 that matrix is arranged that are, and follow-uply along described Cutting Road 100, wafer is cut into to several discrete chips.
In described chip 100, be formed with semiconductor device (not shown) and metal interconnect structure (not shown); described semiconductor device and metal interconnect structure form integrated circuit; described chip 100 surfaces also have passivation insulation (not shown); utilize described passivation insulation protection chip and chip and external electrical are isolated; described passivation insulation also has the opening that exposes described contact pad 103, and the integrated circuit in chip is connected with external circuit with other chips by described contact pad 103.In the present embodiment, be connected for the ease of the conductive trough electricity with follow-up formation, described contact pad 103 is arranged in a linear at the marginal position of chip, and described straight line parallels with the sideline of rectangular dies.Described contact pad 103 can only be formed on the marginal position on a limit of chip, also can be formed on the marginal position on two limits of chip, three limits or four limits.In the present embodiment, in order to illustrate conveniently, 103 marginal positions that are formed on a limit of rectangular dies of described contact pad.
In other embodiments, described contact pad 103 also can need to be arranged on the optional position of chip according to layout design, because making contact pad, the later use metal interconnecting layer is connected with conductive trough electricity, described metal interconnecting layer is formed on the passivation insulation surface of surface of insulating layer or chip, can not affect the layout design of metal interconnect structure in chip, do not need to design extra metal interconnect structure because of the position of considering contact pad, can save the occupied chip area of metal interconnect structure, be conducive to improve the device integrated level of chip.
And because the embodiment of the present invention need to not form the silicon through hole in described chip, therefore do not need described wafer is carried out to attenuate, the mechanical strength of described wafer is larger, is not easy to occur wafer or chip fracture or damage.And owing to need in described chip, not forming the silicon through hole, therefore can save the processing step that forms the silicon through hole, significantly reduce process costs.And because the area of silicon through hole is usually very large and can form stressed zone near the chip position of silicon through hole, the stress of described stressed zone can affect the electric property of semiconductor device, therefore in the position of silicon through hole and stressed zone, all can not form semiconductor device, can cause the waste of chip area, and the present invention is owing to not needing to form the silicon through hole, can more effectively utilize the area of chip, be conducive to improve the device integrated level of chip.
Please refer to Fig. 4, stick the first scribing film 131 at the crystal column surface of described chip 100 second surface 102 correspondences.
In order to prevent that chip is scattered when scribing is cut, before wafer is cut, crystal column surface in chip 100 second surface 102 correspondences sticks described the first scribing film 131, described the first scribing film 131 has viscosity and is difficult for being isolated, it is follow-up when wafer is cut into discrete chip by scribing, described chip still sticks on the first scribing film 131 surfaces, can not be scattered by generating chip, is convenient to the encapsulation of the follow-up chip structure carried out.Described the first scribing film 131 is blue film or UV-light photocuring scribing film (UV film) etc.
Please refer to Fig. 5, carry out the first cutting along the chip 100 of 120 pairs of wafers of Cutting Road, between different chips 100, form groove 105.
The technique of described the first cutting is laser cutting or blade cuts.In the present embodiment, utilize blade to cut along 120 pairs of wafers 10 of Cutting Road, make between different chip 100 and cut open fully, crystal column surface due to chip 100 second surface 102 correspondences posts the first scribing film 131 simultaneously, described the first scribing film 131 is cut opening not, therefore described chip 100 still sticks on the first scribing film 131 surfaces, between different chips 100, forms the groove 105 that runs through whole chip thickness.The width of described groove 105 is less than or equal to the width of Cutting Road 120.
Please refer to Fig. 6, with the first surface 101 of chip 100, form insulating barriers 106 in described groove 105.
Described insulating barrier 106 is as the supporting body of the conductive trough of follow-up formation, and due to described conductive trough domestic demand filled conductive glue, described insulating barrier 106 has insulating properties, can described conducting resinl and chip is isolated, make both not directly contacts, avoid the circuit for generating short circuit.In the present embodiment, described insulating barrier 106 is the hydrophilic resin layer, for example contains-CONHCH
2OH ,-CONH
2,-COOH ,-COOROH ,-NH
2,-OH ,-SO
3The resin of the hydrophilic radicals such as H.In other embodiments, described insulating barrier 106 also can be the hydrophobic resin layer, by the surface to the hydrophobic resin layer, carry out surface treatment, described surface-treated technique comprises plasma, glow discharge, ultraviolet oxidation, concentrated sulfuric acid immersion etc., makes the surface of hydrophobic resin layer have hydrophily.When the surface of described insulating barrier 106 was hydrophily, the follow-up chemical plating process that could utilize formed metal seed layer on described insulating barrier 106 surfaces, utilizes described metal seed layer to form the metal interconnecting layer that connects contact pad and conductive trough.Simultaneously, the formation technique that forms described resin bed is simple, and the mechanical strength of resin is higher, can protect chip to be not easy fracture.
In the present embodiment, described insulating barrier 106 is filled full described groove 105 and is formed on the first surface 101 of chip 100, and concrete formation technique comprises: with the first surface 101 of chip 100, form the hydrophilic resin layers and be cured in described groove 105; Hydrophilic resin layer after described solidify is carried out to polishing polishes or return etching, at the hydrophilic resin layer of described chip 100 first surface 101 reserve part thickness, in described groove 105 and the hydrophilic resin layer of the first surface 101 of chip 100 form described insulating barrier 106.Because described insulating barrier 106 is filled the first surface 101 of expiring described groove 105 and being formed on chip 100, make first surface 101 and the sidewall surfaces of the described chip 100 of rear described insulating barrier 106 covering of the second cutting, can more effectively improve the mechanical strength of chip structure.
In the present embodiment, after forming described insulating barrier 106, on described insulating barrier 106 surfaces, form patterned photoresist layer, the position of the insulating barrier 106 that described patterned photoresist layer exposes is corresponding to the position of contact pad 103, the described patterned photoresist layer of take is mask, described insulating barrier 106 is carried out to dry etching, until expose described contact pad 103, on described contact pad 103 surfaces, form metal interconnecting layer so that follow-up.Described dry etch process can utilize electron cyclotron acceleration vibration (ECR) reactor, reactive ion etching (RIE) reactor, magnetic intensified response ion etching (MERIE) reactor or inductively coupled plasma (ICP) reactor etc. to carry out etching, and the etching gas of described dry etching is the etching gas that contains the halogens such as fluorine, chlorine, bromine or oxygen element or element sulphur, oxygen for example, C
4F
8, C
4F
8Deng, thereby utilize described etching gas and resin bed to react, carry out etching.In other embodiments, also can utilize laser ablation technique that the insulating barrier on described contact pad surface is removed, thereby expose described contact pad.
In other embodiments, also can be after forming through hole the more described insulating barrier of etching to expose described contact pad.
In other embodiments, described insulating barrier is filled the first surface of expiring described groove but exposing chip, and concrete formation technique comprises: with the first surface of chip, form the hydrophilic resin layer and be cured in described groove; Hydrophilic resin layer after described solidify is carried out to polishing polishes or return etching, until expose described chip first surface and expose described contact pad surface, hydrophilic resin layer in described groove is described insulating barrier, and after the second cutting, described insulating barrier only covers the sidewall surfaces of described chip.
Please refer to Fig. 7, stick the second scribing film 132 at the crystal column surface of described chip 100 first surface 101 correspondences, and the first scribing film 131(that tears the crystal column surface of chip 100 second surface 102 correspondences off please refer to Fig. 6);
Please refer to Fig. 8, crystal column surface in described chip 100 second surface 102 correspondences sticks load film 115, insulating barrier 106 and load film 115 to described chip 100 second surface 102 correspondences carry out etching formation the first through hole 108, the position of described the first through hole 108, quantity are corresponding with position, the quantity of contact pad 103, and the degree of depth of described the first through hole 108 is less than the gross thickness of the insulating barrier 106 that groove is corresponding;
Please refer to Fig. 9, the 3rd scribing film 133 on described load film 115 surface labels, tear described the second scribing film 132 off, insulating barrier 106 at 101 pairs of the first through hole 108 correspondence positions of described chip 100 first surface carries out the second etching, described the first through hole 108 remaining insulating barriers in bottom are worn for 106 quarters, formed described through hole 107.
The technique that forms described through hole 107 is laser ablation technique or dry etch process, in the present embodiment, the technique that forms described through hole 107 is dry etch process, by twice etching, forms the through hole 107 that runs through insulating barrier, is conducive to form the through hole that sidewall is comparatively vertical.In other embodiments, can also utilize etching of laser ablation technique or dry etch process directly insulating barrier that groove is corresponding carve to wear and form the through hole that runs through described insulating barrier.
The plan view shape of described through hole 107 is circle or rectangle, the follow-up groove that is evenly cut into two cylindricalitys by the second cutting technique of described through hole, and described two grooves are as the conductive trough of chip structure.In the present embodiment, the plan view shape of described through hole 107 is rectangle.
The position of described through hole 107 is corresponding with the position of contact pad 103, and the quantity of described through hole 107 is corresponding with the quantity of contact pad 103.In the present embodiment, through hole 107 is follow-up is cut into two conductive troughs, due to for a chip structure, the corresponding contact pad of conductive trough, so corresponding two contact pads 103 of the through hole between two chips 107, described two contact pads 103 are positioned at two two adjacent chip surfaces.Described through hole 107 is positioned at the central point of two corresponding contact pad 103 lines.
In the present embodiment, in order to illustrate conveniently, 103 of described contact pads are formed on the marginal position on a limit of chip of rectangle, and therefore described through hole 107 also only is formed in the insulating barrier that the groove of chip one side is corresponding.In other embodiments, described through hole also can be formed in the insulating barrier that the groove on two limits of chip, three limits or four limits is corresponding, and the position of described through hole is corresponding with the position of contact pad, and the quantity of described through hole is corresponding with the quantity of contact pad.
In the present embodiment, the material of described the second scribing film 132, the 3rd scribing film 133 is identical with the material of the first scribing film 133, all for the chip by wafer, fixes, and avoids because the wafer fracture causes chip to be scattered.In other embodiments, the material of described the second scribing film, the 3rd scribing film can be not identical with the material of the first scribing film yet.Described load film 115 insulation and have viscosity, described load film 115 is attached to the second surface 102 of described chip, follow-up when chip structure is encapsulated, and utilizes described load film 115 by the bonding formation stacked structure of different chips.In the present embodiment, described the 3rd scribing film 133 and load film 115 are all hydrophobic film, so can not form metal seed layers at described the 3rd scribing film 133 or load film 115 surfaces during subsequent chemistry plating inculating crystal layer.
In other embodiments, also can first at described chip first surface, carry out etching to insulating barrier corresponding to groove and form the first through hole, the position of described the first through hole, quantity are corresponding with position, the quantity of contact pad, and the degree of depth of described the first through hole is less than the gross thickness of the insulating barrier that groove is corresponding, then at crystal column surface corresponding to described chip second surface, form the load film, insulating barrier at described chip second surface and the first through hole correspondence position carries out etching, the remaining insulating barrier of described the first via bottoms is carved and worn, form described through hole.
In other embodiments, also can not form the load film, follow-up when chip structure is encapsulated, utilize the conducting resinl in described conductive trough to be fixed together different chip structures is stacking.
Please refer to Figure 10 and Figure 11, Figure 10 is the cross-sectional view of chip cutting process, Figure 11 is the perspective view of described chip cutting process, on described contact pad 103 surfaces, through hole 107 sidewalls and insulating barrier 106 surfaces form metal interconnecting layers 109, utilize described metal interconnecting layer 109 to make contact pad 103 be connected with through hole 107 sidewalls, thereby make contact pad 103 be connected with the follow-up conducting resinl electricity formed in conductive trough.
In the present embodiment, the concrete technology that forms described metal interconnecting layer 109 comprises: utilize chemical plating process or physical gas-phase deposition on described contact pad 103 surfaces, through hole 107 sidewalls and insulating barrier 106 surfaces form metal seed layer (not shown), the material of described metal seed layer is copper, aluminium, silver waits wherein a kind of, when utilizing chemical plating process to form metal seed layer, because chemical plating process can only form metal seed layer at hydrophilic material surface, therefore, described metal seed layer can only be formed on described contact pad 103 surfaces, hydrophilic through hole 107 sidewalls and insulating barrier 106 surfaces, on described metal seed layer surface, form patterned photoresist layer (not shown), described patterned photoresist layer defines the position of the metal interconnecting layer between contact pad and through hole, utilize electroplating technology, chemical plating process to form metal interconnecting layer 109 on the metal seed layer surface that described patterned photoresist layer exposes, the material of described metal interconnecting layer 109 is copper, aluminium or aluminium copper, utilize cineration technics to remove described patterned photoresist layer, expose the metal seed layer of correspondence position, utilize dry etch process or wet-etching technology to remove the described metal seed layer exposed, due to the thickness of metal seed layer, be far smaller than the thickness of metal interconnecting layer, therefore removing the described metal seed layer exposed can affect the electrology characteristic of metal interconnecting layer hardly.
In the present embodiment, due to insulating barrier 106, cover the first surface 101 of chip 100, therefore described metal interconnecting layer 109 is formed on described contact pad 103 surfaces, through hole 107 sidewalls and insulating barrier 106 top surfaces, utilizes described metal interconnecting layer 109 to make contact pad 103 be connected with through hole 107 sidewall electricity.
In other embodiments, because insulating barrier only is formed in groove, therefore described metal interconnecting layer is formed on first surface, insulating barrier top surface and the through-hole side wall of described contact pad surface, chip, utilizes described metal interconnecting layer to make contact pad be connected with through-hole side wall electricity.
Please refer to Figure 12 and Figure 13, Figure 12 is the cross-sectional view of chip cutting process, Figure 13 is the perspective view of described chip cutting process, along described through hole 107(, please refer to Figure 10) central point to the insulating barrier 106 in described groove carry out second the cutting, described wafer 10 is cut into discrete chip structure 20, and described through hole 107(please refer to Figure 10) after the second cutting, formed conductive trough 110 at described chip structure 20 sidewalls.
The technique of described the second cutting is laser cutting or blade cuts, described the second cutting technique cuts the insulating barrier 106 in described groove along the linear position that the central point of through hole 107 is linked to be, make described through hole 107 evenly be cut into the conductive trough of two columns, namely the sidewall of the insulating barrier 106 after the second cutting forms conductive trough 110.After the second cutting technique, described wafer 10 is cut into several chip structures, and each chip structure correspondence has a chip 100, and the sidewall of described chip structure is formed with conductive trough 110.
The embodiment of the present invention also provides a kind of chip structure, please refer to Figure 14 and Figure 15, Figure 14 is the cross-sectional view of described chip structure 20, Figure 15 is the perspective view of described chip structure 20, comprise: chip 100, described chip 100 has first surface 101 and second surface 102, and the first surface 101 of described chip 100 has contact pad 103; Be positioned at the insulating barrier 106 of described chip 100 sidewalls and first surface 101, the sidewall of described insulating barrier 106 has conductive trough 110; Be positioned at the metal interconnecting layer 109 on described conductive trough 110 sidewall surfaces, contact pad 103 surfaces and 106 surfaces, insulating barrier top, and described conductive trough 110, contact pad 103 utilize described metal interconnecting layer 109 electricity to connect.
In other embodiments, described insulating barrier only is formed on the sidewall of described chip, and described metal interconnecting layer is formed on first surface, insulating barrier top surface and the conductive trough sidewall surfaces of contact pad surface, chip, utilize described metal interconnecting layer that conductive trough, contact pad electricity are connected.
In the present embodiment, described insulating barrier 106 is the hydrophilic resin layer, and in other embodiments, described insulating barrier also can be the hydrophobic resin layer, and the surface of described hydrophobic resin layer is after surface treatment, and the surface of hydrophobic resin layer has hydrophily.Due to described conductive trough 110, be positioned at the sidewall of insulating barrier 106, though follow-up at the interior filled conductive glue of described conductive trough 110, described conducting resinl can be not directly yet and chip come in contact, avoid being short-circuited.
In the present embodiment, the second surface 102 of described chip 100 is formed with load film 115, described load film 115 insulate and has viscosity, it is follow-up when described chip structure is encapsulated, utilize described load film 115 that different chip structures is bonding, be conducive to improve the mechanical strength of described chip-packaging structure, be conducive to improve rate of finished products.In other embodiments, also can be not at the second surface of described chip, do not form the load film, the conducting resinl in the described conductive trough of later use is stacking and be fixed together by different chip structures.
The embodiment of the present invention also provides a kind of chip packaging method, please refer to Figure 16, and the schematic flow sheet for the chip packaging method of the present embodiment specifically comprises:
Step S201, provide at least two chip structures, and the sidewall of described chip structure has conductive trough, and the conductive trough position of the stacking setting of described chip structure and stacking chip structure is corresponding;
Step S202, fill full conducting resinl in described conductive trough, utilize described conducting resinl that the circuit electricity in stacking chip structure is connected.
Concrete, please refer to Figure 17 and Figure 18, Figure 17 is the cross-sectional view of described chip package process, Figure 18 is the perspective view of described chip package process, at least two chip structures 20 as shown in Figure 14 and Figure 15 are provided, the sidewall of described chip structure 20 has conductive trough 110, and conductive trough 110 positions of the stacking setting of described chip structure 20 and different chip structure 20 are corresponding.
In the present embodiment, because conductive trough 110 positions of different chip structures 20 are corresponding, and the conductive trough 11 of each chip structure 20 is connected with the contact pad 103 on corresponding chip 100 surfaces, therefore at the interior filled conductive glue of conductive trough 110, different chips can be carried out to the electricity connection.
In the present embodiment, all have load film 115 between different chip structures 20, described load film 115 utilizes described load film 115 that different chip structure 20 is bonding, is conducive to improve the mechanical strength of described chip-packaging structure, is conducive to improve rate of finished products.In other embodiments, do not have the load film between described different chip structures, the conducting resinl in the described conductive trough of later use is stacking and be fixed together by different chip structures.
In the present embodiment, three stacking settings of chip structure 20, in other embodiments, can also be by two or more than the stacking setting of chip structure 20 of three and encapsulate.While due to the chip structure of the embodiment of the present invention, encapsulating, utilize the conducting resinl in conductive trough that different chip electricity is connected, therefore the stacking number of plies of chip structure is unrestricted, than the chip stack structure based on Bonding, chip-packaging structure of the present invention can improve the encapsulation and integration degree greatly.
Please refer to Figure 19 and Figure 20, Figure 19 is the cross-sectional view of described chip-packaging structure, Figure 20 is the perspective view of described chip-packaging structure, at the interior filled conductive glue 111 of described conductive trough 110, utilizes described conducting resinl 111 that the circuit electricity in stacking chip structure 20 is connected.
Described conducting resinl 111 includes organic polymer matrix and conducting particles, described conducting particles generally includes the electric conducting materials such as carbon, metal, metal oxide, by conducting particles being mixed in described organic polymer matrix, thereby make described conducting resinl have the electric conductivity close with metal.In the present embodiment, described conducting resinl 111 is filled full described conductive trough 110 just fully, and in other embodiments, the surface of described conducting resinl 111 is higher or lower than the sidewall surfaces of described insulating barrier 160, and conducting resinl 111 electric isolation in different conductive trough.
In the present embodiment, after the full conducting resinl 111 of the interior filling of described conductive trough 110, described conducting resinl 111 is solidified and makes the chip structure of described multiple-level stack be packaged into a chip-packaging structure, and described chip-packaging structure utilizes the conducting resinl 111 in conductive trough 110 that the integrated circuit electricity in different chips is connected.
After forming described chip-packaging structure, can also carry out plastic packaging to described chip-packaging structure, make the described conducting resinl exposed 111 and extraneous electric isolation, avoid described chip-packaging structure to be short-circuited.
The embodiment of the present invention also provides a kind of chip-packaging structure, please refer to Figure 19 and Figure 20, Figure 19 is the cross-sectional view of described chip-packaging structure, Figure 20 is the perspective view of described chip-packaging structure, comprise: at least two chip structures 20 as shown in Figure 14 and Figure 15, the sidewall of described chip structure 20 has conductive trough 110, and conductive trough 110 positions of the stacking setting of described chip structure 20 and stacking chip structure 20 are corresponding; Be positioned at the conducting resinl 111 of described conductive trough 110, utilize described conducting resinl 111 that the circuit electricity in stacking chip structure 20 is connected.
In the present embodiment, all have load film 115 between different chip structures 20, utilize described load film 115 that different chip structure 20 is bonding, be conducive to improve the mechanical strength of described chip-packaging structure, be conducive to improve rate of finished products.In other embodiments, also can not have the load film between described different chip structures, the conducting resinl in the described conductive trough of later use is stacking and be fixed together by different chip structures.
Because the chip-packaging structure of the embodiment of the present invention only need to can make the circuit electricity in different chip structures connect by filled conductive glue in conductive trough, the alignment precision of chip-stacked equipment requires to reduce, packaging technology is simple, and the stacking number of plies of the chip structure of the embodiment of the present invention is unrestricted, than the chip stack structure based on Bonding, chip-packaging structure of the present invention can improve the encapsulation and integration degree greatly.
Although the present invention discloses as above, the present invention not is defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (7)
1. a chip structure, is characterized in that, comprising:
Chip, described chip have first surface and the second surface relative with first surface, and the first surface of described chip has contact pad;
Be positioned at the insulating barrier of described chip sidewall, the sidewall of described insulating barrier has conductive trough, and the position of described conductive trough is corresponding with the position of contact pad, and the quantity of described conductive trough is corresponding with the quantity of contact pad;
Be positioned at the metal interconnecting layer of described conductive trough sidewall surfaces, contact pad surface and surface of insulating layer, and described conductive trough, contact pad are connected by described metal interconnecting layer.
2. chip structure as claimed in claim 1, is characterized in that, described insulating barrier also covers the first surface of chip, and described insulating layer exposing goes out described contact pad.
3. chip structure as claimed in claim 1 or 2, is characterized in that, described insulating barrier is the hydrophilic resin layer.
4. chip structure as claimed in claim 1 or 2, is characterized in that, described insulating barrier is the hydrophobic resin layer, and the surface of described hydrophobic resin layer has hydrophily through surface treatment.
5. chip structure as claimed in claim 1, is characterized in that, the material of described metal interconnecting layer is copper, aluminium or aluminium copper.
6. a chip-packaging structure, is characterized in that, comprising:
At least two chip structures as claimed in claim 1, the sidewall of described chip structure has conductive trough, and the conductive trough position of the stacking setting of described chip structure and stacking chip structure is corresponding;
Be positioned at the conducting resinl of described conductive trough, utilize described conducting resinl that the circuit electricity in stacking chip structure is connected.
7. chip-packaging structure as claimed in claim 6, is characterized in that, also comprises: the load film between described stacking chip structure, utilize described load film that different chip structures is bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310335859.3A CN103413798B (en) | 2013-08-02 | 2013-08-02 | Chip structure, chip-packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310335859.3A CN103413798B (en) | 2013-08-02 | 2013-08-02 | Chip structure, chip-packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103413798A true CN103413798A (en) | 2013-11-27 |
| CN103413798B CN103413798B (en) | 2016-03-09 |
Family
ID=49606796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310335859.3A Active CN103413798B (en) | 2013-08-02 | 2013-08-02 | Chip structure, chip-packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103413798B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653690A (en) * | 2017-03-03 | 2017-05-10 | 成都中宇微芯科技有限公司 | Multi-dimension chip cutting technology |
| CN108389912A (en) * | 2018-01-12 | 2018-08-10 | 武汉高芯科技有限公司 | A kind of non-refrigerated infrared detector chip and its encapsulating structure and preparation method |
| CN111863641A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip packaging method |
| CN111863719A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863717A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863793A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging device and chip interconnection method |
| CN111863640A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip packaging method |
| CN111863795A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging body and chip packaging body |
| CN113540064A (en) * | 2021-07-16 | 2021-10-22 | 芯知微(上海)电子科技有限公司 | Wafer level packaging structure and packaging method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135763A (en) * | 2007-12-20 | 2008-06-12 | Seiko Epson Corp | Semiconductor module, and method for manufacturing electronic equipment and semiconductor module |
| CN101330025A (en) * | 2007-06-20 | 2008-12-24 | 海力士半导体有限公司 | Method for fabricating semiconductor encapsulation and semiconductor chip for encapsulation |
| CN101335262A (en) * | 2007-06-26 | 2008-12-31 | 海力士半导体有限公司 | Stack package and method for manufacturing the same |
-
2013
- 2013-08-02 CN CN201310335859.3A patent/CN103413798B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330025A (en) * | 2007-06-20 | 2008-12-24 | 海力士半导体有限公司 | Method for fabricating semiconductor encapsulation and semiconductor chip for encapsulation |
| CN101335262A (en) * | 2007-06-26 | 2008-12-31 | 海力士半导体有限公司 | Stack package and method for manufacturing the same |
| JP2008135763A (en) * | 2007-12-20 | 2008-06-12 | Seiko Epson Corp | Semiconductor module, and method for manufacturing electronic equipment and semiconductor module |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653690A (en) * | 2017-03-03 | 2017-05-10 | 成都中宇微芯科技有限公司 | Multi-dimension chip cutting technology |
| CN106653690B (en) * | 2017-03-03 | 2019-05-28 | 成都中宇微芯科技有限公司 | A kind of more scale chips cutting techniques |
| CN108389912A (en) * | 2018-01-12 | 2018-08-10 | 武汉高芯科技有限公司 | A kind of non-refrigerated infrared detector chip and its encapsulating structure and preparation method |
| CN108389912B (en) * | 2018-01-12 | 2020-02-28 | 武汉高芯科技有限公司 | Uncooled infrared detector chip and packaging structure and preparation method thereof |
| CN111863717A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863719A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863641A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip packaging method |
| CN111863793A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging device and chip interconnection method |
| CN111863640A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip packaging method |
| CN111863795A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging body and chip packaging body |
| CN111863640B (en) * | 2020-07-28 | 2021-11-23 | 南通通富微电子有限公司 | Chip packaging method |
| CN111863793B (en) * | 2020-07-28 | 2022-07-12 | 南通通富微电子有限公司 | Semiconductor packaging device and chip interconnection method |
| CN111863717B (en) * | 2020-07-28 | 2022-07-15 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863719B (en) * | 2020-07-28 | 2022-07-19 | 南通通富微电子有限公司 | Chip interconnection method |
| CN113540064A (en) * | 2021-07-16 | 2021-10-22 | 芯知微(上海)电子科技有限公司 | Wafer level packaging structure and packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103413798B (en) | 2016-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103413785B (en) | chip cutting method and chip packaging method | |
| CN103413798B (en) | Chip structure, chip-packaging structure | |
| CN103681613B (en) | There is the semiconductor device of discrete area | |
| CN103996630B (en) | Packaged semiconductor devices and packaging devices and methods | |
| CN101800207B (en) | Packaging structure of semiconductor element and manufacture method thereof | |
| KR102372349B1 (en) | Semiconductor chip, method for fabricating the same, and semiconductor package comprising the same | |
| TW201714259A (en) | A semiconductor package structure and method for forming the same | |
| TWI626717B (en) | A semiconductor package structure | |
| CN104637967A (en) | Packaging method and packaging structure | |
| CN104882417A (en) | Integrated Passive Flip Chip Package | |
| CN105374731A (en) | Packaging method | |
| CN103779351B (en) | Three-dimension packaging structure and its manufacture method | |
| CN105225974A (en) | Method for packing | |
| CN103489802A (en) | Chip packaging structure and formation method thereof | |
| CN103219303B (en) | The encapsulating structure of a kind of TSV back side small opening and method | |
| TWI506753B (en) | Coreless package structure and method for manufacturing same | |
| CN103972111A (en) | Formation method of lead frame structure | |
| TW202324670A (en) | Structure and formation method of chip package with reinforcing structures | |
| KR20130110872A (en) | Stacked semiconductor package and method of manufacturing the same | |
| CN101814461B (en) | Packaging substrate structure and chip packaging structure, as well as manufacturing method thereof | |
| US10818616B2 (en) | Semiconductor package structure and method for forming the same | |
| CN103311131A (en) | Method for preventing lateral undercutting of micro-convex points in manufacturing process of micro-convex points | |
| CN108461464A (en) | Semiconductor package and its manufacturing method | |
| CN105633027B (en) | Fan-out wafer grade chip-packaging structure and its manufacturing method | |
| CN103745933A (en) | Packaging structure forming method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |