CN111856247B - Device for simulating memory current test - Google Patents
Device for simulating memory current test Download PDFInfo
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- CN111856247B CN111856247B CN202010669479.3A CN202010669479A CN111856247B CN 111856247 B CN111856247 B CN 111856247B CN 202010669479 A CN202010669479 A CN 202010669479A CN 111856247 B CN111856247 B CN 111856247B
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- 238000012360 testing method Methods 0.000 title claims abstract description 26
- 239000002184 metal Substances 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000011810 insulating material Substances 0.000 claims description 8
- 238000013461 design Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000012795 verification Methods 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
- G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
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- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a device for simulating memory current test, which comprises the following components: the plurality of analog memory pull-up support plates are arranged on the memory strip slot side by side, and each analog memory pull-up support plate is provided with a plurality of groups of connecting strips; the connecting plate is provided with a plurality of groups of connecting holes side by side, and each group of connecting holes is matched with each group of connecting strips in shape so as to detachably fix the connecting plate on the analog memory pull carrier plate; and the switch blade is arranged on the connecting plate, a plurality of protruding parts are arranged on the switch blade, and the protruding parts are arranged corresponding to the connecting holes so as to enable the plurality of analog memory pull carrier plates to form short circuits by inserting the protruding parts into the connecting holes. The scheme provided by the invention simulates the severest load condition of the work of the mainboard memory bank by adopting the simulated memory pull-up plate, verifies the design index of the memory voltage specification, has low cost and simple and convenient operation, reduces the labor hour, and improves the working efficiency and the test accuracy.
Description
Technical Field
The present invention relates to the field of testing, and more particularly, to a device for simulating a memory current test.
Background
With the depth of artificial intelligence, the requirements on power and performance of the servers are higher and higher, and the requirements on power supply of the memory by more and more servers are higher and higher. The server motherboard has transitioned from the previous 2-way to 4-way and 8-way. The requirement on the memory is higher and higher, and the full-load working current of the analog memory is higher and basically reaches more than 100A.
The server motherboard and other boards need a power supply test for the memory VR (Voltage specification) during the development phase. In the testing process, the electronic load is required to carry a large current to the load end of the memory VR so as to verify whether various design indexes of the memory VR meet the industry design standard or not, and whether parameters such as output voltage and current of the memory VR meet the specified SPEC requirements or not is judged. Meanwhile, various protection verification tests and the like for the memory VR are required. Generally, the largest-sized memory bank is fully allocated on the server motherboard, and when a pressure test is performed, the supply current of the memory VR cannot reach the maximum load current and the most severe working condition through the pressure test.
In the prior art, when the loading current is very large, a plurality of load lines need to be welded at the VR output end, the load lines are connected to an electronic load, the electronic load and other equipment are used for carrying out related verification, and the verification work is more and more complicated. Meanwhile, because the main board end memory VR is connected to the electronic load through the welding load line, when the load cable is long and short-circuit protection test is carried out, the risk of board burning easily occurs because the loop is long.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a device for simulating a memory current test, which simulates the severest load condition of the operation of a main board memory bank by using a simulated memory pull-up board, verifies the design index of the memory voltage specification, has low cost and simple operation, reduces the labor hour, and improves the working efficiency and the test accuracy.
In view of the foregoing, an aspect of the embodiments of the present invention provides a device for simulating a memory current test, including the following components: the analog memory pull-in support plates are arranged on the memory strip slots side by side, and each analog memory pull-in support plate is provided with a plurality of groups of connecting strips; the connecting plate is provided with a plurality of groups of connecting holes side by side, and each group of connecting holes is matched with each group of connecting strip shapes so as to detachably fix the connecting plate on the analog memory pull carrier plate; and the switch blade is arranged on the connecting plate, a plurality of protruding parts are arranged on the switch blade, and the protruding parts and the connecting holes are correspondingly arranged so as to enable the plurality of analog memory pull-up carrier plates to form short circuits by inserting the protruding parts into the connecting holes.
In some embodiments, further comprising: the connecting plate is provided with a detachable pulling load line between every two groups of connecting holes.
In some embodiments, each group of the connection bars of the analog memory pull-in board includes a power connection bar and a ground connection bar, and distances between the power connection bars and the ground connection bars of each group are the same.
In some embodiments, the power types corresponding to the power connection bars in different groups of connection bars on the same analog memory pull-up carrier are different.
In some embodiments, the power connection bars of the same power type in the plurality of analog memory pull-up carrier boards are arranged at the same position.
In some embodiments, the connecting plate includes a first metal plate and a second metal plate, the first metal plate and the second metal plate are arranged side by side, and the first metal plate and the second metal plate are connected with an insulating material therebetween.
In some embodiments, each set of connection holes on the connection plate includes a first sub-connection hole and a second sub-connection hole, the first sub-connection hole and the second sub-connection hole are respectively disposed on the first metal plate and the second metal plate, and the first sub-connection hole and the second sub-connection hole are symmetrical with respect to the insulating material.
In some embodiments, the distance between the first sub-connection hole and the second sub-connection hole is the same as the distance between two sub-connection bars in the corresponding group of connection bars.
In some embodiments, a plurality of sub-connection portions are disposed on the blade corresponding to the plurality of sets of connection holes, and the plurality of sub-connection portions are disposed in parallel.
In some embodiments, each of the sub-connecting portions is provided with a first protruding portion and a second protruding portion, the first protruding portion is disposed corresponding to the first sub-connecting hole, and the second protruding portion is disposed corresponding to the second sub-connecting hole.
The invention has the following beneficial technical effects: the severest load condition of the work of simulating the mainboard memory bank is simulated by adopting the simulated memory pull-up plate, the design index of the memory voltage specification is verified, the cost is low, the operation is simple and convenient, the labor hour is reduced, and the working efficiency and the test accuracy are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of an apparatus for simulating a memory current test according to the present invention;
FIG. 2 is a schematic view of a connection plate provided by the present invention;
fig. 3 is a schematic diagram of an analog memory pull carrier according to the present invention;
fig. 4 is a schematic view of a knife blade provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are only used for convenience of expression and should not be construed as a limitation to the embodiments of the present invention, and no description is given in the following embodiments.
In view of the above object, a first aspect of an embodiment of the present invention proposes an embodiment of a protection circuit for preventing reverse connection. Fig. 1 is a schematic diagram illustrating an embodiment of an apparatus for simulating a memory current test according to the present invention. As shown in fig. 1, an embodiment of the present invention includes the following components:
the analog memory pull-in board comprises a plurality of analog memory pull-in boards 1, wherein the analog memory pull-in boards 1 are arranged on memory strip slots of a mainboard 0 side by side, and each analog memory pull-in board 1 is provided with a plurality of groups of connecting strips 11;
a plurality of groups of connecting holes 21 are arranged on the connecting plate 2 side by side, and each group of connecting holes 21 is matched with each group of connecting strips 11 in shape so as to detachably fix the connecting plate 2 on the simulated memory pull carrier plate 1; and
the switch blade 3 is arranged on the connecting plate 2, a plurality of protruding parts 31 are arranged on the switch blade 3, the protruding parts 31 are arranged corresponding to the connecting holes 21, and the protruding parts 31 are inserted into the connecting holes 21 to enable the plurality of analog internal memory pull-up carrier plates 1 to form short circuits.
Fig. 2 shows a schematic view of a connection plate provided by the present invention. As shown in fig. 2, the connection plate 2 includes a plurality of sets of connection holes 21. In some embodiments, the connecting plate includes a first metal plate and a second metal plate, the first metal plate and the second metal plate are arranged side by side, and the first metal plate and the second metal plate are connected with an insulating material therebetween. As shown in fig. 2, the connection plate 2 includes a first metal plate 22a and a second metal plate 22b, the first metal plate 22a and the second metal plate 22b are arranged side by side, and the first metal plate 22a and the second metal plate 22b are connected with an insulating material therebetween.
In some embodiments, further comprising: the connecting plate is provided with a detachable pulling load line between every two groups of connecting holes. With continued reference to fig. 2, a detachable loading wire 23 is arranged between each two groups of connecting holes 21 of the connecting plate 2.
In some embodiments, each set of connection holes on the connection plate includes a first sub-connection hole and a second sub-connection hole, the first sub-connection hole and the second sub-connection hole are respectively disposed on the first metal plate and the second metal plate, and the first sub-connection hole and the second sub-connection hole are symmetrical with respect to the insulating material. With continued reference to fig. 2, each set of connection holes 21 on the connection plate 2 includes a first sub-connection hole 21a and a second sub-connection hole 21b, the first sub-connection hole 21a and the second sub-connection hole 21b are respectively provided in the first metal plate 22a and the second metal plate 22b, and the first sub-connection hole 21a and the second sub-connection hole 21b are symmetrical with respect to the insulating material.
Fig. 3 is a schematic diagram of an analog memory pull carrier board provided by the present invention. As shown in fig. 3, one end of the analog memory pull-in carrier plate 1 includes a plurality of groups of connecting strips 11, and the other end is connected with the memory strip slot, so that the PIN can be defined consistently with the PIN of the memory strip slot of the motherboard, and the design can be performed by using a gold finger. In some embodiments, each group of the connection bars of the analog internal memory pull-up carrier plate includes a power connection bar and a ground connection bar, and the distances between the power connection bars and the ground connection bars of each group are the same. As shown in fig. 3, the analog rrav board 1 includes three sets of connection bars, but this is only exemplary, and in other embodiments, other numbers of connection bars may be adopted, and each set of connection bars includes one power connection bar and one ground connection bar. In some embodiments, the power types corresponding to the power connection bars in different groups of connection bars on the same analog memory pull-up carrier are different. The power supply connection bars in this embodiment are VDD, VTT and VPP, respectively, and are denoted by 13a, 13b and 13c, respectively, and the ground connection bar is denoted by 14.
In some embodiments, the power connection bars of the same power type in the plurality of analog memory pull-up carrier boards are arranged at the same position. In order to facilitate the test, the plurality of analog internal memory pull-up carrier boards may be designed to be identical, and certainly, the position fixing of the power connection bars of different power types on each analog internal memory pull-up carrier board is also included. For example, in the analog memory pull-up board a1, the VDD, VTT and VPP power connection bars are arranged in 13a, 13b and 13c, and in the analog memory pull-up board a2, the VDD, VTT and VPP power connection bars may also be arranged in 13a, 13b and 13c.
In some embodiments, the distance between the first sub-connection hole and the second sub-connection hole is the same as the distance between two sub-connection bars in the corresponding group of connection bars. The sub-connecting strips are different types of power supply connecting strips and ground connecting strips, and the connecting holes and the connecting strips are matched for use, so that the distance between two sub-connecting holes in each group of connecting holes is the same as the distance between two sub-connecting strips in the corresponding group of connecting strips.
In some embodiments, a plurality of sub-connection portions are disposed on the blade corresponding to the plurality of sets of connection holes, and the plurality of sub-connection portions are disposed in parallel. Fig. 4 is a schematic view of a blade according to the present invention. As shown in fig. 4, a plurality of sub-connecting portions 32 are provided on the blade 3 corresponding to the plurality of sets of connecting holes 21, the plurality of sub-connecting portions 32 are arranged in parallel and converge at a connecting portion 33, and the connecting portion 33 is connected to a handle 34, so that the movement of the plurality of sub-connecting portions 32 can be simultaneously controlled by the handle 34.
In some embodiments, each of the sub-connecting portions is provided with a first protruding portion and a second protruding portion, the first protruding portion is disposed corresponding to the first sub-connecting hole, and the second protruding portion is disposed corresponding to the second sub-connecting hole. With continued reference to fig. 4, the sub-connecting portion 32 is provided with a first protruding portion 31a and a second protruding portion 31b, the first protruding portion 31a is disposed corresponding to the first sub-connecting hole 21a, and the second protruding portion 31b is disposed corresponding to the second sub-connecting hole 21 b. When the knife switch is lifted up (VDD \ VTT \ VPP) and the GND are disconnected, and the knife switch is closed when an output short-circuit test is needed, and (VDD \ VTT \ VPP) and the GND are quickly connected. Due to the short loop, the protection test can be realized quickly.
When a test item needing to be subjected to electronic load pull load test is tested, connecting a pull load wire to an electronic load, and setting the electronic load; powering on the mainboard to be tested, and carrying out corresponding pull load test; and (3) powering off the mainboard to be tested, disconnecting the switch blade when a short-circuit protection test item requiring memory voltage is carried out, quickly closing the switch blade after the mainboard is powered on, and completing short-circuit protection.
The foregoing are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, where the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also combinations between technical features in the above embodiments or in different embodiments are possible, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit or scope of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (9)
1. An apparatus for simulating memory current testing, comprising:
the memory module comprises a plurality of analog memory pull-up carrier plates, a plurality of memory module slots and a plurality of connecting strips, wherein the analog memory pull-up carrier plates are arranged on the memory module slots side by side;
the connecting plate is provided with a plurality of groups of connecting holes side by side, and each group of connecting holes is matched with each group of connecting strips in shape so as to detachably fix the connecting plate on the analog memory pull carrier plate; and
the switch blade is arranged on the connecting plate, and is provided with a plurality of protruding parts which are arranged corresponding to the connecting holes so as to enable the plurality of analog memory pull carrier plates to form short circuits by inserting the protruding parts into the connecting holes;
the connecting plate is provided with a detachable pulling load line between every two groups of connecting holes.
2. The device of claim 1, wherein each group of the connection bars of the analog dram carrier board comprises a power connection bar and a ground connection bar, and the distances between the power connection bar and the ground connection bar of each group are the same.
3. The apparatus of claim 2, wherein the power types corresponding to the power connection bars in different groups of connection bars on the same analog DRAM carrier are different.
4. The apparatus of claim 3, wherein the power connection bars of the same power type in the plurality of analog memory pull-up boards are disposed at the same position.
5. The apparatus of claim 1, wherein the connecting plate comprises a first metal plate and a second metal plate, the first metal plate and the second metal plate are arranged side by side, and the first metal plate and the second metal plate are connected with an insulating material therebetween.
6. The apparatus of claim 5, wherein each set of connection holes on the connection plate includes a first sub-connection hole and a second sub-connection hole, the first sub-connection hole and the second sub-connection hole being disposed on the first metal plate and the second metal plate, respectively, the first sub-connection hole and the second sub-connection hole being symmetrical with respect to the insulating material.
7. The apparatus of claim 6, wherein the distance between the first sub-connection hole and the second sub-connection hole is the same as the distance between two sub-connection bars in a corresponding set of the connection bars.
8. The device as claimed in claim 7, wherein a plurality of sub-connecting portions are provided on the blade corresponding to the plurality of sets of connecting holes, and the plurality of sub-connecting portions are arranged in parallel.
9. The apparatus of claim 8, wherein each of the sub-connecting portions has a first protrusion and a second protrusion, the first protrusion corresponding to the first sub-connecting hole, and the second protrusion corresponding to the second sub-connecting hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010669479.3A CN111856247B (en) | 2020-07-13 | 2020-07-13 | Device for simulating memory current test |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010669479.3A CN111856247B (en) | 2020-07-13 | 2020-07-13 | Device for simulating memory current test |
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| CN111856247A CN111856247A (en) | 2020-10-30 |
| CN111856247B true CN111856247B (en) | 2022-12-06 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201429631Y (en) * | 2009-03-19 | 2010-03-24 | 张光荣 | Memory bar protection test socket |
| CN201444524U (en) * | 2009-03-19 | 2010-04-28 | 张光荣 | Memory switching test bench |
| CN102880534A (en) * | 2012-07-20 | 2013-01-16 | 曙光信息产业(北京)有限公司 | Testing method for memory voltage of Loongson server motherboard |
| CN203397348U (en) * | 2013-07-19 | 2014-01-15 | 浪潮电子信息产业股份有限公司 | Novel memory-chip testing jig |
| CN110032483A (en) * | 2019-04-15 | 2019-07-19 | 苏州浪潮智能科技有限公司 | A kind of method, apparatus and medium adjusting test parameter |
| CN210182075U (en) * | 2019-07-26 | 2020-03-24 | 厦门市原子通电子科技有限公司 | Short circuit testing device for memory power supply circuit |
-
2020
- 2020-07-13 CN CN202010669479.3A patent/CN111856247B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201429631Y (en) * | 2009-03-19 | 2010-03-24 | 张光荣 | Memory bar protection test socket |
| CN201444524U (en) * | 2009-03-19 | 2010-04-28 | 张光荣 | Memory switching test bench |
| CN102880534A (en) * | 2012-07-20 | 2013-01-16 | 曙光信息产业(北京)有限公司 | Testing method for memory voltage of Loongson server motherboard |
| CN203397348U (en) * | 2013-07-19 | 2014-01-15 | 浪潮电子信息产业股份有限公司 | Novel memory-chip testing jig |
| CN110032483A (en) * | 2019-04-15 | 2019-07-19 | 苏州浪潮智能科技有限公司 | A kind of method, apparatus and medium adjusting test parameter |
| CN210182075U (en) * | 2019-07-26 | 2020-03-24 | 厦门市原子通电子科技有限公司 | Short circuit testing device for memory power supply circuit |
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| CN111856247A (en) | 2020-10-30 |
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