CN113138889B - Test circuit and server - Google Patents
Test circuit and server Download PDFInfo
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- CN113138889B CN113138889B CN202110327948.8A CN202110327948A CN113138889B CN 113138889 B CN113138889 B CN 113138889B CN 202110327948 A CN202110327948 A CN 202110327948A CN 113138889 B CN113138889 B CN 113138889B
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- 238000012360 testing method Methods 0.000 title claims abstract description 132
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052742 iron Inorganic materials 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
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- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a test circuit and a server, wherein the test circuit comprises: a signal control unit; the first test component is connected to a first preset signal output pin of the signal control unit; the grid electrode of the first Mos tube is connected to a first signal output pin of the signal control unit, the drain electrode of the first Mos tube is connected to a first preset signal output pin, and the source electrode of the first Mos tube is grounded; a second test part and a third test part; and the source electrode of the second Mos tube is connected to the second test component, the drain electrode of the second Mos tube is connected to a second preset signal pin of the third test component, and the grid electrode of the second Mos tube is connected to a second signal output pin of the signal control unit. By using the scheme of the invention, the test time can be saved, the risk of board damage is reduced, and the product competitiveness is improved.
Description
Technical Field
The field relates to the field of computers, and more particularly to a test circuit and server.
Background
In order to ensure that the server can accurately record various conditions encountered by the system during operation, it is necessary to simulate various possible system conditions during the development stage, so that the system generates errors during operation, and observe whether the system has normal alarms or not, and when the errors disappear, whether the system resumes normal operation and cancels the alarms. If the simulation error occurs, the system does not alarm normally or the system cannot operate normally after the error is removed, which indicates that careless mistakes occur in which aspect of the design needs to be tested again, and then the design is modified and verified again.
Such measurements are quite extensive and are typically performed in a manner that artificially causes some signals to be short or open. Because of the need to create a short circuit while the system is running, if a signal is manually shorted or disconnected, it is easy to mistouch other signals, resulting in unexpected results. Therefore, the signal to be tested is pulled out in the way of external welding circuit, and is grounded to produce the effect of short circuit during testing, or the serial connection assembly is removed, the external circuit is welded to communicate the signal, and is cut off to produce an open circuit during testing. This test method requires great care in handling because it requires manual handling of the soldering iron, leaves residual tin on the board somewhat inadvertently, or some passive components are damaged by the high temperature of the soldering iron. Moreover, the system needs to be shut down when the soldering iron is operated, and then the system needs to be started up for testing after the operation is finished, so that the time spent on each test item is very long. The time it takes to perform a complete test can be longer, and if the design is modified after the test fails and then retested, the time it takes is more difficult to estimate.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a test circuit and a server, which can save test time, reduce the risk of board damage, and improve product competitiveness by using the technical solution of the present invention.
In view of the above object, an aspect of an embodiment of the present invention provides a test circuit including:
a signal control unit;
the first test component is connected to a first preset signal output pin of the signal control unit;
the grid electrode of the first Mos tube is connected to a first signal output pin of the signal control unit, the drain electrode of the first Mos tube is connected to a first preset signal output pin, and the source electrode of the first Mos tube is grounded;
a second test part and a third test part;
and the source electrode of the second Mos tube is connected to the second test component, the drain electrode of the second Mos tube is connected to a second preset signal pin of the third test component, and the grid electrode of the second Mos tube is connected to a second signal output pin of the signal control unit.
According to one embodiment of the invention, the signal control unit comprises a BMC configured to cause the first signal output pin and the second signal output pin to output a high voltage or a low voltage according to a test requirement.
According to an embodiment of the present invention, the first test part includes a fan, and the first preset signal output pin is configured to output a PWM (pulse width modulation) signal.
According to one embodiment of the invention, the second test component comprises a CPLD, the third test component comprises a PSU, and the second predetermined signal pin is configured to output a PS _ ON signal output by the PSU.
According to an embodiment of the present invention, further comprising:
and the Dummy unit has one end connected to the source electrode of the second Mos tube and the other end connected to the drain electrode of the second Mos tube, and comprises a 0 ohm resistor, wherein the 0 ohm resistor is configured to be separated from the Dummy unit in a test stage of the test circuit so as to disconnect two ends of the Dummy unit, and is connected to the Dummy unit in a non-test stage of the test circuit so as to connect two ends of the Dummy unit.
In another aspect of the embodiments of the present invention, there is also provided a server, including a test circuit, the test circuit including:
a signal control unit;
the first test component is connected to a first preset signal output pin of the signal control unit;
the grid electrode of the first Mos tube is connected to a first signal output pin of the signal control unit, the drain electrode of the first Mos tube is connected to a first preset signal output pin, and the source electrode of the first Mos tube is grounded;
a second test part and a third test part;
and the source electrode of the second Mos tube is connected to the second test component, the drain electrode of the second Mos tube is connected to a second preset signal pin of the third test component, and the grid electrode of the second Mos tube is connected to a second signal output pin of the signal control unit.
According to one embodiment of the invention, the signal control unit comprises a BMC configured to cause the first signal output pin and the second signal output pin to output a high voltage or a low voltage according to a test requirement.
According to an embodiment of the present invention, the first test component includes a fan, and the first preset signal output pin is configured to output a PWM signal.
According to one embodiment of the invention, the second test component comprises a CPLD, the third test component comprises a PSU, and the second predetermined signal pin is configured to output a PS _ ON signal output by the PSU.
According to an embodiment of the present invention, further comprising:
and the Dummy unit has one end connected to the source electrode of the second Mos tube and the other end connected to the drain electrode of the second Mos tube, and comprises a 0 ohm resistor, wherein the 0 ohm resistor is configured to be separated from the Dummy unit in a test stage of the test circuit so as to disconnect two ends of the Dummy unit, and is connected to the Dummy unit in a non-test stage of the test circuit so as to connect two ends of the Dummy unit.
The invention has the following beneficial technical effects: the test circuit provided by the embodiment of the invention is provided with the signal control unit; the first test component is connected to a first preset signal output pin of the signal control unit; the grid electrode of the first Mos tube is connected to a first signal output pin of the signal control unit, the drain electrode of the first Mos tube is connected to a first preset signal output pin, and the source electrode of the first Mos tube is grounded; a second test part and a third test part; the source electrode of the second Mos tube is connected to the second testing component, the drain electrode of the second Mos tube is connected to the second preset signal pin of the third testing component, and the grid electrode of the second Mos tube is connected to the second signal output pin of the signal control unit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of a test circuit according to one embodiment of the present invention;
fig. 2 is a schematic diagram of a server according to one embodiment of the invention.
Detailed Description
Embodiments of the present disclosure are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; certain features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment for a typical application. However, various combinations and modifications of the features consistent with the teachings of the present disclosure may be desirable for certain specific applications or implementations.
In view of the above objects, a first aspect of embodiments of the present invention proposes an embodiment of a test circuit. Fig. 1 shows a schematic diagram of the test circuit.
As shown in fig. 1, the test circuit may include:
the signal control unit comprises a BMC which is configured to enable a corresponding signal pin to output high voltage or low voltage according to test requirements, and can also be other devices with similar functions;
a first test part connected to a first preset signal output pin of the signal control unit, the first test part being a device such as a fan, the first preset signal being a PWM signal provided by the signal control unit when the first test part is the fan;
the gate of the first Mos tube is connected to a first signal output pin of the signal control unit, the drain of the first Mos tube is connected to a first preset signal output pin, the source of the first Mos tube is grounded, when a tester needs to short-circuit the PWM signal, the first signal output pin of the signal control unit is controlled to pull the voltage to P3V3 through an IPMI (intelligent platform management interface) instruction, the source and the drain of the first Mos tube are conducted, the PWM signal is connected to the ground through the drain and the source of the first Mos tube to form a short-circuit test environment, and the first Mos tube can be directly removed after the test is finished;
a second test component which may be a CPLD (complex programmable logic device) and a third test component which may be a PSU (power supply unit);
and when the PS _ ON needs to be opened, the second signal output pin of the signal control unit is controlled to be low voltage through an IPMI instruction, the source and the drain of the second Mos tube are turned off, and an open-circuit test environment is formed between the CPLD and the PSU.
By the technical scheme, the test time can be saved, the risk of board damage is reduced, and the product competitiveness is improved.
In a preferred embodiment of the present invention, the signal control unit includes a BMC configured to enable the first signal output pin and the second signal output pin to output a high voltage or a low voltage according to a test requirement, and the signal control unit may also be other devices with similar functions.
In a preferred embodiment of the present invention, the first test part includes a fan, and the first preset signal output pin outputs a PWM signal, which is provided by the signal control unit. When a tester needs to short-circuit the PWM signal, the voltage is pulled to P3V3 through a first signal output pin of an IPMI (intelligent platform management interface) instruction control signal control unit, a source electrode and a drain electrode of the first Mos tube are conducted, the PWM signal is connected to the ground through the drain electrode and the source electrode of the first Mos tube to form a short-circuit test environment, and the first Mos tube can be directly removed after the test is finished.
In a preferred embodiment of the present invention, the second test component comprises a CPLD, the third test component comprises a PSU, and the second predetermined signal pin comprises a PS _ ON signal output by the PSU. When the PS _ ON needs to be opened, the second signal output pin of the signal control unit is controlled to be low voltage through the IPMI instruction, the source and the drain of the second Mos tube are turned off, and an open-circuit test environment is formed between the CPLD and the PSU.
In a preferred embodiment of the present invention, the method further comprises:
and one end of the Dummy unit is connected to the source electrode of the second Mos tube, the other end of the Dummy unit is connected to the drain electrode of the second Mos tube, the Dummy unit comprises a 0 ohm resistor, the 0 ohm resistor is configured to be separated from the Dummy unit by an on-off device so as to disconnect two ends of the Dummy unit when the test circuit is in a test stage, and the 0 ohm resistor is connected into the Dummy unit so as to connect two ends of the Dummy unit when the test circuit is in a non-test stage. The Dummy unit is arranged between the CPLD and the PSU, and the middle of a circuit of the Dummy unit is provided with a 0 ohm resistor without loading, because the test of hardware link disconnection only exists in the development stage, the test item is not needed after the product is produced in mass, so that the Mos tubes are not needed to be reserved, the Mos tubes can be removed from the BOM table after the test is finished, but the signal for performing the open circuit test is directly opened after the Mos tubes are removed, so that the system cannot be operated, therefore, a resistor circuit without loading is reserved, and when the Mos tubes are removed from the BOM table, the 0 ohm resistor loading is needed. Because the cost of the resistor is extremely low, the cost is very little for the BOM table after the production.
By the technical scheme, the test time can be saved, the risk of damage of the board card is reduced, and the product competitiveness is improved.
In view of the above object, a second aspect of the embodiments of the present invention proposes a server 1, as shown in fig. 2, the server 1 including a test circuit, the test circuit including:
a signal control unit;
the first test component is connected to a first preset signal output pin of the signal control unit;
the grid electrode of the first Mos tube is connected to a first signal output pin of the signal control unit, the drain electrode of the first Mos tube is connected to a first preset signal output pin, and the source electrode of the first Mos tube is grounded;
a second test part and a third test part;
and the source electrode of the second Mos tube is connected to the second test component, the drain electrode of the second Mos tube is connected to a second preset signal pin of the third test component, and the grid electrode of the second Mos tube is connected to a second signal output pin of the signal control unit.
In a preferred embodiment of the present invention, the signal control unit includes a BMC configured to cause the first signal output pin and the second signal output pin to output a high voltage or a low voltage according to a test requirement.
In a preferred embodiment of the present invention, the first test part includes a fan, and the first preset signal output pin outputs a PWM signal.
In a preferred embodiment of the present invention, the second test component comprises a CPLD, the third test component comprises a PSU, and the second predetermined signal pin comprises a PS _ ON signal output by the PSU.
In a preferred embodiment of the present invention, the method further comprises:
and one end of the Dummy unit is connected to the source electrode of the second Mos tube, the other end of the Dummy unit is connected to the drain electrode of the second Mos tube, the Dummy unit comprises a 0 ohm resistor, the 0 ohm resistor is configured to be not connected into the Dummy unit so as to disconnect two ends of the Dummy unit when the test circuit is in a test stage, and the 0 ohm resistor is connected into the Dummy unit so as to connect two ends of the Dummy unit when the test circuit is in a non-test stage.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
The embodiments described above, particularly any "preferred" embodiments, are possible examples of implementations and are presented merely to clearly understand the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing from the spirit and principles of the technology described herein. All such modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Claims (10)
1. A test circuit, comprising:
a signal control unit;
a first test component connected to a first preset signal output pin of the signal control unit;
a grid electrode of the first Mos tube is connected to a first signal output pin of the signal control unit, a drain electrode of the first Mos tube is connected to the first preset signal output pin, and a source electrode of the first Mos tube is grounded;
a second test part and a third test part;
and the source electrode of the second Mos tube is connected to the second test component, the drain electrode of the second Mos tube is connected to a second preset signal pin of the third test component, and the grid electrode of the second Mos tube is connected to a second signal output pin of the signal control unit.
2. The test circuit of claim 1, wherein the signal control unit comprises a BMC configured to cause the first signal output pin and the second signal output pin to output a high voltage or a low voltage according to a test requirement.
3. The test circuit of claim 1, wherein the first test component comprises a fan, and wherein the first preset signal output pin is configured to output a PWM signal.
4. The test circuit of claim 1, wherein the second test component comprises a CPLD, the third test component comprises a PSU, and the second predetermined signal pin is configured to output a PS _ ON signal output by the PSU.
5. The test circuit of claim 1, further comprising:
the Dummy unit is connected with one end of the second Mos tube and the other end of the second Mos tube, and comprises a 0 ohm resistor, wherein the 0 ohm resistor is configured to be separated from the Dummy unit when the test circuit is in a test stage so as to disconnect two ends of the Dummy unit, and is connected into the Dummy unit when the test circuit is in a non-test stage so as to connect two ends of the Dummy unit.
6. A server, comprising a test circuit, the test circuit comprising:
a signal control unit;
a first test part connected to a first preset signal output pin of the signal control unit;
a grid electrode of the first Mos tube is connected to a first signal output pin of the signal control unit, a drain electrode of the first Mos tube is connected to the first preset signal output pin, and a source electrode of the first Mos tube is grounded;
a second test part and a third test part;
and the source electrode of the second Mos tube is connected to the second test component, the drain electrode of the second Mos tube is connected to a second preset signal pin of the third test component, and the grid electrode of the second Mos tube is connected to a second signal output pin of the signal control unit.
7. The server according to claim 6, wherein the signal control unit comprises a BMC configured to cause the first signal output pin and the second signal output pin to output a high voltage or a low voltage according to a test requirement.
8. The server of claim 6, wherein the first test component comprises a fan, and wherein the first preset signal output pin is configured to output a PWM signal.
9. The server according to claim 6, wherein the second test component comprises a CPLD, the third test component comprises a PSU, and the second predetermined signal pin is configured to output a PS _ ON signal output by the PSU.
10. The server of claim 6, further comprising:
the Dummy unit is connected with one end of the second Mos tube and the other end of the second Mos tube, and comprises a 0 ohm resistor, wherein the 0 ohm resistor is configured to be separated from the Dummy unit when the test circuit is in a test stage so as to disconnect two ends of the Dummy unit, and is connected into the Dummy unit when the test circuit is in a non-test stage so as to connect two ends of the Dummy unit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110327948.8A CN113138889B (en) | 2021-03-26 | 2021-03-26 | Test circuit and server |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110327948.8A CN113138889B (en) | 2021-03-26 | 2021-03-26 | Test circuit and server |
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| Publication Number | Publication Date |
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| CN113138889A CN113138889A (en) | 2021-07-20 |
| CN113138889B true CN113138889B (en) | 2022-05-17 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202548256U (en) * | 2012-03-19 | 2012-11-21 | 鸿富锦精密工业（深圳）有限公司 | Short-circuit test device |
| CN206639004U (en) * | 2017-04-07 | 2017-11-14 | 广州地铁集团有限公司 | A kind of on-off control device |
| CN111752776A (en) * | 2020-05-29 | 2020-10-09 | 苏州浪潮智能科技有限公司 | Cyclic power-on and power-off test method and system for server |
| CN111831498A (en) * | 2020-07-17 | 2020-10-27 | 浪潮商用机器有限公司 | Power failure test method, device and equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4811902B2 (en) * | 2004-12-24 | 2011-11-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for testing semiconductor device |
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- 2021-03-26 CN CN202110327948.8A patent/CN113138889B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202548256U (en) * | 2012-03-19 | 2012-11-21 | 鸿富锦精密工业（深圳）有限公司 | Short-circuit test device |
| CN206639004U (en) * | 2017-04-07 | 2017-11-14 | 广州地铁集团有限公司 | A kind of on-off control device |
| CN111752776A (en) * | 2020-05-29 | 2020-10-09 | 苏州浪潮智能科技有限公司 | Cyclic power-on and power-off test method and system for server |
| CN111831498A (en) * | 2020-07-17 | 2020-10-27 | 浪潮商用机器有限公司 | Power failure test method, device and equipment |
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