CN111837339A - 锁相环电路以及应用锁相环电路的设备 - Google Patents
锁相环电路以及应用锁相环电路的设备 Download PDFInfo
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- CN111837339A CN111837339A CN201880091073.2A CN201880091073A CN111837339A CN 111837339 A CN111837339 A CN 111837339A CN 201880091073 A CN201880091073 A CN 201880091073A CN 111837339 A CN111837339 A CN 111837339A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
一种锁相环电路,涉及数字电路领域,用于跟踪和生成时钟信号。该锁相环电路包括目标频率相等的参考相位产生电路和时钟信号产生电路,上述参考相位产生电路根据第一参考相位信号产生第二参考相位信号,上述时钟产生电路根据上述第二参考相位信号产生输出时钟信号,其中上述第一参考相位信号、第二参考相位信号和输出时钟信号的相位差均为0。由于参考相位产生电路和时钟信号产生电路之间没有反馈支路,时钟信号产生电路中的杂散和抖动不会反馈至参考相位产生电路,因此提升了锁相环电路的整体性能,提高输出时钟信号的精度。
Description
PCT国内申请,说明书已公开。
Claims (8)
- PCT国内申请,权利要求书已公开。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/CN2018/102654 WO2020041967A1 (zh) | 2018-08-28 | 2018-08-28 | 锁相环电路以及应用锁相环电路的设备 |
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CN111837339A true CN111837339A (zh) | 2020-10-27 |
CN111837339B CN111837339B (zh) | 2022-06-28 |
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US20170346493A1 (en) * | 2016-05-25 | 2017-11-30 | Imec Vzw | DTC-Based PLL and Method for Operating the DTC-Based PLL |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104485951A (zh) * | 2014-12-15 | 2015-04-01 | 佳律通信设备(上海)有限公司 | 带锁相环(pll)的频率合成源电路及控制方法 |
CN204376874U (zh) * | 2015-02-03 | 2015-06-03 | 苏州市灵矽微***有限公司 | 时钟产生电路 |
CN107425849A (zh) * | 2017-07-05 | 2017-12-01 | 电子科技大学 | 一种可锁相恒定频率的多相操作电路 |
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2018
- 2018-08-28 WO PCT/CN2018/102654 patent/WO2020041967A1/zh active Application Filing
- 2018-08-28 CN CN201880091073.2A patent/CN111837339B/zh active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5579351A (en) * | 1994-10-19 | 1996-11-26 | Lg Information & Communications, Ltd. | Jitter suppression circuit |
US20030112043A1 (en) * | 2001-12-19 | 2003-06-19 | Ando Electric Co., Ltd. | PLL circuit and control method for PLL circuit |
US20030117195A1 (en) * | 2001-12-20 | 2003-06-26 | Horng-Der Chang | Hybrid phase-locked loop |
US20040008805A1 (en) * | 2002-07-15 | 2004-01-15 | Texas Instruments Incorporated | Precision jitter-free frequency synthesis |
KR20040027350A (ko) * | 2002-09-26 | 2004-04-01 | 엔이씨 일렉트로닉스 코포레이션 | 정상 상태 위상 오차를 줄인 위상 동기 루프 회로 |
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CN107222209A (zh) * | 2011-06-08 | 2017-09-29 | 美国亚德诺半导体公司 | 数模混合锁相环 |
CN103152036A (zh) * | 2011-12-07 | 2013-06-12 | 珠海扬智电子科技有限公司 | 鉴相滤波器、数字锁相环电路和时钟发生方法 |
CN103684436A (zh) * | 2012-09-10 | 2014-03-26 | 国际商业机器公司 | 锁相环电路和使用锁相环来生成时钟信号的方法 |
CN103490777A (zh) * | 2013-09-30 | 2014-01-01 | 四川九洲电器集团有限责任公司 | 低杂散频率合成器 |
JP2015220726A (ja) * | 2014-05-21 | 2015-12-07 | 三菱電機株式会社 | Pll回路 |
CN104917519A (zh) * | 2014-07-16 | 2015-09-16 | 美商威睿电通公司 | 锁相环电路 |
CN104320134A (zh) * | 2014-10-27 | 2015-01-28 | 海能达通信股份有限公司 | 快速锁定的频率产生电路 |
US9705515B1 (en) * | 2016-01-11 | 2017-07-11 | Electronics And Telecommunications Research Institute | Digital phase locked loop and method of driving the same |
US20170346493A1 (en) * | 2016-05-25 | 2017-11-30 | Imec Vzw | DTC-Based PLL and Method for Operating the DTC-Based PLL |
Non-Patent Citations (1)
Title |
---|
徐江涛等: "一种高速低相位噪声锁相环的设计", 《天津大学学报》 * |
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Publication number | Publication date |
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CN111837339B (zh) | 2022-06-28 |
WO2020041967A1 (zh) | 2020-03-05 |
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