CN111599691A - 一种基于fc芯片的双面挖腔陶瓷封装工艺 - Google Patents

一种基于fc芯片的双面挖腔陶瓷封装工艺 Download PDF

Info

Publication number
CN111599691A
CN111599691A CN202010459064.3A CN202010459064A CN111599691A CN 111599691 A CN111599691 A CN 111599691A CN 202010459064 A CN202010459064 A CN 202010459064A CN 111599691 A CN111599691 A CN 111599691A
Authority
CN
China
Prior art keywords
ceramic
chip
digging
ceramic substrate
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010459064.3A
Other languages
English (en)
Inventor
胡孝伟
代文亮
伊海伦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Sinbo Electronic Technology Co ltd
Original Assignee
Shanghai Sinbo Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Sinbo Electronic Technology Co ltd filed Critical Shanghai Sinbo Electronic Technology Co ltd
Priority to CN202010459064.3A priority Critical patent/CN111599691A/zh
Publication of CN111599691A publication Critical patent/CN111599691A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807Ceramic parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Ceramic Products (AREA)

Abstract

本发明的一种基于FC芯片的双面挖腔陶瓷封装工艺,在陶瓷基板上下面的芯片贴装位置进行预先挖腔,封装时将FC芯片分别沉到相应的陶瓷腔里并与陶瓷基板连接,将盖板通过合金熔封的工艺焊接在陶瓷基板四周的焊接区内,并在陶瓷基板背面植球,完成封装。通过在陶瓷基板两侧面挖腔形成上空腔和下空腔,上空腔和下空腔内分别安装有FC芯片,使得陶瓷基板的封装空间变大,提高了陶瓷封装的空间利用率且降低了陶瓷封装的外形尺寸。

Description

一种基于FC芯片的双面挖腔陶瓷封装工艺
技术领域
本发明属于芯片陶瓷封装技术领域,具体来说是一种基于FC芯片的双面挖腔陶瓷封装工艺。
背景技术
随着半导体技术的不断发展,越来越多的芯片种类被开发出来以适用于不同的市场需求,其中FC芯片是为现阶段封装所使用的主流芯片之一。然而现有的FC芯片的陶瓷封装结构由于内部空间小,存在难以满足需求的问题。
发明内容
1.发明要解决的技术问题
本发明的目的在于解决现有的FC芯片陶瓷封装结构由于内部空间小,难以满足需求的问题。
2.技术方案
为达到上述目的,本发明提供的技术方案为:
本发明的一种基于FC芯片的双面挖腔陶瓷封装工艺,在陶瓷基板两侧面的芯片贴装位置进行预先挖腔,封装时将FC芯片分别沉到相应的陶瓷腔里并与陶瓷基板连接,将盖板通过合金熔封的工艺焊接在陶瓷基板四周的焊接区内,并在陶瓷基板背面植球,完成封装。
优选的,所述封装工艺具体包括如下步骤:
S100、挖腔,在陶瓷基板两侧面的芯片贴装位置进行挖腔;
S200、绝缘,对同一面的腔体之间进行相互隔离;
S300、贴装,将FC芯片分别沉到相应的陶瓷腔里并进行固定;
S400、粘合,使用填充胶填充FC芯片与陶瓷基板之间;
S500、封帽,将盖板通过合金熔封的方式焊接在陶瓷基板顶部的焊接区内;
S600、植球,对陶瓷基板背面植球,完成封装。
优选的,所述步骤S100中的挖腔具体为先将各生瓷片通过激光或者机械冲制在相应位置开出槽,再将各层生瓷片叠加在一起进行烧结,该相应位置的槽在叠加一起之后形成了腔体。
优选的,所述步骤S200中的相互隔离具体是将腔体之间陶瓷体上打满接地孔。
优选的,所述步骤S300中的贴装具体为将FC芯片以表贴的方式贴装到陶瓷基板的腔体中,贴装精度控制在±35um以内。
优选的,所述步骤S400具体为使用填充胶填充FC芯片与陶瓷基板之间后,再进行烘烤使得填充胶凝固,所述烘烤的具体过程为将陶瓷基板置于150℃的温度下烘烤30~40分钟,使填充胶完全固化。
优选的,所述步骤S400中的粘合具体为对腔体中的FC芯片底部的锡球进行底部填充胶。
优选的,所述步骤5600中焊接区的宽度为1.5~2.0mm。
优选的,所述挖腔深度为0.2~0.4mm。
3.有益效果
采用本发明提供的技术方案,与现有技术相比,具有如下有益效果:
本发明的一种基于FC芯片的双面挖腔陶瓷封装工艺,在陶瓷基板上下面的芯片贴装位置进行预先挖腔,封装时将FC芯片分别沉到相应的陶瓷腔里并与陶瓷基板连接,将盖板通过合金熔封的工艺焊接在陶瓷基板四周的焊接区内,并在陶瓷基板背面植球,完成封装。通过在陶瓷基板两侧面挖腔形成上空腔和下空腔,上空腔和下空腔内分别安装有FC芯片,使得陶瓷基板的封装空间变大,提高了陶瓷封装的空间利用率且降低了陶瓷封装的外形尺寸。
附图说明
图1为本实施例的制备的封装结构的内部俯视图;
图2为本实施例的制备的封装结构的内部仰视图;
图3为本实施例的制备的封装结构的结构示意图;
图4为本发明的工艺流程图。
示意图中的标号说明:
1、陶瓷基板;2、焊接区;3、上空腔;4、下空腔;5、FC芯片;6、锡球;7、点胶层;8、盖板;9、植球。
具体实施方式
为了便于理解本发明,下面将参照相关附图对本发明进行更全面的描述,附图中给出了本发明的若干实施例,但是,本发明可以以许多不同的形式来实现,并不限于本文所描述的实施例,相反地,提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
需要说明的是,当元件被称为“固设于”另一个元件,它可以直接在另一个元件上或者也可以存在居中的元件;当一个元件被认为是“连接”另一个元件,它可以是直接连接到另一个元件或者可能同时存在居中元件;本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的。
除非另有定义,本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同;本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本发明;本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
实施例1
参照附图1-附图3,本实施例的一种基于FC芯片的双面挖腔陶瓷封装工艺,在陶瓷基板1两侧面的芯片贴装位置进行预先挖腔,封装时将FC芯片5分别沉到相应的陶瓷腔里并与陶瓷基板1连接,将盖板8通过合金熔封的工艺焊接在陶瓷基板1四周的焊接区2内,并在陶瓷基板1背面植球9,完成封装。
其中,封装工艺具体包括如下步骤:
S100、挖腔,在陶瓷基板1两侧面的芯片贴装位置进行挖腔,挖腔深度为0.2~0.4mm。;
S200、绝缘,对同一面的腔体之间进行相互隔离;
S300、贴装,将FC芯片5分别沉到相应的陶瓷腔里并进行固定;
S400、粘合,使用填充胶填充FC芯片5与陶瓷基板1之间;
S500、封帽,将盖板8通过合金熔封的方式焊接在陶瓷基板1顶部的焊接区2内;
S600、植球,对陶瓷基板1背面植球,完成封装。
步骤S100中的挖腔具体为先将各生瓷片通过激光或者机械冲制在相应位置开出槽,再将各层生瓷片叠加在一起进行烧结,该相应位置的槽在叠加一起之后形成了腔体。通过预先在各生瓷片上进行开槽然后组装烧结形成腔体,比整体烧结后进行开孔形成腔体更加稳定且腔体尺寸可控,且降低烧结后开孔过程对陶瓷基板1造成的结构性损害,大大提升了陶瓷基板1的完整性和稳定性。
步骤S200中的相互隔离具体是将腔体之间陶瓷体上打满接地孔,防止相邻间的腔体的元器件之间互相造成干扰,提升了整体芯片的稳定性。
步骤S300中的贴装具体为将FC芯片5以表贴的方式贴装到陶瓷基板1的腔体中,贴装精度控制在±35um以内。
步骤S400具体为使用填充胶填充FC芯片5与陶瓷基板1之间后,再进行烘烤使得填充胶凝固,所述烘烤的具体过程为将陶瓷基板1置于150℃的温度下烘烤30~40分钟,使填充胶完全固化形成点胶层7,填充胶完全固化后可以对FC芯片5与陶瓷基板1进行良好的的固定,提升整体封装结构的稳定性。
步骤S600中焊接区2的宽度为1.5~2.0mm。
本实施例的工艺制备的封装结构包括陶瓷基板1和FC芯片5,所述陶瓷基板1的两侧向内凹陷形成上空腔3和下空腔4,所述上空腔3和下空腔4内均设有FC芯片5,所述上空腔3和下空腔4内壁通过锡球6与FC芯片5固定,所述FC芯片5与锡球6之间还填充有点胶层7,所述陶瓷基板1底部设有若干个均匀分布的植球9。通过在陶瓷基板1两侧面挖腔形成上空腔3和下空腔4,上空腔3和下空腔4内分别安装有FC芯片5,使得陶瓷基板1的封装空间变大,提高了陶瓷封装的空间利用率且降低了陶瓷封装的外形尺寸。
其中,上空腔3的尺寸为2cm×2cm~4cm×4cm,上空腔3的深度为2~5mm。下空腔4的的尺寸为1cm×1cm~2cm×2cm,所述下空腔4的深度为2~5mm。上空腔3内设有至少一个FC芯片5,所述下空腔4内内设有至少一个FC芯片5。可以在上空腔3内放置一个或者多个尺寸相同或不同的FC芯片5,提高了陶瓷封装的空间利用率。
陶瓷基板1在上空腔3的一面上覆盖有盖板8,所述盖板8与陶瓷基板1固定连接,所述盖板8的面积大于所述上空腔3的面积。盖板8中心相对于上空腔3向外突出,使得盖板8与陶瓷基板1上表面形成空隙,防止盖板8对上空腔3内的FC芯片5造成积压,提升了陶瓷封装结构的稳定性和安全性。陶瓷基板1侧面设有焊接区2,所述盖板8与陶瓷基板1的接触面在焊接区2上。
以上所述实施例仅表达了本发明的某种实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制;应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围;因此,本发明专利的保护范围应以所附权利要求为准。

Claims (9)

1.一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:在陶瓷基板两侧面的芯片贴装位置进行预先挖腔,封装时将FC芯片分别沉到相应的陶瓷腔里并与陶瓷基板连接,将盖板通过合金熔封的工艺焊接在陶瓷基板四周的焊接区内,并在陶瓷基板背面植球,完成封装。
2.根据权利要求1所述的一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:所述封装工艺具体包括如下步骤:
S100、挖腔,在陶瓷基板两侧面的芯片贴装位置进行挖腔;
S200、绝缘,对同一面的腔体之间进行相互隔离;
S300、贴装,将FC芯片分别沉到相应的陶瓷腔里并进行固定;
S400、粘合,使用填充胶填充FC芯片与陶瓷基板之间;
S500、封帽,将盖板通过合金熔封的方式焊接在陶瓷基板顶部的焊接区内;
S600、植球,对陶瓷基板背面植球,完成封装。
3.根据权利要求1所述的一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:所述步骤S100中的挖腔具体为先将各生瓷片通过激光或者机械冲制在相应位置开出槽,再将各层生瓷片叠加在一起进行烧结,该相应位置的槽在叠加一起之后形成了腔体。
4.根据权利要求1所述的一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:所述步骤S200中的相互隔离具体是将腔体之间陶瓷体上打满接地孔。
5.根据权利要求1所述的一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:所述步骤S300中的贴装具体为将FC芯片以表贴的方式贴装到陶瓷基板的腔体中,贴装精度控制在±35um以内。
6.根据权利要求1所述的一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:所述步骤S400具体为使用填充胶填充FC芯片与陶瓷基板之间后,再进行烘烤使得填充胶凝固,所述烘烤的具体过程为将陶瓷基板置于150℃的温度下烘烤30~40分钟,使填充胶完全固化。
7.根据权利要求1所述的一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:所述步骤S400中的粘合具体为对腔体中的FC芯片底部的锡球进行底部填充胶。
8.根据权利要求1所述的一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:所述步骤5600中焊接区的宽度为1.5~2.0mm。
9.根据权利要求3所述的一种基于FC芯片的双面挖腔陶瓷封装工艺,其特征在于:所述挖腔深度为0.2~0.4mm。
CN202010459064.3A 2020-05-27 2020-05-27 一种基于fc芯片的双面挖腔陶瓷封装工艺 Pending CN111599691A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010459064.3A CN111599691A (zh) 2020-05-27 2020-05-27 一种基于fc芯片的双面挖腔陶瓷封装工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010459064.3A CN111599691A (zh) 2020-05-27 2020-05-27 一种基于fc芯片的双面挖腔陶瓷封装工艺

Publications (1)

Publication Number Publication Date
CN111599691A true CN111599691A (zh) 2020-08-28

Family

ID=72192259

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010459064.3A Pending CN111599691A (zh) 2020-05-27 2020-05-27 一种基于fc芯片的双面挖腔陶瓷封装工艺

Country Status (1)

Country Link
CN (1) CN111599691A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112366187A (zh) * 2020-11-19 2021-02-12 航天科工微电子***研究院有限公司 一种毫米波芯片空腔封装结构及封装方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681593A (zh) * 2013-12-02 2014-03-26 江苏省宜兴电子器件总厂 一种无引线陶瓷片式载体封装结构及其制备工艺
CN204289421U (zh) * 2014-12-08 2015-04-22 无锡中微高科电子有限公司 气密性双腔封装结构
CN107248513A (zh) * 2017-06-19 2017-10-13 苏州博海创业微***有限公司 北斗一体化封装电路
CN107301982A (zh) * 2017-05-11 2017-10-27 西安空间无线电技术研究所 基于ltcc的cga一体化封装结构及其实现方法
CN108428672A (zh) * 2018-04-17 2018-08-21 中国电子科技集团公司第二十九研究所 超宽带射频微***的陶瓷双面三维集成架构及封装方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681593A (zh) * 2013-12-02 2014-03-26 江苏省宜兴电子器件总厂 一种无引线陶瓷片式载体封装结构及其制备工艺
CN204289421U (zh) * 2014-12-08 2015-04-22 无锡中微高科电子有限公司 气密性双腔封装结构
CN107301982A (zh) * 2017-05-11 2017-10-27 西安空间无线电技术研究所 基于ltcc的cga一体化封装结构及其实现方法
CN107248513A (zh) * 2017-06-19 2017-10-13 苏州博海创业微***有限公司 北斗一体化封装电路
CN108428672A (zh) * 2018-04-17 2018-08-21 中国电子科技集团公司第二十九研究所 超宽带射频微***的陶瓷双面三维集成架构及封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112366187A (zh) * 2020-11-19 2021-02-12 航天科工微电子***研究院有限公司 一种毫米波芯片空腔封装结构及封装方法

Similar Documents

Publication Publication Date Title
CN103681377B (zh) 带有底部金属基座的半导体器件及其制备方法
CN207338361U (zh) 用于引线框架的设备和***
CN102144290B (zh) 倒装芯片过模封装件
US7425468B2 (en) Method for making flip chip on leadframe package
CA2118785A1 (en) Packaged semiconductor device suitable to be mounted and connected to microstrip line structure board
KR20010060343A (ko) 반도체 장치 및 반도체 장치 제조 방법
CN103000538A (zh) 半导体封装结构的制造方法
US20230317708A1 (en) Multiple Chip Module Trenched Lid and Low Coefficient of Thermal Expansion Stiffener Ring
CN111599691A (zh) 一种基于fc芯片的双面挖腔陶瓷封装工艺
CN106129023A (zh) 双面贴装的扇出封装结构及封装方法
CN105047630B (zh) 芯片后组装有源埋入封装结构及其生产工艺
CN111599689A (zh) 一种基于wb芯片的双面挖腔陶瓷封装工艺
CN105347292A (zh) 可缓解盖板应力的mems封装结构及其封装方法
CN205187841U (zh) 可缓解盖板应力的mems封装结构
CN111599690A (zh) 一种基于wb芯片与fc芯片共存的双面挖腔陶瓷封装工艺
TW201526198A (zh) 具有堆疊元件的封裝模組
CN210575913U (zh) 一种分拣倒装芯片的封盖平衡性填充封装结构
CN203277350U (zh) 多芯片封装体
CN114220785A (zh) 一种具有高可靠度焊点结构的散热倒装封装结构及方法
CN101308804A (zh) 射频模块的封装结构及其制造方法
WO2022041846A1 (zh) Led 支架、灯珠及其制作方法、导电基座、发光单元模组
CN206819986U (zh) 一种增强散热性能的ic封装结构
CN100373615C (zh) 具有散热片的多封装件模组构造
CN211828731U (zh) 一种基于fc芯片的双面挖腔陶瓷封装结构
CN219163401U (zh) 一种带有滤波器的射频***模块封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20200828

RJ01 Rejection of invention patent application after publication