CN111525790A - Charge pump circuit - Google Patents

Charge pump circuit Download PDF

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Publication number
CN111525790A
CN111525790A CN202010219641.1A CN202010219641A CN111525790A CN 111525790 A CN111525790 A CN 111525790A CN 202010219641 A CN202010219641 A CN 202010219641A CN 111525790 A CN111525790 A CN 111525790A
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Prior art keywords
nmos transistor
capacitor
nmos
tube
charge pump
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CN202010219641.1A
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Chinese (zh)
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CN111525790B (en
Inventor
周怡鑫
王科平
王志功
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Southeast University
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Southeast University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a charge pump circuit, which comprises a first NMOS (N-channel metal oxide semiconductor) tube M1A second NMOS transistor M2And the third NMOS transistor M3And the fourth NMOS tube M4The fifth NMOS transistor M5And a sixth NMOS transistor M6And a seventh NMOS transistor M7And the eighth NMOS transistor M8A first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4A fifth capacitor C5A sixth capacitor C6And an output capacitor COUT. The state of the NMOS tube is controlled through clock signals with different phases, so that reverse loss is effectively avoided, and the working efficiency and the current driving capability of the charge pump are improved; the substrate end of the NMOS tube in the charge pump circuit can be uniformly connected to a specific potential, so that the reverse breakdown voltage of the substrate diode is increased, and the maximum output voltage which can be borne by the charge pump is improved.

Description

Charge pump circuit
Technical Field
The invention relates to a charge pump circuit, and belongs to the technical field of circuits and systems.
Background
With the wide application of the non-volatile memory, the working voltage far higher than the power voltage is required for writing and erasing data, and the charge pump circuit can raise the lower power voltage to the higher working voltage. The traditional cross-coupled charge pump circuit has the problem of reverse loss, wherein the reverse loss is the phenomenon of charge leakage caused by the fact that MOS (metal oxide semiconductor) tubes are simultaneously conducted when clock signals change. And the traditional charge pump circuit has the problem that the bearable maximum output voltage is limited by the reverse breakdown voltage of the substrate diode of the MOS tube.
Disclosure of Invention
Aiming at the problems of reverse loss of the traditional cross-coupled charge pump and the problem that the maximum output voltage of a multi-stage charge pump is limited by the reverse breakdown voltage of a substrate diode of an MOS (metal oxide semiconductor) tube, the invention provides a charge pump circuit, which adopts a full NMOS (N-channel metal oxide semiconductor) type charge pump circuit controlled by a multi-phase clock, effectively avoids the generation of reverse loss, and improves the working efficiency and the current driving capability of the charge pump; the substrate end of the NMOS tube in the charge pump circuit can be uniformly connected to a specific potential, so that the reverse breakdown voltage of the substrate diode is increased, and the maximum output voltage which can be borne by the charge pump is improved.
In order to achieve the purpose, the technical scheme of the invention is as follows: a charge pump circuit is characterized by comprising a multi-stage charge pump with at least 1 stage, wherein each stage of charge pump is composed of a capacitor and an NMOS (N-channel metal oxide semiconductor) tube.
As an improvement of the invention, the NMOS tube is a deep N-well type NMOS tube.
As a modification of the invention, the substrate end of the NMOS tube is uniformly connected to a specific potential or connected to the source electrode thereof.
As an improvement of the invention, the circuit comprises a first NMOS tube M1A second NMOS transistor M2And the third NMOS transistor M3And the fourth NMOS tube M4The fifth NMOS transistor M5And a sixth NMOS transistor M6And a seventh NMOS transistor M7And the eighth NMOS transistor M8A first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4A fifth capacitor C5A sixth capacitor C6And an output capacitor COUT(ii) a The first capacitor C1One end of which is connected to the clock signal CLK1The other end is connected with a second NMOS tube M2Drain electrode of (1) and eighth NMOS transistor M8A source electrode of (a); the second capacitor C2Is connected to the second clock signal CLK2The other end is connected with a first NMOS tube M1Drain electrode of (1) and seventh NMOS transistor M7A source electrode of (a); the thirdCapacitor C3Is connected to the third clock signal CLK3The other end is connected with a first NMOS tube M1Grid electrode of and a third NMOS tube M3Drain electrode of (1) and fourth NMOS transistor M4Grid and sixth NMOS transistor M6A gate electrode of (1); the fourth capacitor C4Is connected to the fourth clock signal CLK4The other end is connected with a second NMOS tube M2Grid electrode of and a third NMOS tube M3Grid and fourth NMOS transistor M4Drain electrode of (1) and fifth NMOS transistor M5A gate electrode of (1); the fifth capacitor C5Is connected to the fifth clock signal CLK5The other end is connected with a fifth NMOS tube M5Drain electrode of (1) and eighth NMOS transistor M8A gate electrode of (1); sixth capacitor C6Is connected to the sixth clock signal CLK6The other end is connected with a sixth NMOS tube M6Drain electrode of (1) and seventh NMOS transistor M7A gate electrode of (1); the first NMOS tube M1Source electrode of the first NMOS transistor M2Source electrode of and third NMOS transistor M3Source electrode of and fourth NMOS transistor M4Source electrode of and the fifth NMOS transistor M5Source electrode of (1) and sixth NMOS transistor M6Is connected to the input signal VIN(ii) a The seventh NMOS tube M7Is connected with an eighth NMOS tube M8And output signal VOUT(ii) a The output capacitor COUTOne end of the first NMOS transistor is connected to the ground, and the other end of the first NMOS transistor is connected to the seventh NMOS transistor M7Of the substrate.
Compared with the prior art, the invention has the following advantages: 1) according to the scheme, the charge pump circuit is controlled by adopting different phase clock signals, so that the problem of reverse loss is avoided, and the working efficiency and the current driving capability are improved; 2) according to the scheme, the charge pump circuit is formed by adopting the uniform deep N-well type NMOS tubes, and the substrate ends of the NMOS tubes can be uniformly connected to a specific potential, so that the reverse breakdown voltage of the substrate diode is increased, and the maximum output voltage which can be borne by the charge pump is improved.
Drawings
FIG. 1 is a schematic diagram of a charge pump circuit with a substrate terminal connected to a particular potential;
FIG. 2 is a schematic diagram of a charge pump circuit with a substrate terminal connected to a source;
FIG. 3 is a waveform diagram of input clock signals of different phases according to the present invention;
fig. 4 is a schematic cross-sectional view of a three-dimensional structure of a deep N-well NMOS transistor in the present invention with the substrate terminal connected to a specific potential.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in detail below with reference to the accompanying drawings.
Example (b): in the present invention, the charge pump circuit with substrate terminals connected separately is shown in fig. 1, and comprises a first NMOS transistor M1A second NMOS transistor M2And the third NMOS transistor M3And the fourth NMOS tube M4The fifth NMOS transistor M5And a sixth NMOS transistor M6And a seventh NMOS transistor M7And a sixth NMOS transistor M6A first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4A fifth capacitor C5A sixth capacitor C6And an output capacitor COUT(ii) a Wherein the first capacitor C1Has one end connected to the first clock signal CLK1The other end is connected with a second NMOS tube M2Drain electrode of (1) and eighth NMOS transistor M8A source electrode of (a); the second capacitor C2Is connected to the second clock signal CLK2The other end is connected with a first NMOS tube M1Drain electrode of (1) and seventh NMOS transistor M7A source electrode of (a); the third capacitor C3Is connected to the third clock signal CLK3The other end is connected with a first NMOS tube M1Grid electrode of and a third NMOS tube M3Drain electrode of (1) and fourth NMOS transistor M4Grid and sixth NMOS transistor M6A gate electrode of (1); the fourth capacitor C4Is connected to the fourth clock signal CLK4The other end is connected with a second NMOS tube M2Grid electrode of and a third NMOS tube M3Grid and fourth NMOS transistor M4Drain electrode of (1) and fifth NMOS transistor M5A gate electrode of (1); the fifth capacitor C5Is connected to the fifth clock signal CLK5The other end is connected with a fifth NMOS tube M5Drain electrode of (1) and eighth NMOS transistor M8A gate electrode of (1); sixth capacitor C6Is connected to the sixth clock signal CLK6The other end is connected with a sixth NMOS tube M6Drain electrode of (1) and seventh NMOS transistor M7A gate electrode of (1); the first NMOS tube M1Source electrode of the first NMOS transistor M2Source electrode of and third NMOS transistor M3Source electrode of and fourth NMOS transistor M4Is connected to the input signal VIN(ii) a The seventh NMOS tube M7Is connected with an eighth NMOS tube M8And output signal VOUT(ii) a The output capacitor COUTOne end of the first NMOS transistor is connected to the ground, and the other end of the first NMOS transistor is connected to the seventh NMOS transistor M7A drain electrode of (1); the first NMOS tube M1Substrate end, second NMOS tube M2Substrate end, third NMOS tube M3Substrate end, fourth NMOS tube M4Substrate end, fifth NMOS tube M5Substrate end, sixth NMOS tube M6Substrate end, seventh NMOS transistor M7Substrate end and eighth NMOS transistor M8Substrate terminal of (1) is connected with input signal V1。
In the present invention, the charge pump circuit with the substrate end connected to the source is shown in fig. 2, and includes a first NMOS transistor M1A second NMOS transistor M2And the third NMOS transistor M3And the fourth NMOS tube M4The fifth NMOS transistor M5And a sixth NMOS transistor M6And a seventh NMOS transistor M7And a sixth NMOS transistor M6A first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4A fifth capacitor C5A sixth capacitor C6And an output capacitor COUT(ii) a Wherein the first capacitor C1Has one end connected to the first clock signal CLK1The other end is connected with a second NMOS tube M2Drain electrode of (1) and eighth NMOS transistor M8The source and the substrate end; the second capacitor C2Is connected to the second clock signal CLK2The other end is connected with a first NMOS tube M1Drain electrode of (1) and seventh NMOS transistor M7The source and the substrate end; the third capacitor C3Is connected to the third clock signal CLK3The other end is connected with a first NMOS tube M1Grid electrode of and a third NMOS tube M3Drain electrode of (1), fourth NMOS tube M4Grid and sixth NMOS transistor M6A gate electrode of (1); the fourth capacitor C4Is connected to the fourth clock signal CLK4The other end is connected with a second NMOS tube M2Grid electrode of and a third NMOS tube M3Grid electrode of and a fourth NMOS tube M4Drain electrode of (1) and fifth NMOS transistor M5A gate electrode of (1); the fifth capacitor C5Is connected to the fifth clock signal CLK5The other end is connected with a fifth NMOS tube M5Drain electrode of (1) and eighth NMOS transistor M8A gate electrode of (1); sixth capacitor C6Is connected to the sixth clock signal CLK6The other end is connected with a sixth NMOS tube M6Drain electrode of (1) and seventh NMOS transistor M7A gate electrode of (1); the first NMOS tube M1Source and substrate end, second NMOS transistor M2Source and substrate end, third NMOS transistor M3Source and substrate end, fourth NMOS transistor M4Source and substrate end, fifth NMOS transistor M5Source and substrate end and sixth NMOS transistor M6Is connected with the substrate end to input signal VIN(ii) a The seventh NMOS tube M7Is connected with an eighth NMOS tube M8And output signal VOUT(ii) a The output capacitor COUTOne end of the first NMOS transistor is connected to the ground, and the other end of the first NMOS transistor is connected to the seventh NMOS transistor M7Of the substrate.
FIG. 3 shows the input clock signals with different phases in the present invention, wherein the first clock signal CLK1A second clock signal CLK2A second clock signal CLK3And a fourth clock signal CLK4Is a power supply voltage VDDThe low level potential is ground; the fifth clock signal CLK5And a sixth clock signal CLK6Is 2 times the supply voltage (i.e. 2V)DD) The low level is the ground; the first clock signal CLK1And a second clock signal CLK2At the same time, the time is tcThe third clock signal CLK3And a fourth clock signal CLK4At the same time, the time is tnop1The fifth clock signal CLK5And a sixth clock signal CLK6At the same time of low levelTime tnop2And t isnop2>tnop1>tc. At a time period tcAnd in addition, MOS (metal oxide semiconductor) tubes in the multi-phase charge pump circuit are all in a cut-off state, so that the reverse loss of the charge pump is effectively avoided.
FIG. 4 is a cross-sectional view showing a three-dimensional structure of a deep N-well type NMOS transistor in which a substrate terminal is connected to a specific potential according to the present invention, wherein a diode D1A diode formed by the substrate end B of the NMOS tube and the P-type substrate, and a diode D2And a diode formed by the substrate end B of the bit NMOS tube and the source electrode S of the bit NMOS tube. The connection mode enables the breakdown voltage of the substrate diode of the MOS tube to be changed into a diode D1And a diode D2Thereby increasing the maximum output voltage that the charge pump can withstand.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (4)

1. A charge pump circuit is characterized by comprising a multi-stage charge pump with at least 1 stage, wherein each stage of charge pump is composed of a capacitor and an NMOS (N-channel metal oxide semiconductor) tube.
2. The charge pump circuit of claim 1, wherein: the NMOS tube is a deep N-well type NMOS tube.
3. The charge pump circuit of claim 1, wherein: the substrate ends of the NMOS tubes are uniformly connected to a specific potential or connected to the sources of the NMOS tubes.
4. The charge pump circuit of claim 1, wherein: the circuit comprises a first NMOS transistor M1A second NMOS transistor M2And the third NMOS transistor M3And the fourth NMOS tube M4The fifth NMOS transistor M5And a sixth NMOS transistor M6And a seventh NMOS transistor M7And the eighth NMOS transistor M8A first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4、
Fifth capacitor C5A sixth capacitor C6And an output capacitor COUT(ii) a The first capacitor C1One end of which is connected to the clock signal CLK1The other end is connected with a second NMOS tube M2Drain electrode of (1) and eighth NMOS transistor M8A source electrode of (a); the second capacitor C2Is connected to the second clock signal CLK2The other end is connected with a first NMOS tube M1Drain electrode of (1) and seventh NMOS transistor M7A source electrode of (a);
the third capacitor C3Is connected to the third clock signal CLK3The other end is connected with a first NMOS tube M1Grid electrode of and a third NMOS tube M3Drain electrode of (1), fourth NMOS tube M4Grid and sixth NMOS transistor M6A gate electrode of (1); the fourth capacitor C4Is connected to the fourth clock signal CLK4The other end is connected with a second NMOS tube M2Grid electrode of and a third NMOS tube M3Grid electrode of and a fourth NMOS tube M4Drain electrode of (1) and fifth NMOS transistor M5A gate electrode of (1); the fifth capacitor C5Is connected to the fifth clock signal CLK5The other end is connected with a fifth NMOS tube M5Drain electrode of (1) and eighth NMOS transistor M8A gate electrode of (1);
sixth capacitor C6Is connected to the sixth clock signal CLK6The other end is connected with a sixth NMOS tube M6Drain electrode of (1) and seventh NMOS transistor M7A gate electrode of (1); the first NMOS tube M1Source electrode of the first NMOS transistor M2Source electrode of and third NMOS transistor M3Source electrode of and fourth NMOS transistor M4Source electrode of and the fifth NMOS transistor M5Source electrode of (1) and sixth NMOS transistor M6Is connected to the input signal VIN(ii) a The seventh NMOS tube M7Is connected with an eighth NMOS tube M8And output signal VOUT；
The output capacitor COUTOne end of the first NMOS transistor is connected to the ground, and the other end of the first NMOS transistor is connected to the seventh NMOS transistor M7Of the substrate.
CN202010219641.1A 2020-03-25 2020-03-25 Charge pump circuit Active CN111525790B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114157140A (en) * 2021-11-30 2022-03-08 上海华虹宏力半导体制造有限公司 Charge pump circuit
CN115987092A (en) * 2023-03-22 2023-04-18 上海海栎创科技股份有限公司 Cross-coupled charge pump unit and structure
WO2023124637A1 (en) * 2021-12-28 2023-07-06 深圳飞骧科技股份有限公司 Charge pump circuit with controllable output voltage, and radio frequency chip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101867290A (en) * 2010-06-17 2010-10-20 清华大学 Charge pump circuit with low power consumption
CN103532375A (en) * 2013-09-22 2014-01-22 江苏芯创意电子科技有限公司 Boosting charge pump
CN105720813A (en) * 2016-04-22 2016-06-29 中国科学院微电子研究所 Charge pump circuit
CN207442695U (en) * 2017-11-20 2018-06-01 广东工业大学 A kind of charge pump sequential control circuit and charge pump circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101867290A (en) * 2010-06-17 2010-10-20 清华大学 Charge pump circuit with low power consumption
CN103532375A (en) * 2013-09-22 2014-01-22 江苏芯创意电子科技有限公司 Boosting charge pump
CN105720813A (en) * 2016-04-22 2016-06-29 中国科学院微电子研究所 Charge pump circuit
CN207442695U (en) * 2017-11-20 2018-06-01 广东工业大学 A kind of charge pump sequential control circuit and charge pump circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114157140A (en) * 2021-11-30 2022-03-08 上海华虹宏力半导体制造有限公司 Charge pump circuit
WO2023124637A1 (en) * 2021-12-28 2023-07-06 深圳飞骧科技股份有限公司 Charge pump circuit with controllable output voltage, and radio frequency chip
CN115987092A (en) * 2023-03-22 2023-04-18 上海海栎创科技股份有限公司 Cross-coupled charge pump unit and structure
CN115987092B (en) * 2023-03-22 2023-05-23 上海海栎创科技股份有限公司 Cross-coupled charge pump unit and structure

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