CN115987092A - Cross-coupled charge pump unit and structure - Google Patents

Abstract

The invention provides a cross-coupled charge pump unit and a structure. The cross-coupled charge pump cell comprises: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a first branch circuit and a second branch circuit. According to the cross-coupling charge pump unit, the first NMOS tube and the second NMOS tube can be kept in good conduction, the conduction resistance of the first NMOS tube and the second NMOS tube is reduced, the power consumption is reduced, the voltage loss is reduced, and the working efficiency of the cross-coupling charge pump unit is improved.

Description

Cross-coupled charge pump unit and structure

Technical Field

The invention relates to the field of power management of analog integrated circuits, in particular to a cross-coupled charge pump unit and a structure thereof.

Background

Charge pumps are an important component of the power management field of integrated circuits and are commonly used in circuits to produce a dc output that is higher than the supply voltage. The circuit is widely applied to circuits such as a nonvolatile memory, an LCD (liquid crystal display) driver and a touch detector, and can help to improve the performance of some circuits.

The charge pump is divided into Dickson charge pump topology, ladder topology, fibonacci topology, capacitance series-parallel topology, cross-coupling topology and other structures according to different topological structures. With the continuous development of integrated circuit technology, the charge pump with cross-coupled structure can compensate the consumption disadvantage of threshold voltage, and can provide automatic reverse bias to solve the problem of charge transfer in only half a cycle, and the charge pump shows higher efficiency and smaller ripple, and is often used in practical application.

However, the conventional cross charge pump with a cross coupling structure generally has the problems of large on-resistance, large power consumption, low working efficiency and the like.

Disclosure of Invention

The invention aims to provide a cross-coupled charge pump unit and a structure thereof, which are used for solving the problems of large on-resistance, large power consumption, low working efficiency and the like of the conventional cross-coupled charge pump.

To solve the problems in the prior art, in a first aspect, the present invention provides a cross-coupled charge pump unit, including: the first NMOS tube, the second NMOS tube, the first branch and the second branch; wherein the content of the first and second substances,

the first branch comprises a first end, a second end, a third end, a fourth end and a fifth end; the first end of the first branch circuit is connected with the grid electrode of the first NMOS tube, the second end of the first branch circuit is connected with input voltage, and the fifth end of the first branch circuit is connected with a complementary clock signal; a diode formed by splicing first PMOS tubes is connected between the third end of the first branch and the fourth end of the first branch, and the fourth end of the first branch is connected to an output end;

the second branch comprises a first end, a second end, a third end, a fourth end and a fifth end; the first end of the second branch circuit is connected with the grid electrode of the second NMOS tube and the third end of the first branch circuit, the second end of the second branch circuit is connected with the input voltage, the third end of the second branch circuit is connected with the first end of the first branch circuit, and the fifth end of the second branch circuit is connected with a clock signal; and a diode formed by splicing second PMOS tubes is connected between the third end of the second branch and the fourth end of the second branch, and the fourth end of the second branch is connected to the output end.

Optionally, the cross-coupled charge pump unit further includes a third PMOS transistor, a fourth PMOS transistor, a first capacitor, and a second capacitor; the drain electrode of the first NMOS tube is connected with the input voltage, and the source electrode of the first NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the upper polar plate of the first capacitor; the drain electrode of the second NMOS tube is connected with the input voltage, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube and the upper polar plate of the second capacitor; the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the fourth end of the first branch circuit and the fourth end of the second branch circuit are connected and then are used as the output end of the cross-coupled charge pump unit; the lower polar plate of the first capacitor is connected with the complementary clock signal; and the lower polar plate of the second capacitor is connected with the clock signal.

Optionally, the first branch comprises: the third NMOS tube, the first PMOS tube and a third capacitor; wherein the content of the first and second substances,

the lower pole plate of the third capacitor is connected with the complementary clock signal, and the upper pole plate of the third capacitor is connected with the third end of the first branch circuit, the grid electrode of the fourth NMOS tube and the grid electrode of the second NMOS tube;

the drain electrode of the third NMOS tube is connected with the input voltage, and the source electrode of the third NMOS tube is connected with the first end of the second branch and the drain electrode of the first PMOS tube;

the grid electrode of the first PMOS tube is in short circuit with the source electrode of the first PMOS tube to form a diode and serve as the fourth end of the first branch circuit.

Optionally, the second branch comprises: the fourth NMOS transistor, the second PMOS transistor and a fourth capacitor; wherein the content of the first and second substances,

the lower pole plate of the fourth capacitor is connected with the clock signal, and the upper pole plate of the fourth capacitor is connected with the third end of the second branch circuit, the grid electrode of the third NMOS tube and the grid electrode of the first NMOS tube;

the drain electrode of the fourth NMOS tube is connected with the input voltage, and the source electrode of the fourth NMOS tube is connected with the first end of the first branch circuit and the drain electrode of the second PMOS tube;

and the grid electrode of the second PMOS tube is in short circuit with the source electrode of the second PMOS tube to form a diode and serve as the fourth end of the second branch circuit.

Optionally, the body region of the first NMOS transistor, the body region of the second NMOS transistor, the body region of the third NMOS transistor, and the body region of the fourth NMOS transistor are all connected to a ground voltage.

In a second aspect, the present invention also provides a cross-coupled charge pump structure, comprising: an N-stage cross-coupled charge pump unit; the cross-coupled charge pump cell is the cross-coupled charge pump cell described in the first aspect; the input end of the 1 st-stage cross-coupled charge pump unit is connected with the voltage of the input end, and the input end of the j-th-stage cross-coupled charge pump unit is connected with the output end of the j-1 st-stage cross-coupled charge pump unit; wherein N is an integer of 2 or more, and j is an integer of 1 or more and N or less.

Optionally, the cross-coupled charge pump structure further comprises a clock generation circuit, the clock generation circuit comprising:

n stages of delay units connected in series in sequence; wherein, the output end of the ith delay unit is connected with at least the fifth end of the second branch in the ith stage of the cross-coupled charge pump unit; i is an integer less than or equal to N.

Optionally, the delay unit of stage 1 includes a buffer, and an input end of the buffer is connected to a clock signal;

the j-th stage of the delay unit comprises a buffer and an adjustable capacitor, an upper polar plate of the adjustable capacitor in the j-th stage of the delay unit is connected with an output end of the buffer in the j-th delay unit, and a lower polar plate of each adjustable capacitor is grounded; the buffers are connected in series in sequence.

As described above, the cross-coupled charge pump unit and the structure of the present invention have the following advantages:

according to the cross-coupling charge pump unit, the first branch and the second branch are additionally arranged, the diode formed by splicing the first PMOS tubes is connected between the third end of the first branch and the fourth end of the first branch, the diode formed by splicing the second PMOS tubes is connected between the third end of the second branch and the fourth end of the second branch, and therefore when the cross-coupling charge pump unit works in a load mode, grid voltages of the first NMOS tube and the second NMOS tube are not pulled to be lower than the output end of the cross-coupling charge pump unit, the grid voltages of the first NMOS tube and the second NMOS tube are higher than the voltage of the output end of the cross-coupling charge pump unit by the conducting voltage of one diode, the first NMOS tube and the second NMOS tube are enabled to be well conducted, conducting resistances of the first NMOS tube and the second NMOS tube are reduced, power consumption is reduced, voltage loss is reduced, and working efficiency of the cross-coupling charge pump unit is improved.

In the cross-coupled charge pump structure, each level of cross-coupled charge pump unit is additionally provided with a first branch circuit and a second branch circuit, a diode formed by splicing first PMOS tubes is connected between a third end of the first branch circuit and a fourth end of the first branch circuit, a diode formed by splicing second PMOS tubes is connected between a third end of the second branch circuit and a fourth end of the second branch circuit, so that the grid voltages of the first NMOS and the second NMOS tubes in each level of cross-coupled charge pump unit can be ensured not to be pulled to be lower than the output end of the cross-coupled charge pump unit when the cross-coupled charge pump unit works under a load, the grid voltages of the first NMOS and the second NMOS tubes in each level of cross-coupled charge pump unit are at least one diode higher than the voltage of the output end of each level of the cross-coupled charge pump unit, the first NMOS tube and the second NMOS tube are kept well conducted, the conduction resistance of the first NMOS tube and the second NMOS tube is reduced, the power consumption is reduced, and the voltage loss is reduced; meanwhile, the control voltage of the first NMOS tube and the control voltage of the second NMOS tube in each stage of cross-coupled charge pump unit are connected to the output end of each stage, the first branch and the second branch also provide driving capability for the cross-coupled charge pump unit, power consumption is not wasted, the working efficiency of each cross-coupled charge pump unit is integrally improved, and the working efficiency of the cross-coupled charge pump structure is further improved.

Drawings

Fig. 1 is a circuit diagram of a cross-coupled charge pump cell.

Fig. 2 is a circuit diagram of a cross-coupled charge pump unit according to a first embodiment of the present invention.

Fig. 3 is a circuit diagram of a cross-coupled charge pump structure according to a second embodiment of the present invention.

Fig. 4 is a timing diagram of a cross-coupled charge pump structure according to a second embodiment of the invention.

Fig. 5 is a circuit diagram of a clock generation circuit in a cross-coupled charge pump structure according to a second embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.

It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced devices or components must be constructed and operated in a particular orientation and thus are not to be considered limiting.

Charge pumps are an important component of the power management field of integrated circuits and are commonly used in circuits to produce a dc output above the supply voltage. The circuit is widely applied to circuits such as a nonvolatile memory, an LCD driver and a touch detection circuit, and can help to improve the performance of certain circuits.

The charge pump is divided into Dickson charge pump topology, ladder topology, fibonacci topology, capacitance series-parallel topology, cross-coupling topology and other structures according to different topological structures. With the continuous development of integrated circuit technology, the charge pump with cross-coupled structure can compensate the consumption disadvantage of threshold voltage, and can provide automatic reverse bias to solve the problem of charge transfer in only half a cycle, and the charge pump shows higher efficiency and smaller ripple, and is often used in practical application.

The cross-coupled charge pump cell is shown in fig. 1, which is a circuit diagram of a cross-coupled charge pump cell. The cross-coupled charge pump unit comprises two NMOS tubes (a first NMOS tube N1 'and a second NMOS tube N2'), two PMOS tubes (a first PMOS tube P 'and a second PMOS tube P2') and two capacitors (a first capacitor C1 'and a second capacitor C2'), wherein the first capacitor C1 'and the second capacitor C2' are respectively connected with two cross complementary clock signals (a clock signal CLK and a complementary clock signal CLKB). In the cross-coupled charge pump circuit, a phenomenon of charge backflow exists due to structural limitation; in addition, the on-resistance of the transmission tube is relatively high due to the substrate bias effect of the NMOS tube along with the rise of the voltage, particularly in a single-well process or when a PWELL layer is not needed to be used for saving cost; these all affect the efficiency of the charge pump unit and increase the power consumption of the circuit.

Example one

Referring to fig. 2, the present invention provides a cross-coupled charge pump unit, which includes:

the device comprises a first NMOS tube N1, a second NMOS tube N2, a first branch and a second branch; wherein the content of the first and second substances,

the first branch comprises a first end, a second end, a third end, a fourth end and a fifth end; a first end net11 of the first branch is connected to the gate of the first NMOS transistor N1, a second end net12 of the first branch is connected to the input voltage Vin, and a fifth end net25 of the first branch is connected to the complementary clock signal CLKB; a diode formed by splicing first PMOS transistors P1 is connected between the third end net13 (nb) of the first branch and the fourth end net14 of the first branch, and the fourth end net14 of the first branch is an output end;

the second branch comprises a first end, a second end, a third end, a fourth end and a fifth end; the first end net21 of the second branch is connected to the gate of the second NMOS transistor N2 and the third end net13 of the first branch, the second end net22 of the second branch is connected to the input voltage Vin, the third end net23 (na) of the second branch is connected to the first end net11 of the first branch, and the fifth end net15 of the second branch is connected to the clock signal CLK; a diode formed by splicing second PMOS tubes P2 is connected between the third end net23 of the second branch and the fourth end net24 of the second branch, and the fourth end net24 of the second branch is an output end;

in an example, the cross-coupled charge unit further includes a third PMOS transistor P3, a fourth PMOS transistor P4, a first capacitor C1, and a second capacitor C2; the drain electrode of the first NMOS tube N1 is connected with the input voltage, and the source electrode of the first NMOS tube N1 is connected with the drain electrode of the third PMOS tube P3, the grid electrode of the fourth PMOS tube P4 and the upper polar plate of the first capacitor C1; the drain electrode of the second NMOS transistor N2 is connected to the input voltage, and the source electrode of the second NMOS transistor N2 is connected to the drain electrode of the fourth PMOS transistor P4, the gate electrode of the third PMOS transistor P3, and the upper plate of the second capacitor C2; the source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the fourth end of the first branch, and the fourth end of the second branch are connected together and then used as the output end of the cross-coupled charge pump unit (for outputting the output voltage Vout in fig. 2); the lower plate of the first capacitor C1 is connected with the complementary clock signal; and the lower plate of the second capacitor C2 is connected with the clock signal.

In one example, continuing with reference to fig. 2, the first leg includes: a third NMOS transistor N3, the first PMOS transistor P1 and a third capacitor C4; wherein the content of the first and second substances,

a lower pole plate of the third capacitor C4 is connected with the complementary clock signal CLKB, and an upper pole plate of the third capacitor C4 is connected with a third end of the first branch, a gate of a fourth NMOS transistor N4, and a gate of the second NMOS transistor N2;

the drain electrode of the third NMOS transistor N3 is connected to the input voltage Vin, and the source electrode of the third NMOS transistor N3 is connected to the first end of the second branch and the drain electrode of the first PMOS transistor P1;

the grid electrode of the first PMOS pipe P1 is in short circuit with the source electrode of the first PMOS pipe P1 to form a diode and serve as a fourth end of the first branch circuit.

Specifically, the source of the third NMOS transistor N3 is the third end of the first branch, and the lower plate of the third capacitor C4 is the fifth end of the first branch.

In one example, continuing with fig. 2, the second branch includes: the fourth NMOS transistor N4, the second PMOS transistor P2 and a fourth capacitor C3; wherein, the first and the second end of the pipe are connected with each other,

a lower pole plate of the fourth capacitor C3 is connected with the clock signal CLK, and an upper pole plate of the fourth capacitor C3 is connected with a third end of the second branch circuit, a grid electrode of the third NMOS tube N3 and a grid electrode of the first NMOS tube N1;

the drain electrode of the fourth NMOS transistor N4 is connected to the input voltage Vin, and the source electrode of the fourth NMOS transistor N4 is connected to the first end of the first branch and the drain electrode of the second PMOS transistor P2;

the grid electrode of the second PMOS pipe P2 is in short circuit with the source electrode of the second PMOS pipe P2 to form a diode and serve as the fourth end of the second branch circuit.

Specifically, the source of the fourth NMOS transistor N4 is the third end of the second branch, and the lower plate of the fourth capacitor C3 is the fifth end of the second branch.

It should be noted that, as shown in fig. 2, the upper plate of the first capacitor C1 is connected to the source of the first NMOS transistor N1, the drain of the third PMOS transistor P3, and the gate of the fourth PMOS transistor P4 through a node nd; the second capacitor C2 is connected with the source electrode of the second NMOS transistor N2, the drain electrode of the fourth PMOS transistor P4, and the gate electrode of the third PMOS transistor P3 via a node nc; the na node in fig. 2 is the first end of the first branch and the third end of the second branch, and the nb node in fig. 2 is the third end of the first branch and the first end of the second branch.

For example, referring to fig. 2, the body region of the first NMOS transistor N1, the body region of the second NMOS transistor N2, the body region of the third NMOS transistor N3, and the body region of the fourth NMOS transistor N4 are all connected to a ground voltage VSS.

In fig. 2, all the NMOS transistors (the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4) do not have a PWELL (P-type well region) or do not use a PWELL layer, and the substrates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are all connected to a ground voltage VSS; compared to a conventional cross-coupled charge pump cell: the gate voltage of the second NMOS transistor N2 is no longer provided by the node nd, but a first branch formed by the third NMOS transistor N3, the first PMOS transistor P1, and the third capacitor C4 is introduced, so that the gate voltage of the second NMOS transistor N2 is generated by the first branch, and is connected to the output of the cross-coupled charge pump unit through the first PMOS transistor P1 formed by splicing diodes, that is, a relatively high voltage is provided for nb, so that the on-resistance of the second NMOS transistor N2 does not increase greatly with the increase of the voltage of the cross-coupled charge pump unit, the voltage of nb is not pulled low by a load through the diode connection formed by the first PMOS transistor P1, and meanwhile, the first PMOS transistor P1 formed by splicing diodes can also provide a current to the output; similarly, the gate voltage of the first NMOS transistor N1 is no longer provided by the node nc, but a second branch formed by the fourth NMOS transistor N4, the second PMOS transistor P2, and the fourth capacitor C3 is introduced, so that the gate voltage of the first NMOS transistor N1 is generated by the second branch, and is connected to the output of the cross-coupled charge pump unit through the second PMOS transistor P2 formed by splicing diodes, that is, a relatively high voltage is provided for na, so that the on-resistance of the first NMOS transistor N1 does not increase greatly with the increase of the voltage of the cross-coupled charge pump unit, the voltage of na is not pulled low by a load through the diode connection formed by splicing the second PMOS transistor P2, and meanwhile, the second PMOS transistor P2 formed by splicing diodes can also provide a current to the output.

Example two

Referring to fig. 3, the present embodiment further provides a cross-coupled charge pump structure, where the cross-coupled charge pump structure includes: an N-stage cross-coupled charge pump unit; the cross-coupled charge pump unit is the cross-coupled charge pump unit as described in the first embodiment; the input end of the 1 st-stage cross-coupled charge pump unit is connected with an input end voltage Vin, and the input end of the jth-stage cross-coupled charge pump unit is connected with the output end of the j-1 st-stage cross-coupled charge pump unit; wherein N is an integer of 2 or more, and j is an integer of 1 or more and N or less.

Specifically, the cross-coupled charge pump structure in fig. 3 includes 3 stages of cross-coupled charge pump units as an example, a lower plate of the third capacitor C4 in the 1 st stage of the cross-coupled charge pump unit is connected to a first complementary clock signal CLK1B, a lower plate of the third capacitor C4 in the 2 nd stage of the cross-coupled charge pump unit is connected to a second complementary clock signal CLK2B, and a lower plate of the third capacitor C4 in the 3 rd stage of the cross-coupled charge pump unit is connected to a third complementary clock signal CLK 3B.

A lower pole plate of the fourth capacitor C3 in the i-th stage of the cross-coupled charge pump unit is connected with the i-th clock signal CLKi, and an upper pole plate of the fourth capacitor C3 is connected with a third end of the second branch, a gate of the third NMOS transistor N3, and a gate of the first NMOS transistor N1;

the drain electrode of the fourth NMOS tube N4 is connected with the input voltage, and the source electrode of the fourth NMOS tube N4 is connected with the first end of the first branch and the drain electrode of the second PMOS tube P2;

the grid electrode of the second PMOS pipe P2 is in short circuit with the source electrode of the second PMOS pipe P2 to form a diode and serve as the fourth end of the second branch circuit.

Specifically, the cross-coupled charge pump structure in fig. 3 includes 3 stages of cross-coupled charge pump units as an example, a lower plate of the fourth capacitor C3 in the 1 st stage of the cross-coupled charge pump unit is connected to a first clock signal CLK1, a lower plate of the fourth capacitor C3 in the 2 nd stage of the cross-coupled charge pump unit is connected to a second clock signal CLK2, and a lower plate of the fourth capacitor C3 in the 3 rd stage of the cross-coupled charge pump unit is connected to a third clock signal CLK3.

As an example, referring to fig. 5, the cross-coupled charge pump structure further includes a clock generation circuit, the clock generation circuit including:

n stages of delay units connected in series in sequence; the output end of the ith delay unit is connected with at least the fifth end of the second branch in the ith stage of the cross-coupled charge pump unit; i is an integer less than or equal to N.

As an example, the output terminal of the ith delay unit is further connected to a plate, far from the node nc, of the second capacitor C2 in the ith stage of the cross-coupled charge pump unit, and specifically, the output terminal of the ith delay unit is further connected to a lower plate of the second capacitor C2 in the ith stage of the cross-coupled charge pump unit.

As an example, the delay unit of stage 1 includes a buffer D1, and an input terminal of the buffer D1 is connected to a clock signal;

the j stage of the delay unit comprises a buffer Dj and an adjustable capacitor Cj-1, the upper polar plate of the adjustable capacitor in the j stage of the delay unit is connected with the output end of the buffer Dj in the j stage of the delay unit, and the lower polar plate of each adjustable capacitor is grounded; the buffers are connected in series in sequence.

Specifically, in fig. 5, for example, the clock generation circuit includes 3 stages of delay units connected in series in sequence, the 1 st stage of delay unit includes a buffer D1, an input end of the buffer D1 is connected to a clock signal CLK, and an output end of the buffer D1 is connected to a fifth end of a second branch in the 1 st stage of cross-coupled charge pump unit and a lower plate of a second capacitor C2 in the 1 st stage of cross-coupled charge pump unit, and is configured to generate a first clock signal CLK1; the 2 nd-stage delay unit comprises a buffer D2 and an adjustable capacitor CP1, an input end of the buffer D2 is connected with an output end of the buffer D1, an output end of the buffer D2 is connected with a fifth end of a second branch in the 2 nd-stage cross-coupled charge pump unit and a lower plate of a second capacitor C2 in the 2 nd-stage cross-coupled charge pump unit, an upper plate of the adjustable capacitor CP1 is connected with an output end of the buffer D2, and the 2 nd-stage delay unit is configured to generate a second clock signal CLK2; the 3 rd stage delay unit comprises a buffer D3 and an adjustable capacitor CP2, an input end of the buffer D3 is connected with an output end of the buffer D2, an output end of the buffer D3 is connected with a fifth end of a second branch in the 3 rd stage cross-coupled charge pump unit and a lower electrode plate of a second capacitor C2 in the 3 rd stage cross-coupled charge pump unit, an upper electrode plate of the adjustable capacitor CP2 is connected with an output end of the buffer D3, and the 3 rd stage delay unit is used for generating a third clock signal CLK3.

When no PWELL layer is used or not used in the process, the substrate end of the NMOS tube is connected to the ground potential VSS, so that the threshold value of the NMOS tube is increased due to the substrate bias effect, particularly, the threshold value is increased more obviously along with the increase of the stage number of the cross-coupled charge pump unit, and the on-resistance of the NMOS tube is increased according to the on-resistance characteristic of the MOS tube, so that the output voltage is reduced, and the efficiency of the cross-coupled charge pump structure is reduced. In this respect, the present invention introduces the first branch to provide the gate voltage to the first NMOS transistor N1 of the PUMP based on the conventional cross-coupled charge PUMP unit, introduces the second branch to provide the gate voltage to the second NMOS transistor N2 of the PUMP, and simultaneously, this control voltage is connected to the output terminal of each stage of the cross-coupled charge PUMP unit through the diode formed by the first PMOS transistor P1 and the diode formed by the second PMOS transistor P2. The improvement can ensure that when the cross-coupled charge pump unit works in a load, the voltage of the first NMOS tube N1 and the second NMOS tube N2 is not lower than that of the output end, and is at least one diode breakover voltage higher than the output voltage of each stage, so that the first NMOS tube N1 and the second NMOS tube N2 are kept well conducted, the breakover resistance of the first NMOS tube N1 and the second NMOS tube N2 is relatively reduced, the power consumption is reduced, and the voltage loss is reduced; meanwhile, the control voltage of the grid electrode of the first NMOS pipe N1 is connected to the output end of each stage of cross-coupled charge pump unit through a diode spliced by a first PMOS pipe P1, the control voltage of the grid electrode of the second NMOS pipe N2 is connected to the output end of each stage of cross-coupled charge pump unit through a diode spliced by a second PMOS pipe P2, and the newly introduced first branch and the second branch also provide driving capability for the cross-coupled charge pump unit, so that no power consumption is wasted; thereby improving the efficiency of the cross-coupled charge pump cell as a whole.

The reason why the reverse current of the cross-coupled charge pump unit reduces the efficiency of the cross-coupled charge pump unit is that the clock driving signal of the cross-coupled charge pump unit generally drives the pump capacitor by two inverted signals, and if the pair of inverted signals CLK and CLKB are generated by using the inverter, because the inverter has a certain delay, the two driving signals are simultaneously high, so that the charges stored in the node of the pump capacitor reversely flow to discharge the charges. At present, in order to reduce the influence of the reverse current, a non-overlapping clock is usually used, and the method can inhibit simultaneous channels of the NMOS in the charge pump unit, prevent the reverse current from flowing from the PMOS to the NMOS, reduce the reverse current to a certain extent, and improve the efficiency of the charge pump unit. The non-overlapping clocks are used as driving signals of the pump capacitors, the reverse current of the interior of each stage of charge pump unit can be restrained, but in the multi-stage cascaded charge pump structure, the charge which reversely flows from the next stage to the previous stage cannot be prevented. The reason is that the non-overlap clock controls that the NMOS transistors are not turned on at the same time, but the PMOS transistors are turned on at the same time, so that a reverse current from the NMOS transistor of the next stage to the PMOS transistor of the previous stage is generated, thereby affecting the efficiency of the charge pump unit. In the cross-coupled charge pump structure, the delay unit is added in the drive time of different stages of the cross-coupled charge pump unit, the drive clock of the next stage is delayed relative to the clock of the previous stage, the PMOS (P-channel metal oxide semiconductor) tube of the previous stage is ensured not to be simultaneously conducted when the next stage is conducted, and the delay unit can be modified to meet various PVT changes if needed.

The cross-coupled charge pump structure of the present invention is illustrated by fig. 4 and 5, and the circuit for implementing the timing relationship and the timing relationship of the clock driving signals of different stages of the cross-coupled charge pump unit: because the efficiency of the cross-coupled charge pump unit is reduced due to the reverse current of the cross-coupled charge pump unit, in the prior art, a non-overlapping clock is generally used in each stage of the cross-coupled charge pump unit to prevent the reverse flow of charges, and for the condition that a technology for preventing the current reversal is not adopted between the previous stage and the next stage of the multi-stage cascaded cross-coupled charge pump unit, the invention provides a simple solution. The method can delay the clock signal of the next stage relative to the clock signal of the previous stage, for example, CLK2 is delayed relative to CLK1 in fig. 3, and the delay can be adjusted by trimming if necessary, so that only one of the third PMOS transistor P3 and the fourth PMOS transistor P4 of the previous stage is turned on and the other is turned off when the first NMOS transistor N1 and the second NMOS transistor N2 of the next stage are turned on, thereby effectively preventing reverse charge circulation between the stages of the cross-coupled charge pump structure, and improving the efficiency of the cross-coupled charge pump structure.

(1) The invention can be used for the process without or without PWELL layer, thereby realizing the purpose of reducing the cost;

the substrate of the NMOS (namely the first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3 and the fourth NMOS tube N4) of the invention does not need PWELL and is directly connected to the PSUB, thereby reducing the mask layer number used in chip production and lowering the production cost.

(2) The invention can effectively improve the efficiency of the cross-coupled charge pump unit;

according to the scheme provided by the invention, on one hand, through reasonable topological connection, the grid control voltage of the first NMOS tube N1 and the second NMOS tube N2 is simply and effectively improved, the influence of a load is avoided, the on-resistance of the first NMOS tube N1 and the second NMOS tube N2 is reduced, and the power consumption is reduced; on the other hand, the cross-coupled charge pump units in the multi-stage cascade connection effectively prevent the reverse current between stages of the cross-coupled charge pump units and reduce the waste of the current through simple clock delay; thereby effectively improving the efficiency of the cross-coupled charge pump cell as a whole.

(3) The circuit of the invention is simple, reliable and easy to realize;

the circuit of the invention is very simple in circuit realization and extremely late in realization no matter a second branch circuit used for reducing the on-resistance of the first NMOS pipe N1 and a first branch circuit used for reducing the on-resistance of the second NMOS pipe N2 are added in the cross-coupled charge pump unit, or a clock circuit used for preventing the inter-stage reverse current of the cross-coupled charge pump structure, thereby ensuring the reliability and practicability of the circuit.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (8)

1. A cross-coupled charge pump cell, comprising: the first NMOS tube, the second NMOS tube, the first branch and the second branch; wherein the content of the first and second substances,

the first branch comprises a first end, a second end, a third end, a fourth end and a fifth end; the first end of the first branch circuit is connected with the grid electrode of the first NMOS tube, the second end of the first branch circuit is connected with input voltage, and the fifth end of the first branch circuit is connected with a complementary clock signal; a diode formed by splicing first PMOS tubes is connected between the third end of the first branch circuit and the fourth end of the first branch circuit, and the fourth end of the first branch circuit is connected to an output end;

the second branch comprises a first end, a second end, a third end, a fourth end and a fifth end; the first end of the second branch circuit is connected with the grid electrode of the second NMOS tube and the third end of the first branch circuit, the second end of the second branch circuit is connected with the input voltage, the third end of the second branch circuit is connected with the first end of the first branch circuit, and the fifth end of the second branch circuit is connected with a clock signal; and a diode formed by splicing second PMOS tubes is connected between the third end of the second branch and the fourth end of the second branch, and the fourth end of the second branch is connected to the output end.

2. The cross-coupled charge pump cell of claim 1, wherein: the power supply also comprises a third PMOS tube, a fourth PMOS tube, a first capacitor and a second capacitor; the drain electrode of the first NMOS tube is connected with the input voltage, and the source electrode of the first NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the upper polar plate of the first capacitor; the drain electrode of the second NMOS tube is connected with the input voltage, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube and the upper polar plate of the second capacitor; the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the fourth end of the first branch circuit and the fourth end of the second branch circuit are connected and then jointly used as the output end of the cross-coupling charge pump unit; the lower polar plate of the first capacitor is connected with the complementary clock signal; and the lower polar plate of the second capacitor is connected with the clock signal.

3. The cross-coupled charge pump cell of claim 1, wherein the first branch comprises: the third NMOS tube, the first PMOS tube and a third capacitor; wherein the content of the first and second substances,

the lower pole plate of the third capacitor is connected with the complementary clock signal, and the upper pole plate of the third capacitor is connected with the third end of the first branch circuit, the grid electrode of the fourth NMOS tube and the grid electrode of the second NMOS tube;

the drain electrode of the third NMOS tube is connected with the input voltage, and the source electrode of the third NMOS tube is connected with the first end of the second branch and the drain electrode of the first PMOS tube;

the grid electrode of the first PMOS tube is in short circuit with the source electrode of the first PMOS tube to form a diode and serve as the fourth end of the first branch circuit.

4. The cross-coupled charge pump cell of claim 3, wherein the second branch comprises: the fourth NMOS transistor, the second PMOS transistor and a fourth capacitor; wherein the content of the first and second substances,

the lower pole plate of the fourth capacitor is connected with the clock signal, and the upper pole plate of the fourth capacitor is connected with the third end of the second branch circuit, the grid electrode of the third NMOS tube and the grid electrode of the first NMOS tube;

the drain electrode of the fourth NMOS tube is connected with the input voltage, and the source electrode of the fourth NMOS tube is connected with the first end of the first branch circuit and the drain electrode of the second PMOS tube;

and the grid electrode of the second PMOS tube is in short circuit with the source electrode of the second PMOS tube to form a diode and serve as the fourth end of the second branch circuit.

5. The cross-coupled charge pump unit of claim 4, wherein the body regions of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all connected to a ground voltage.

6. A cross-coupled charge pump structure comprises N-stage cross-coupled charge pump units; the cross-coupled charge pump cell is a cross-coupled charge pump cell as claimed in any one of claims 1 to 5; the input end of the 1 st-stage cross-coupled charge pump unit is connected with the voltage of the input end, and the input end of the j-th-stage cross-coupled charge pump unit is connected with the output end of the j-1 st-stage cross-coupled charge pump unit; wherein N is an integer of 2 or more, and j is an integer of 1 or more and N or less.

7. The cross-coupled charge pump structure of claim 6, further comprising a clock generation circuit, the clock generation circuit comprising:

n stages of delay units connected in series in sequence; the output end of the ith delay unit is connected with at least the fifth end of the second branch in the ith stage of the cross-coupled charge pump unit; i is an integer less than or equal to N.

8. The cross-coupled charge pump structure of claim 7,

the 1 st stage of the delay unit comprises a buffer, and the input end of the buffer is connected with a clock signal;

the j-th stage of the delay unit comprises a buffer and an adjustable capacitor, an upper polar plate of the adjustable capacitor in the j-th stage of the delay unit is connected with an output end of the buffer in the j-th delay unit, and a lower polar plate of each adjustable capacitor is grounded; the buffers are connected in series in sequence.

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