CN102270984A - Positive high voltage level conversion circuit - Google Patents
Positive high voltage level conversion circuit Download PDFInfo
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Abstract
The invention discloses a positive high voltage level conversion circuit, which belongs to the technical field of integrated circuit designing. Connection relationships of parts of the positive high voltage level conversion circuit are that: an input voltage VIN is connected with a common node of an inverter INV1 and a first bootstrap circuit; the inverter INV1 is also connected with a second bootstrap circuit; and a voltage conversion circuit is connected with the first bootstrap circuit, the second bootstrap circuit and an output voltage VOUT. The positive high voltage level conversion circuit has the advantages that: the circuit has a simple circuit structure, high conversion speed and low power consumption; the two bootstrap circuits increases the amplitude of oscillator of a low voltage control signal once and enhances the driving capability of two high voltage N-channel metal oxide semiconductor (NMOS) transistors in the voltage conversion circuit, thereby reducing stiff competition between a pull-down NMOS transistor and a pull-up P-channel metal oxide semiconductor (PMOS) transistor in a voltage conversion process of the voltage conversion circuit and reducing the power consumption for high voltage conversion; and the circuit still can work normally under low power voltage.
Description
Technical field
The invention belongs to the integrated circuit (IC) design technical field, particularly a kind of positive high voltage level shifting circuit.
Background technology
At present, flash memory (Flash memory) is widely used in the portable sets such as mobile phone, camera, palmtop PC, advantages such as the power down data are not lost, high program speed, high integration that it has.Fig. 1 is the profile of a conventional flash memory cells, the stacked gate structure that it is made up of polysilicon control grid 10 and floating boom 12.On p type substrate 16, by injecting source electrode 14 and the drain electrode 15 that forms the n+ structure.In addition, 16 of floating boom 12 and p type substrates are isolated with second insulating barrier 13, between polysilicon control grid 10 and the floating boom 12 with 11 isolation of first insulating barrier.This stacked gate structure makes the threshold voltage of the memory cell seen from polysilicon control grid 10, depends on the quantity of electronics in the floating boom 12.
Flash cell adopts Fowler-Nordheim (being called for short F-N), and tunneling effect is programmed, erase operation.Table 1 is that flash cell carries out the exemplary voltages on various when operation control grids, drain electrode, the source electrode.
| Operation | Control gate | The drain region | Source area |
| Programming | 10V | -5V | -5V |
| Wipe | -5V | 10V | 10V |
| Read | 2.5V | 0.8V | 0V |
Table 1
As can be seen from the above table, when memory carries out different operating, all need to apply positive high voltage, this just needs one can be the positive high voltage level shifting circuit of corresponding positive high voltage with the data conversion of input.
Fig. 2 is a traditional positive high voltage level shifting circuit.When the IN input voltage is 0V, be output as high level voltage by the INV inverter, so nmos pass transistor 204 conductings, make also conducting of PMOS transistor 201.Therefore the N node voltage by on move the VPH positive high voltage to, this makes PMOS transistor 203 turn-off, so the OUT output voltage is the VSS earth potential.
When the VIN input voltage was the VDD supply voltage, nmos pass transistor 202 conductings made 203 conductings of PMOS transistor.Therefore the OUT output voltage is pulled to the VPH positive high voltage.Nmos pass transistor 204 turn-offs in addition, has cut off earthy DC channel from the VPH positive high voltage to VSS, and the OUT output voltage remains the VPH positive high voltage.As seen, the OUT output voltage can switch between VPH positive high voltage and VSS earth potential, thereby has finished the control and the switching of IN input voltage to the VPH positive high voltage.
Yet, for traditional positive high voltage level switching circuit shown in Figure 2, when the VDD supply voltage reduces, the gate drive voltage of nmos pass transistor 202 and nmos pass transistor 204 descends, therefore its ducting capacity will descend, cause the intensified competition between PMOS transistor AND gate nmos pass transistor in the level conversion process, bigger level conversion delay and conversion power consumption occur.When the VDD supply voltage further descends, even the problem that circuit can not normally switch high pressure can appear.The simple method that increases the nmos pass transistor size will cause the area of commutation circuit sharply to increase, and improve the technology cost.In addition, because word line and number of bit are numerous in the flash memory system, the performance degradation of high pressure commutation circuit will have a strong impact on the performance of whole flash memory system.
Summary of the invention
Purpose of the present invention discloses a kind of positive high voltage level shifting circuit at above-mentioned defective.Its annexation is as follows: the VIN input voltage connects the common node of the INV1 inverter and first boostrap circuit, the INV1 inverter also is connected with second boostrap circuit, and voltage conversion circuit is connected with first boostrap circuit, second boostrap circuit and VOUT output voltage respectively.
The annexation of described first boostrap circuit is as follows: the VIN input voltage connects the input of first inverter respectively, the grid of the transistorized grid of the 2nd PMOS and first nmos pass transistor, first inverter and first capacitances in series, the N1 node connects first electric capacity respectively, the one PMOS transistor drain and the transistorized source electrode of the 2nd PMOS, the N2 node connects the transistorized grid of a PMOS respectively, the grid of the 3rd nmos pass transistor, the drain electrode of the 2nd PMOS transistor drain and first nmos pass transistor, the VDD supply voltage connects the transistorized substrate of the 2nd PMOS and transistorized source electrode of a PMOS and substrate respectively, and the source electrode of first nmos pass transistor all is connected the VSS earth potential with substrate.
The annexation of described second boostrap circuit is as follows: the N0 node connects the output of INV1 inverter respectively, the input of second inverter, the grid of the transistorized grid of the 4th PMOS and second nmos pass transistor, second inverter and second capacitances in series, the N3 node connects second electric capacity respectively, the 3rd PMOS transistor drain and the transistorized source electrode of the 4th PMOS, the N4 node connects the transistorized grid of the 3rd PMOS respectively, the grid of the 4th nmos pass transistor, the drain electrode of the 4th PMOS transistor drain and second nmos pass transistor, the VDD supply voltage connects the transistorized substrate of the 4th PMOS and transistorized source electrode of the 3rd PMOS and substrate respectively, and the source electrode of second nmos pass transistor all is connected the VSS earth potential with substrate.
The annexation of described voltage conversion circuit is as follows: the VPH positive high voltage connects the transistorized source electrode of the 5th PMOS and substrate and transistorized source electrode of the 6th PMOS and substrate respectively, the VSS earth potential connects source electrode and substrate and the transistorized source electrode of the 6th PMOS and the substrate of the 3rd nmos pass transistor respectively, the transistorized grid of the 5th PMOS connects the drain electrode of the 6th PMOS transistor drain, the 4th nmos pass transistor and the common node of VOUT output voltage, and the transistorized grid of the 6th PMOS connects the common node of the drain electrode of five PMOS transistor drain and the 3rd nmos pass transistor.
Beneficial effect of the present invention is: circuit structure is simple, conversion speed is fast, power consumption is little.Two boostrap circuits increase the amplitude of oscillation of low-voltage control signal and are twice, two transistorized driving forces of high pressure NMOS in the voltage conversion circuit have been strengthened, thereby reduced voltage conversion circuit and in the voltage transitions process, drawn competition serious between the PMOS transistor on the pull-down NMOS transistor AND gate, reduced the power consumption of high pressure conversion, the present invention still can operate as normal under very low supply voltage.
Description of drawings
Fig. 1 is the profile of a traditional flash memory cell;
Fig. 2, traditional positive high voltage level shifting circuit structural representation;
Fig. 3, an embodiment of the positive voltage level change-over circuit that the present invention proposes;
Fig. 4, another embodiment of the positive voltage level change-over circuit that the present invention proposes.
Embodiment
The present invention will be further described below in conjunction with accompanying drawing.
As shown in Figure 3, a kind of annexation of positive high voltage level shifting circuit is as follows: the VIN input voltage connects the common node of the INV1 inverter 40 and first boostrap circuit 41, INV1 inverter 40 also is connected with second boostrap circuit 42, and voltage conversion circuit 43 is connected with the VOUT output voltage with first boostrap circuit 41, second boostrap circuit 42 respectively.
The annexation of first boostrap circuit 41 is as follows: the VIN input voltage connects the input of first inverter 4101 respectively, the grid of the grid of the 2nd PMOS transistor 4104 and first nmos pass transistor 4105, first inverter 4101 is connected with first electric capacity 4102, the N1 node connects first electric capacity 4102 respectively, the source electrode of the drain electrode of the one PMOS transistor 4103 and the 2nd PMOS transistor 4104, the N2 node connects the grid of a PMOS transistor 4103 respectively, the grid of the 3rd nmos pass transistor 4302, the drain electrode of the drain electrode of the 2nd PMOS transistor 4104 and first nmos pass transistor 4105, the VDD supply voltage connects the substrate of the 2nd PMOS transistor 4104 and the source electrode and the substrate of a PMOS transistor 4103 respectively, and the source electrode of first nmos pass transistor 4105 all is connected the VSS earth potential with substrate.
The annexation of second boostrap circuit 42 is as follows: the N0 node connects the output of INV1 inverter 40 respectively, the input of second inverter 4201, the grid of the grid of the 4th PMOS transistor 4204 and second nmos pass transistor 4205, second inverter 4201 is connected with second electric capacity 4202, the N3 node connects second electric capacity 4202 respectively, the source electrode of the drain electrode of the 3rd PMOS transistor 4203 and the 4th PMOS transistor 4204, the N4 node connects the grid of the 3rd PMOS transistor 4203 respectively, the grid of the 4th nmos pass transistor 4304, the drain electrode of the drain electrode of the 4th PMOS transistor 4204 and second nmos pass transistor 4205, the VDD supply voltage connects the substrate of the 4th PMOS transistor 4204 and the source electrode and the substrate of the 3rd PMOS transistor 4203 respectively, and the source electrode of second nmos pass transistor 4205 all is connected the VSS earth potential with substrate.
The annexation of voltage conversion circuit 43 is as follows: the VPH positive high voltage connects the source electrode of the 5th PMOS transistor 4301 and the source electrode and the substrate of substrate and the 6th PMOS transistor 4303 respectively, the VSS earth potential connects the source electrode of the 3rd nmos pass transistor 4302 and the source electrode and the substrate of substrate and the 6th PMOS transistor 4303 respectively, the 5th PMOS transistor 4301 is connected with the 6th PMOS transistor 4303 cross-couplings, the grid of the 5th PMOS transistor 4301 connects the drain electrode of the 6th PMOS transistor 4303, the common node of the drain electrode of the 4th nmos pass transistor 4304 and VOUT output voltage, the grid of the 6th PMOS transistor 4303 connect the common node of the drain electrode of the drain electrode of five PMOS transistors 4301 and the 3rd nmos pass transistor 4302.
Be illustrated in figure 3 as an a kind of embodiment of positive high voltage level shifting circuit, its operation principle is as follows:
Setting the VDD supply voltage is 1.5V, and the VSS earth potential is 0V, and the VPH positive high voltage is 7.5V.First boostrap circuit 41 and second boostrap circuit 42 are important component parts of a kind of positive high voltage level shifting circuit, both operation principles are identical, with first boostrap circuit 41 is example, when the VIN input voltage is 1.5V, first inverter, 4101 output end voltages are 0V, the source electrode of first nmos pass transistor 4105 connects the VSS earth potential, 4105 conductings of first nmos pass transistor, the 2nd PMOS transistor 4104 turn-offs, at this moment, the N2 node voltage is 0V, PMOS transistor 4103 conducting owing to the Voltage Feedback of N2 node, so the N1 node voltage is 1.5V.
When the VIN input voltage was 0V by the 1.5V upset, the upset of first inverter, 4101 output end voltages was 1.5V, because the charge-retention property of first electric capacity 4102, the N1 node voltage will be 3V.At this moment, 4104 conductings of the 2nd PMOS transistor, first nmos pass transistor 4105 turn-offs owing to grid connects the VIN input voltage, so the N2 node voltage is 3V.In addition, a PMOS transistor 4103 is owing to the Voltage Feedback of N2 node is turn-offed, thereby the N1 node voltage remains 3V.
From top analysis as can be seen, first boostrap circuit 41 and second boostrap circuit 42 have utilized the charge-retention property of electric capacity, and when the amplitude of oscillation of input signal was 0V to 1.5V, the amplitude of oscillation of output signal was 0V to 3V, thus the voltage of low-voltage signal bootstrapping function.
1) when the VIN input voltage is 1.5V, the N0 node voltage is 0V, according to the principle Analysis of above-mentioned boostrap circuit as can be known, the N2 node voltage is 3V, because second electric capacity 4202 has charge-retention property, the voltage jump of N3 node is 3V, N4 node (output node) voltage is 3V, at this moment, because N2 node and N4 node are connected the grid of the 3rd nmos pass transistor 4302 and the 4th nmos pass transistor 4304 respectively, the 3rd nmos pass transistor 4302 turn-offs, 4304 conductings of the 4th nmos pass transistor, and driving voltage is 3V, thereby the VOUT output voltage is 0V, and the 5th PMOS transistor 4301 is because the feedback of VOUT output voltage and conducting, the N5 node voltage is 7.5V, therefore, the 6th PMOS transistor 4303 turn-offs, thereby the VOUT output voltage remains 0V.
2) when the VIN input voltage when jumping to 0V for 1.5V, the N0 node voltage is 1.5V.According to the principle Analysis of above-mentioned boostrap circuit as can be known, because first electric capacity 4102 has charge-retention property, the saltus step of N1 node voltage is 3V, and through the transmission of the 2nd PMOS transistor 4104, the N2 node voltage is 3V, and N4 node (output node) voltage is 0V.At this moment, the grid that is connected the 3rd nmos pass transistor 4302 and the 4th nmos pass transistor 4304 owing to N2 node and N4 node respectively, the 4th nmos pass transistor 4304 turn-offs, 4302 conductings of the 3rd nmos pass transistor, the N5 node voltage is 0V, the conducting of the 6th PMOS transistor 4303 owing to N5 node voltage feedback, thereby the VOUT output voltage is 7.5V.Simultaneously, the 5th PMOS transistor 4301 is owing to the feedback of VOUT output voltage is turn-offed, thereby the VOUT output voltage remains 7.5V.
By last surface analysis as can be known, the positive high voltage level shifting circuit is by adopting the circuit bootstrap technique, make that the driving voltage of nmos pass transistor improves 2 times in the voltage conversion circuit 43, nmos pass transistor and the transistorized competition of PMOS when having reduced the high pressure conversion, thereby improved level conversion speed, reduced the transient current and the dynamic power consumption of level conversion.The 3rd nmos pass transistor 4302 and 4304 selections of the 4th nmos pass transistor.When the continuous decline of system power supply voltage, the positive high voltage level shifting circuit still can operate as normal.
Be illustrated in figure 4 as an alternative embodiment of the invention, compare with Fig. 3, the 5th nmos pass transistor 4106 and the 6th nmos pass transistor 4206 have been increased, the grid of the 5th nmos pass transistor 4106 connects the VDD supply voltage, drain electrode connects the N2 node, source electrode connects the drain electrode of first nmos pass transistor 4105, and substrate connects the VSS earth potential; The grid of the 6th nmos pass transistor 4206 connects the VDD supply voltage, and drain electrode connects the N4 node, and source electrode connects the drain electrode of second nmos pass transistor 4205, and substrate connects the VSS earth potential; The 5th nmos pass transistor 4106 and the 6th nmos pass transistor 4206 play the effect that reduces drain-source voltage in first nmos pass transistor 4105 and 4205 work of second nmos pass transistor respectively, thereby first nmos pass transistor 4105 and second nmos pass transistor 4205 can adopt withstand voltage low transistor.
Although in conjunction with Fig. 3 and Fig. 4 the present invention is had been described in detail and explains, it should be understood that changes form of the present invention and details and does not break away from the spirit and scope of the present invention, and it all should be included among the claim scope of the present invention.
Claims (4)
1. positive high voltage level shifting circuit, it is characterized in that, its annexation is as follows: the VIN input voltage connects the common node of INV1 inverter (40) and first boostrap circuit (41), INV1 inverter (40) also is connected with second boostrap circuit (42), and voltage conversion circuit (43) is connected with the VOUT output voltage with first boostrap circuit (41), second boostrap circuit (42) respectively.
2. a kind of positive high voltage level shifting circuit according to claim 1, it is characterized in that, the annexation of described first boostrap circuit (41) is as follows: the VIN input voltage connects the input of first inverter (4101) respectively, the grid of the grid of the 2nd PMOS transistor (4104) and first nmos pass transistor (4105), first inverter (4101) is connected with first electric capacity (4102), the N1 node connects first electric capacity (4102) respectively, the source electrode of the drain electrode of the one PMOS transistor (4103) and the 2nd PMOS transistor (4104), the N2 node connects the grid of a PMOS transistor (4103) respectively, the grid of the 3rd nmos pass transistor (4302), the drain electrode of the drain electrode of the 2nd PMOS transistor (4104) and first nmos pass transistor (4105), the VDD supply voltage connects the substrate of the 2nd PMOS transistor (4104) and the source electrode and the substrate of a PMOS transistor (4103) respectively, and the source electrode of first nmos pass transistor (4105) all is connected the VSS earth potential with substrate.
3. a kind of positive high voltage level shifting circuit according to claim 1, it is characterized in that, the annexation of described second boostrap circuit (42) is as follows: the N0 node connects the output of INV1 inverter (40) respectively, the input of second inverter (4201), the grid of the grid of the 4th PMOS transistor (4204) and second nmos pass transistor (4205), second inverter (4201) is connected with second electric capacity (4202), the N3 node connects second electric capacity (4202) respectively, the source electrode of the drain electrode of the 3rd PMOS transistor (4203) and the 4th PMOS transistor (4204), the N4 node connects the grid of the 3rd PMOS transistor (4203) respectively, the grid of the 4th nmos pass transistor (4304), the drain electrode of the drain electrode of the 4th PMOS transistor (4204) and second nmos pass transistor (4205), the VDD supply voltage connects the substrate of the 4th PMOS transistor (4204) and the source electrode and the substrate of the 3rd PMOS transistor (4203) respectively, and the source electrode of second nmos pass transistor (4205) all is connected the VSS earth potential with substrate.
4. a kind of positive high voltage level shifting circuit according to claim 1, it is characterized in that, the annexation of described voltage conversion circuit (43) is as follows: the VPH positive high voltage connects the source electrode of the 5th PMOS transistor (4301) and the source electrode and the substrate of substrate and the 6th PMOS transistor (4303) respectively, the VSS earth potential connects the source electrode of the 3rd nmos pass transistor (4302) and the source electrode and the substrate of substrate and the 4th nmos pass transistor (4304) respectively, the grid of the 5th PMOS transistor (4301) connects the drain electrode of the 6th PMOS transistor (4303), the drain electrode of the 4th nmos pass transistor (4304) and the common node of VOUT output voltage, the grid of the 6th PMOS transistor (4303) connect the common node of the drain electrode of the drain electrode of five PMOS transistors (4301) and the 3rd nmos pass transistor (4302).
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| CN 201110185191 CN102270984B (en) | 2011-07-01 | 2011-07-01 | Positive high voltage level conversion circuit |
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| CN 201110185191 CN102270984B (en) | 2011-07-01 | 2011-07-01 | Positive high voltage level conversion circuit |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368555A (en) * | 2012-03-27 | 2013-10-23 | 联发科技股份有限公司 | Level shifter circuit |
| CN103795401A (en) * | 2014-02-18 | 2014-05-14 | 南通大学 | Output unit circuit with controllable output level |
| CN103997334A (en) * | 2013-02-20 | 2014-08-20 | 精工电子有限公司 | Level shift circuit |
| CN104639151A (en) * | 2014-12-23 | 2015-05-20 | 苏州宽温电子科技有限公司 | Positive-high-voltage level conversion circuit |
| CN106130536A (en) * | 2016-06-20 | 2016-11-16 | 华为技术有限公司 | Level shifting circuit and electronic equipment |
| CN107124177A (en) * | 2017-06-30 | 2017-09-01 | 深圳贝特莱电子科技股份有限公司 | A kind of capacitance coupling type level shifting circuit for fingerprint recognition driving chip |
| CN108494388A (en) * | 2018-03-22 | 2018-09-04 | 中国电子科技集团公司第二十四研究所 | A kind of high-speed low-noise dynamic comparer |
| CN109245730A (en) * | 2018-08-21 | 2019-01-18 | 中国科学院微电子研究所 | Switching power amplifier and digital transmitter |
| CN109309493A (en) * | 2017-07-27 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | High-voltage level shift circuit and semiconductor device |
| CN109672439A (en) * | 2019-01-17 | 2019-04-23 | 南京观海微电子有限公司 | Pressure-resistant level shifting circuit |
| CN110739960A (en) * | 2019-10-18 | 2020-01-31 | 四川中微芯成科技有限公司 | level conversion circuit for increasing conversion speed and electronic equipment |
| CN111277261A (en) * | 2020-04-03 | 2020-06-12 | 上海集成电路研发中心有限公司 | Level conversion circuit |
| CN112671393A (en) * | 2020-12-29 | 2021-04-16 | 成都锐成芯微科技股份有限公司 | Level conversion circuit |
| CN112929020A (en) * | 2021-01-22 | 2021-06-08 | 珠海零边界集成电路有限公司 | Electronic equipment and level conversion circuit thereof |
| CN113285706A (en) * | 2020-02-19 | 2021-08-20 | 圣邦微电子（北京）股份有限公司 | Voltage level conversion circuit |
| CN114785099A (en) * | 2022-06-17 | 2022-07-22 | 深圳芯能半导体技术有限公司 | Grid driving circuit |
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Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103368555A (en) * | 2012-03-27 | 2013-10-23 | 联发科技股份有限公司 | Level shifter circuit |
| CN103997334A (en) * | 2013-02-20 | 2014-08-20 | 精工电子有限公司 | Level shift circuit |
| CN103795401A (en) * | 2014-02-18 | 2014-05-14 | 南通大学 | Output unit circuit with controllable output level |
| CN104639151A (en) * | 2014-12-23 | 2015-05-20 | 苏州宽温电子科技有限公司 | Positive-high-voltage level conversion circuit |
| CN106130536B (en) * | 2016-06-20 | 2019-06-14 | 华为技术有限公司 | Level shifting circuit and electronic equipment |
| CN106130536A (en) * | 2016-06-20 | 2016-11-16 | 华为技术有限公司 | Level shifting circuit and electronic equipment |
| CN107124177A (en) * | 2017-06-30 | 2017-09-01 | 深圳贝特莱电子科技股份有限公司 | A kind of capacitance coupling type level shifting circuit for fingerprint recognition driving chip |
| CN109309493B (en) * | 2017-07-27 | 2022-05-13 | 中芯国际集成电路制造(上海)有限公司 | High-voltage level shift circuit and semiconductor device |
| CN109309493A (en) * | 2017-07-27 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | High-voltage level shift circuit and semiconductor device |
| CN108494388A (en) * | 2018-03-22 | 2018-09-04 | 中国电子科技集团公司第二十四研究所 | A kind of high-speed low-noise dynamic comparer |
| CN109245730A (en) * | 2018-08-21 | 2019-01-18 | 中国科学院微电子研究所 | Switching power amplifier and digital transmitter |
| CN109672439A (en) * | 2019-01-17 | 2019-04-23 | 南京观海微电子有限公司 | Pressure-resistant level shifting circuit |
| CN110739960A (en) * | 2019-10-18 | 2020-01-31 | 四川中微芯成科技有限公司 | level conversion circuit for increasing conversion speed and electronic equipment |
| CN113285706A (en) * | 2020-02-19 | 2021-08-20 | 圣邦微电子（北京）股份有限公司 | Voltage level conversion circuit |
| CN113285706B (en) * | 2020-02-19 | 2023-08-01 | 圣邦微电子（北京）股份有限公司 | Voltage level conversion circuit |
| CN111277261A (en) * | 2020-04-03 | 2020-06-12 | 上海集成电路研发中心有限公司 | Level conversion circuit |
| CN111277261B (en) * | 2020-04-03 | 2023-10-20 | 上海集成电路研发中心有限公司 | Level conversion circuit |
| CN112671393A (en) * | 2020-12-29 | 2021-04-16 | 成都锐成芯微科技股份有限公司 | Level conversion circuit |
| CN112929020A (en) * | 2021-01-22 | 2021-06-08 | 珠海零边界集成电路有限公司 | Electronic equipment and level conversion circuit thereof |
| CN112929020B (en) * | 2021-01-22 | 2023-09-26 | 珠海零边界集成电路有限公司 | Electronic device and level conversion circuit thereof |
| CN114785099A (en) * | 2022-06-17 | 2022-07-22 | 深圳芯能半导体技术有限公司 | Grid driving circuit |
| CN114785099B (en) * | 2022-06-17 | 2022-09-13 | 深圳芯能半导体技术有限公司 | Grid driving circuit |
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