CN114093950B - LDMOS device of stepped STI auxiliary field plate and manufacturing method thereof - Google Patents
LDMOS device of stepped STI auxiliary field plate and manufacturing method thereof Download PDFInfo
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- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention provides an LDMOS device of a stepped STI auxiliary field plate and a preparation method thereof, wherein the LDMOS device comprises a first conductive type substrate, a first conductive type epitaxial layer, a first conductive type well region, a second conductive type drift region, a second conductive type source region, a first conductive type heavily doped region and an isolation medium region, wherein the isolation medium region has a structure with deep middle and shallow two sides; the semiconductor device further comprises a second conduction type drain region, an isolation gate dielectric layer, a gate electrode, a passivation layer, a source metal electrode and a drain metal electrode. The invention achieves the electric field optimization effect of the multilayer field plate through the one-step formed gate electrode field plate by utilizing the multilayer step type STI technology, improves the blocking capacity of the device, and simultaneously utilizes the gate control charge during forward conduction to assist in conduction so as to further reduce the on-resistance of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to an LDMOS device of a stepped STI auxiliary field plate and a manufacturing method thereof.
Background
The structure of the lateral double diffused field effect transistor LDMOS (Lateral Double Diffused Metal Oxide Semiconductor Field Effects Transistor) was proposed most prior to 1969 and is mainly applied as a switching device in the power and control fields. Later, the application research of the LDMOS is mainly in the radio frequency field, and the application research and the rapid development are mainly carried out in the end of the 20 th century. In order to meet the increasingly high frequency applications, in addition to the special attention required for the frequency characteristics, LDMOS also have new requirements for high breakdown voltage, low on-resistance, etc.
The field plate FP (Field Plate) structure is typically formed by extending a metal layer (or doped polysilicon) in contact with the PN junction and overlying an oxide layer. The MIS structure formed by the field plate, the silicon dioxide insulating layer and the bulk silicon can enable the area under the field plate to be in a depletion state due to a longitudinal electric field between the metal and the semiconductor when the PN junction is reversely biased. The depletion region is connected with the PN junction depletion layer, so that the depletion layer can be widened, and meanwhile, an electric field at the junction edge is dispersed to the field plate, the junction edge electric field is reduced, and the device voltage endurance capacity is improved. The field plate structure is widely applied to terminal protection of a power MOSFET and LDMOS structure.
The field plates commonly used for LDMOS include drain field plates, source field plates, gate electrode field plates. The field plate arrangement of the drift region near the source side is particularly critical. The current advanced multilayer field plate process can effectively reduce the peak value of the bulk electric field in the reverse blocking state by arranging a multilayer field plate or a step-shaped field plate on one side of the grid electrode close to the drain electrode, and can improve the doping concentration of the drift region as much as possible on the premise of ensuring that the breakdown voltage meets the requirement, thereby reducing the on-resistance of the device. However, the multi-layer field plate structure is complex in manufacturing process, multi-layer dielectric isolation and field plate forming are required to be considered optimally, and the requirement on later wiring is higher. In addition, the device structure by manufacturing the field oxide layer in the drift region and extending the gate and drain metals onto the field oxide layer can also have a certain effect of improving the breakdown voltage, but a certain gap is provided compared with the multi-layer field plate structure.
The shallow trench isolation STI (Shallow Trench Isolation) technique can meet the isolation requirements in semiconductor device fabrication by performing an undoped silicon glass (UGS) fill and post CMP planarization process within the shallow trench. Compared with the traditional LOCOS isolation process, the STI technology eliminates the bird's beak effect and can provide a flat surface, so that the STI technology is widely applied to device isolation in advanced semiconductor manufacturing.
Disclosure of Invention
In order to solve the technical problem of complex manufacturing process of the multi-layer field plate structure, the invention provides an LDMOS device of a stepped STI auxiliary field plate and a manufacturing method thereof.
An LDMOS device of a stepped STI auxiliary field plate comprises,
a first conductivity type substrate;
a first conductive type epitaxial layer formed on the first conductive type substrate;
a first conductivity type well region and a second conductivity type drift region on the first conductivity type epitaxial layer;
a second conductivity type source region and a first conductivity type heavily doped region located within the first conductivity type well region, wherein the second conductivity type source region is located on a side close to the second conductivity type drift region, the first conductivity type heavily doped region is located on a side away from the second conductivity type drift region, and a channel region is formed by a boundary difference between the first conductivity type well region and the second conductivity type source region on a side close to the second conductivity type drift region;
the isolation medium region is positioned in the second conduction type drift region and is of a structure with deep middle and shallow two sides;
a second conductive type drain region located at an edge of the second conductive type drift region, wherein the second conductive type drain region is located at a side away from the first conductive type well region;
the isolation gate dielectric layer is arranged on the top of the first conductive type epitaxial layer;
the gate electrode is arranged on the top of the isolation gate dielectric layer;
the passivation layer is arranged on the isolation gate dielectric layer and coats the gate electrode;
source electrode metal electrode and drain electrode metal electrode set up on two sides of dielectric layer of isolated gate separately; wherein a source metal electrode is disposed over the heavily doped region of the first conductivity type and a portion of the source region of the second conductivity type, and a drain metal electrode is disposed over the drain region of the second conductivity type.
Further, the isolation medium region has a step structure with deep middle and shallow two sides, and the number of steps is not less than 2.
Further, the isolation medium region is of a slow change type structure with deep middle and shallow two sides.
Further, a side of the isolation medium region facing the first conductive type well region is spaced apart from a boundary of the second conductive type drift region.
Further, the gate electrode is metal or doped polysilicon.
Further, the gate electrode completely covers the channel region, partially covers the second conductivity type source region, and partially covers the second conductivity type drift region.
Further, the boundary of the gate electrode on the side of the second conductive type drain region is located above the deepest part of the isolation medium region.
The preparation method of the LDMOS device of the upper stepped STI auxiliary field plate comprises the following steps:
s1, forming a first conductive type epitaxial layer on a first conductive type substrate;
s2, forming a second conductivity type drift region on the first conductivity type epitaxial layer through photoetching, injection and annealing processes;
s3, growing SiO on the first conductive type epitaxial layer 2 Layer and on SiO 2 Depositing a layer of Si on the layer 3 N 4 A layer;
s4, sequentially etching Si through photoetching and etching processes 3 N 4 Layer, siO 2 The layer and the second conductivity type drift region form a trench;
s5, after the photoetching mask in the step S4 is removed, etching Si for many times through photoetching and etching processes 3 N 4 Layer, siO 2 Forming a layer and a second conduction type drift region, wherein the trench obtained in the step S4 is the deepest, and the left side and the right side of the trench are shallower;
s6, removing the photoetching mask and Si generated in the step S5 3 N 4 Layer and SiO 2 After the layer, filling undoped silicon glass, carrying out CMP grinding, removing redundant silicon glass, and flattening the surface to form an isolation medium region;
s7, forming an isolation gate dielectric layer on the surface of the wafer in a thermal oxidation mode after an active region process and sacrificial oxidation, depositing doped polysilicon, and forming a gate electrode through photoetching and etching;
s8, forming a first conductive type well region, a first conductive type heavily doped region, a second conductive type source region and a second conductive type drain region respectively through multiple photoetching, injection, mask medium removal and high-temperature annealing processes;
s9, passivation mediums are deposited on two sides of the isolation gate dielectric layer, contact holes are formed through multiple photoetching and etching processes, metal is deposited and etched reversely, and a source electrode metal electrode and a drain electrode metal electrode are formed.
The invention has the beneficial effects that:
the invention achieves the electric field optimization effect of the multilayer field plate through the one-step formed gate electrode field plate by utilizing the multilayer step type STI technology, improves the blocking capacity of the device, and simultaneously utilizes the gate control charge during forward conduction to assist in conduction so as to further reduce the on-resistance of the device. Compared with the traditional multilayer field plate structure, the step type STI has the advantages of simple manufacturing flow, no need of considering multilayer medium isolation, high controllability of slow thickness change of the field plate medium, convenience and easiness in realization of wiring and the like on the surface of a later-stage device.
Drawings
Fig. 1 is a schematic structural diagram of an LDMOS device of embodiment 1.
Fig. 2 is a schematic structural diagram of an LDMOS device of embodiment 2.
Fig. 3 is a schematic diagram of a process flow for fabricating an LDMOS device of embodiment 1.
Reference numerals illustrate: 1. a first conductivity type substrate; 2. an epitaxial layer of the first conductivity type; 3. a second conductivity type drift region; 4. SiO (SiO) 2 A layer; 5. si (Si) 3 N 4 A layer; 6. a first layer of trenches; 7. a second layer of grooves; 8. a third layer trench; 9. isolating the dielectric region; 10. an isolation gate dielectric layer; 11. a gate electrode; 12. a first conductive-type well region; 13. a heavily doped region of the first conductivity type; 14. a second conductivity type source region; 15. a second conductivity type drain region; 16. a passivation layer; 17. a source metal electrode; 18. a drain metal electrode.
Detailed Description
The invention is further described below in connection with examples which are given solely for the purpose of illustration and are not to be construed as limitations on the scope of the claims, as other alternatives will occur to those skilled in the art and are within the scope of the claims.
Furthermore, in the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
An LDMOS device of a stepped STI-assisted field plate, as shown in FIG. 1, includes a first conductivity type substrate 1; a first conductivity type epitaxial layer 2 formed on the first conductivity type substrate 1; a first conductivity type well region 12 and a second conductivity type drift region 3 located on the first conductivity type epitaxial layer 2; a second conductivity type source region 14 and a first conductivity type heavily doped region 13 located in the first conductivity type well region 12, wherein the second conductivity type source region 14 is located on a side close to the second conductivity type drift region 3, the first conductivity type heavily doped region 13 is located on a side far from the second conductivity type drift region 3, and a boundary difference between the first conductivity type well region 12 and the second conductivity type source region 14 on a side close to the second conductivity type drift region forms a channel region; an isolation medium region 9 positioned in the second conductivity type drift region 3, wherein the isolation medium region 9 has a structure with deep middle and shallow two sides; a second conductivity type drain region 15 located at an edge of the second conductivity type drift region 3, wherein the second conductivity type drain region 15 is located at a side away from the first conductivity type well region 12; the isolation gate dielectric layer 10 is positioned at the top of the first conductive type epitaxial layer 2; the gate electrode 11 is positioned at the top of the isolation gate dielectric layer 10; the passivation layer 16 is positioned on the isolation gate dielectric layer 10 and coats the gate electrode 11; source metal electrode 17 and drain metal electrode 18 respectively located on both sides of isolation gate dielectric layer 10; wherein a source metal electrode 17 is located over the heavily doped region 13 of the first conductivity type and a portion of the source region 14 of the second conductivity type and a drain metal electrode 18 is located over the drain region 15 of the second conductivity type.
Specifically, the isolation medium region 9 has a step structure with deep middle and shallow two sides, and the number of steps is not less than 2.
The isolation medium region 9 is spaced apart from the boundary of the second conductivity type drift region 3 toward the side of the first conductivity type well region.
The gate electrode 11 is metal or doped polysilicon.
The gate electrode 11 completely covers the channel region, partially covers the second conductivity type source region 14, and partially covers the second conductivity type drift region 3.
The boundary of the gate electrode 11 on the side of the second conductivity type drain region 15 is located above the deepest portion of the isolation dielectric region 9.
The preparation method of the LDMOS device of the stepped STI auxiliary field plate, as shown in FIG. 3, comprises the following steps:
s1, a first conductive type substrate 1 is shown in FIG. 3 (a), and a first conductive type epitaxial layer 2 is formed on the first conductive type substrate 1 as shown in FIG. 3 (b);
s2, as shown in fig. 3 (c), forming a second conductive type drift region 3 on the first conductive type epitaxial layer 2 through photolithography, implantation and annealing processes;
s3, as shown in FIG. 3 (d), growing SiO on the first conductivity type epitaxial layer 2 2 Layer 4, and on SiO 2 Depositing a layer of Si on the layer 3 N 4 Layer 5;
s4, as shown in FIG. 3 (e), sequentially etching Si through photoetching and etching processes 3 N 4 Layer 5, siO 2 The layer 4 and the second conductivity type drift region 3 form a first layer trench 6;
s5, as shown in FIG. 3 (f) and FIG. 3 (g), removing the photoetching mask in the step S4, and etching Si by photoetching and etching processes 3 N 4 Layer 5, siO 2 The layer 4 and the second conductivity type drift region 3 are formed, a second layer trench 7 is formed with the first layer trench 6 obtained in step S4 as the deepest portion and the left and right sides being shallower, and Si is etched again 3 N 4 Layer 5, siO 2 The layer 4 and the second conductivity type drift region 3 form a third layer trench 8 shallower than the second layer trench 7.
S6, as shown in FIG. 3 (h), removing the photoetching mask and Si generated in the step S5 3 N 4 Layer 5 and SiO 2 After the layer 4, filling undoped silicon glass, carrying out CMP grinding, removing redundant silicon glass, and flattening the surface to form an isolation medium region 9;
s7, as shown in FIG. 3 (i), after the active region process and sacrificial oxidation, forming an isolation gate dielectric layer 10 on the surface of the wafer in a thermal oxidation mode, depositing doped polysilicon, and forming a gate electrode 11 through photoetching and etching;
s8, as shown in FIG. 3 (j), forming a first conductive type well region, a first conductive type heavily doped region, a second conductive type source region and a second conductive type drain region respectively through multiple photoetching, injection, mask medium removal and high-temperature annealing processes;
s9, as shown in fig. 3 (k), passivation mediums are deposited on two sides of the isolation gate dielectric layer, contact holes are formed through multiple photoetching and etching processes, metal is deposited and etched reversely, and a source electrode metal electrode and a drain electrode metal electrode are formed.
Example 2
As shown in fig. 2, the LDMOS device of the stepped STI-assisted field plate is substantially the same as that of embodiment 1, except that the isolation medium region 9 has a shallow intermediate and shallow two sides.
The preparation method of the LDMOS device of the stepped STI-assisted field plate is basically the same as that of embodiment 1, except for the steps of the formation process of the isolation medium region 9, and except for the step S5, the step S5 of this embodiment is as follows:
s5, after the photoetching mask in the step S4 is removed, etching Si for many times through photoetching and etching processes 3 N 4 Layer, siO 2 A layer and a drift region of a second conductivity type, forming a trench obtained in step S4The grooves are deepest and shallower on the left side and the right side;
it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.
Claims (8)
1. An LDMOS device of a stepped STI auxiliary field plate is characterized by comprising,
a first conductivity type substrate;
a first conductive type epitaxial layer formed on the first conductive type substrate;
a first conductivity type well region and a second conductivity type drift region on the first conductivity type epitaxial layer;
a second conductivity type source region and a first conductivity type heavily doped region located within the first conductivity type well region, wherein the second conductivity type source region is located on a side close to the second conductivity type drift region, the first conductivity type heavily doped region is located on a side away from the second conductivity type drift region, and a channel region is formed by a boundary difference between the first conductivity type well region and the second conductivity type source region on a side close to the second conductivity type drift region;
the isolation medium region is positioned in the second conduction type drift region and is of a structure with deep middle and shallow two sides;
a second conductive type drain region located at an edge of the second conductive type drift region, wherein the second conductive type drain region is located at a side away from the first conductive type well region;
the isolation gate dielectric layer is arranged on the top of the first conductive type epitaxial layer;
the gate electrode is arranged on the top of the isolation gate dielectric layer;
the passivation layer is arranged on the isolation gate dielectric layer and coats the gate electrode;
source electrode metal electrode and drain electrode metal electrode set up on two sides of dielectric layer of isolated gate separately; wherein a source metal electrode is disposed over the heavily doped region of the first conductivity type and a portion of the source region of the second conductivity type, and a drain metal electrode is disposed over the drain region of the second conductivity type.
2. The LDMOS device of claim 1, wherein said isolation dielectric region has a step structure with a deep middle and shallow sides, and the number of steps is not less than 2.
3. The LDMOS device of claim 1 wherein said isolation dielectric region is a shallow trench isolation structure with a deep middle and shallow sides.
4. The LDMOS device of claim 2, wherein a side of the isolation dielectric region facing the first conductivity type well region is spaced apart from a boundary of the second conductivity type drift region.
5. The LDMOS device of claim 1 wherein the gate electrode is metal or doped polysilicon.
6. The LDMOS device of claim 1, wherein the gate electrode completely covers the channel region, partially covers the second conductivity type source region, and partially covers the second conductivity type drift region.
7. The LDMOS device of claim 1, wherein a boundary of said gate electrode on a side of said second conductivity type drain region is located above a deepest portion of said isolation dielectric region.
8. The method for manufacturing the stepped STI-assisted field plate LDMOS device of claim 1, comprising the steps of:
s1, forming a first conductive type epitaxial layer on a first conductive type substrate;
s2, forming a second conductivity type drift region on the first conductivity type epitaxial layer through photoetching, injection and annealing processes;
s3, growing SiO on the first conductive type epitaxial layer 2 Layer and on SiO 2 Depositing a layer of Si on the layer 3 N 4 A layer;
s4, sequentially etching Si through photoetching and etching processes 3 N 4 Layer, siO 2 The layer and the second conductivity type drift region form a trench;
s5, after the photoetching mask in the step S4 is removed, etching Si for many times through photoetching and etching processes 3 N 4 Layer, siO 2 Forming a layer and a second conduction type drift region, wherein the trench obtained in the step S4 is the deepest, and the left side and the right side of the trench are shallower;
s6, removing the photoetching mask and Si generated in the step S5 3 N 4 Layer and SiO 2 After the layer, filling undoped silicon glass, carrying out CMP grinding, removing redundant silicon glass, and flattening the surface to form an isolation medium region;
s7, forming an isolation gate dielectric layer on the surface of the wafer in a thermal oxidation mode after an active region process and sacrificial oxidation, depositing doped polysilicon, and forming a gate electrode through photoetching and etching;
s8, forming a first conductive type well region, a first conductive type heavily doped region, a second conductive type source region and a second conductive type drain region respectively through multiple photoetching, injection, mask medium removal and high-temperature annealing processes;
s9, passivation mediums are deposited on two sides of the isolation gate dielectric layer, contact holes are formed through multiple photoetching and etching processes, metal is deposited and etched reversely, and a source electrode metal electrode and a drain electrode metal electrode are formed.
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