CN110957370A - Method for manufacturing lateral double-diffused transistor - Google Patents
Method for manufacturing lateral double-diffused transistor Download PDFInfo
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- CN110957370A CN110957370A CN201911378641.XA CN201911378641A CN110957370A CN 110957370 A CN110957370 A CN 110957370A CN 201911378641 A CN201911378641 A CN 201911378641A CN 110957370 A CN110957370 A CN 110957370A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
Disclosed is a method for manufacturing a lateral double diffused transistor, comprising: sequentially depositing a pad oxide layer and a first hard mask on the surface of a substrate, wherein a P-type well region and an N-type well region which are separated from each other are formed on the substrate; forming an N-type drift region in the substrate through the opening of the first hard mask, the N-type drift region being spaced apart from and abutting the P-type well region; depositing a second hard mask on the first hard mask and the surface of the pad oxide layer; and forming a field oxide layer over the N-type drift region through the opening of the second hard mask. According to the manufacturing method, the first hard mask is etched to form the opening, the drift region is formed through the opening, the mask is saved, the second hard mask is deposited above the first hard mask, the thickness of the nitride layer above the drift region is smaller than that of the nitride layer in other regions, the length of the bird's beak is increased, the electric field of the silicon substrate below the bird's beak region is reduced, the process cost is saved, and meanwhile the breakdown voltage of the transistor is effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a transverse double-diffusion transistor.
Background
As one of power field effect transistors, a Lateral Diffused MOS (LDMOS) transistor has excellent characteristics of process compatibility, good thermal stability and frequency stability, high gain, low feedback capacitance and thermal resistance, and constant input impedance, and thus is widely used, and people have higher and higher requirements for the performance of LDMOS.
In the application of the LDMOS, the source-drain on-resistance Rdson of the device is required to be reduced as much as possible on the premise of meeting the high source-drain breakdown voltage BV-dss, but the optimization requirements of the source-drain breakdown voltage and the on-resistance are contradictory. Generally, the method for reducing the on-resistance of the LDMOS is to use various RESURF (Reduced SURface Field) theories to fully deplete the LDMOS while continuously increasing the concentration of the drift region, so as to obtain a low on-resistance and maintain a high breakdown voltage.
Fig. 1 shows a schematic cross-sectional structure of a prior art lateral double diffused transistor. As shown in fig. 1, in the conventional NLDMOS process, a P-well region 102, an N-well region 103 and a drift region 104 are formed in a substrate 101, a field plate 151 is formed on a field oxide layer 131 of the drift region, and a short bird's beak region is formed between a Gate oxide (Gate oxide layer 141) and the field oxide layer 131 due to a conventional field oxide layer preparation process, so that when the concentration of the drift region 104 is high, according to the gaussian theorem, an extremely strong electric field is easily generated in silicon (such as a star mark in the figure) below the Gate oxide layer 141 close to the field oxide layer 131, thereby causing breakdown, and making the breakdown voltage of the NLDMOS lower.
In the existing manufacturing process, the electric field at the star mark shown in fig. 1 is reduced by reducing the concentration of the drift region or reducing the overlapping size of the drift region and the gate oxide layer, so that the breakdown voltage is improved, but the on-resistance of the LDMOS is increased, or the manufacturing cost of the process is increased.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide an optimized method for manufacturing a lateral double-diffused transistor, in which an opening is formed by etching a first hard mask, a drift region is formed through the opening, the mask is saved, and a second hard mask is deposited over the first hard mask, so that the thickness of a nitride layer over the drift region is smaller than that of a nitride layer in other regions, the length of a bird's beak is increased, an electric field of a silicon substrate under the bird's beak region is reduced, and the breakdown voltage of the transistor is effectively increased while the process cost is saved.
According to the present invention, there is provided a method of manufacturing a lateral double diffused transistor, comprising:
sequentially depositing a pad oxide layer and a first hard mask on the surface of a substrate, wherein the substrate is provided with a P-type well region and an N-type well region which are separated from each other;
forming an N-type drift region in the substrate through an opening of a first hard mask, the N-type drift region being spaced apart from and abutting the P-type well region;
depositing a second hard mask on the first hard mask and the surface of the pad oxide layer; and
a field oxide layer is formed over the N-type drift region through an opening of a second hard mask.
Optionally, the first hard mask and the second hard mask are respectively formed by the following steps:
forming a nitride layer;
forming a resist mask on the nitride layer; and
the nitride layer is etched through the resist mask to form an opening.
Optionally, the resist mask used by the first hard mask when forming the opening is an N-type drift region mask, and the resist mask used by the second hard mask when forming the opening is an active region mask.
Optionally, forming a field oxide layer over the N-type drift region via the opening of the second hard mask, comprising the steps of:
etching a part of the second hard mask positioned above the N-type drift region to expose a part of the surface of the pad oxide layer; and
growing a field oxide layer on the exposed region of the pad oxide layer.
Optionally, after forming the opening of the second hard mask, a thickness of all nitride layers above the drift region is less than a thickness of all nitride layers above the P-type well region.
Optionally, the second hard mask over the P-type well region that is not etched away covers a surface of the first hard mask and a surface of a portion of the pad oxide layer.
Optionally, the thickness of the second hard mask is less than the thickness of the first hard mask.
Optionally, after forming a field oxide layer over the N-type drift region through the opening of the second hard mask, the method further includes:
etching to remove the second hard mask, the first hard mask and the pad oxide layer;
forming a gate oxide layer adjacent to the bird's beak region of the field oxide layer; and
and depositing a field plate layer above the gate oxide layer, etching to form a gate, and injecting a source electrode and a drain electrode.
Optionally, the field plate layer sequentially covers the gate oxide layer and a part of the field oxide layer.
Optionally, the field plate layer comprises a polysilicon layer.
Optionally, the first and second hard masks are grown using chemical vapor deposition.
According to the manufacturing method of the transverse double-diffusion transistor, the first hard mask is etched to form the opening, the drift region is formed through the opening, and the opening of the first hard mask is formed while the drift region is manufactured, so that the mask is saved, the process steps are simplified, and the process cost is saved; and deposit the second hard mask above the first hard mask, so that the thickness of the nitride layer above the drift region is smaller than the thickness of the nitride layer in other areas, thus make the bird's beak length of the drift region increase, introduce a area of thickness gradual transition between gate oxide and field oxide equivalently, thus reduce the electric field of the silicon substrate under the bird's beak area, thus promote the breakdown voltage of the transistor effectively, because adopt the drift region mask to do the corrasion of the barrier layer to carry on the first hard mask at the same time, does not need to use the separate mask, has simplified the difficulty of the process, has saved the process cost.
Preferably, the thickness of the second hard mask is smaller than that of the first hard mask, so that the thickness of the nitride layer above the drift region is further ensured to be smaller than that of the nitride layer above the P-type well region, the bird's beak length of the drift region is increased, a thickness transition region is formed between the field oxide layer and the gate oxide layer instead of the bird's beak with the instantaneously reduced thickness, the electric field of the silicon substrate below the bird's beak region is greatly reduced, and therefore the breakdown voltage of the transistor is effectively improved and the on-resistance is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic cross-sectional structure of a prior art lateral double diffused transistor;
FIGS. 2a-2e show schematic cross-sectional views of stages in a method of fabricating a conventional lateral double diffused transistor;
fig. 3 shows a flow chart of a method of manufacturing a lateral double diffused transistor according to an embodiment of the invention;
fig. 4a to 4j show schematic cross-sectional views of stages of a method of manufacturing a lateral double diffused transistor according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
Unless otherwise specified below, various layers or regions of a semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge. The gate conductor, electrode layer may be formed of various materials that are electrically conductive, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other electrically conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" refers to extending in a direction substantially perpendicular to the depth direction of the trench.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 2a-2e show schematic cross-sectional views of various stages of a method of manufacturing a conventional lateral double diffused transistor, which is described below in connection with fig. 2a-2 e.
As shown in fig. 2a, which is a schematic cross-sectional view of a certain stage of a manufacturing method of a conventional LDMOS device, first, a P-type well region 202, an N-type well region 203 and an N-type drift region 204 are formed in an N-type doped semiconductor substrate, such as a silicon substrate 201, on the top of the substrate 201, and on the side of the P-type well region 202, the N-type drift region 204 and the P-type well region 202 are separated from each other. A well mask is required for forming P-type well region 202 and N-type well region 203, and a drift region mask is also required for forming N-type drift region 204, which are necessary steps in the fabrication process and will not be described in detail here.
Then, a pad oxide layer 212 is deposited on the surface of the silicon substrate 201, a first mask 221 is placed on the pad oxide layer 212 above the drift region 204, and the pad oxide layer 212 is etched by using the mask 221 to remove the pad oxide layer 212 above the two well regions.
Further, as shown in fig. 2b, the mask 221 is removed, and a second pad oxide layer 211 is deposited on the surface of the substrate 201, the pad oxide layer 211 covers the pad oxide layer 212, and a hard mask 213 is deposited on the surface of the pad oxide layer 211. The pad oxide layer 212 and the pad oxide layer 211 are made of the same material, such as silicon oxide, and the hard mask 213 is made of silicon nitride. A second layer of mask, active area mask 222, is then placed over pad oxide layer 211 over P-type well region 202 and N-type well region 203, active area mask 222 exposing hard mask 213 over N-type drift region 204. The hard mask 213 is then etched using the active area mask 222.
Further, as shown in fig. 2c, which is a cross-sectional view of the hard mask 213 after being etched, the hard mask 213 located above the P-well 202 extends from the P-well 202 to the drift region 204, covering a portion of the pad oxide layer 212, and the hard mask 213 located above the N-well 203 only covers the pad oxide layer 211.
Further, as shown in fig. 2d, the pad oxide layers 211 and 212 above the N-type drift region 204, which are not covered by the hard mask 213, react under certain conditions to form a field oxide layer 231, and two ends of the field oxide layer 231 form bird's beak regions. The bird's beak region of the field oxide layer 231 near the end of the P-well 202 abuts the pad oxide layer 212 due to the presence of the pad oxide layer 212, and then contacts the pad oxide layer 211. The thickness of pad oxide layer 212 is greater than the thickness of pad oxide layer 211, such that an increasing thickness of oxide layer is formed gradually from P-well region 202 to drift region 204.
Further, as shown in fig. 2e, the hard mask 213 and the pad oxide layer 211 are removed by etching, and only the field oxide layer 231 and the pad oxide layer 212 adjacent thereto remain. Oxide is then deposited over the P-well 202 to form a gate oxide 241. A polysilicon layer is then deposited over the gate oxide 241 to form a field plate 251 and a gate, and finally ion implantation is performed to form source and drain regions in the P-well region 202 and the N-well region 203, respectively. The source region and the drain region are both N-type doped regions.
In the transistor, a liner oxide layer 212 is added between a gate oxide layer 241 and a bird's beak of a field oxide layer 231, so that a step-shaped oxide layer is formed from a P-type well region 202 to an N-type drift region 204, the thickness of the oxide layer at the star point in fig. 2e is increased, and an electric field at the star point is reduced, so that the breakdown voltage is greatly improved. Since the present invention improves the conventional method for manufacturing the LDMOS device, the LDMOS device structure is manufactured through the process steps shown in fig. 3 and fig. 4a to fig. 4j to further improve the characteristics of the transistor, reduce the on-state voltage drop, and improve the breakdown voltage.
Fig. 3 shows a flow chart of a method of manufacturing a lateral double diffused transistor according to an embodiment of the invention; fig. 4a to 4j show schematic cross-sectional views of stages of a method of manufacturing a lateral double diffused transistor according to an embodiment of the invention.
The following describes a process flow of manufacturing the LDMOS device according to the embodiment of the present application with reference to fig. 3 to fig. 4 j.
As shown in fig. 3, in step S101, a pad oxide layer and a first hard mask are sequentially deposited on a substrate surface formed with a P-type well region and an N-type well region spaced apart from each other.
As shown in fig. 4a, a P-type well region 402 and an N-type well region 403 isolated from P-type well region 402 are formed inside a semiconductor substrate 401. This step is accomplished using conventional techniques. A pad oxide layer 411 is then deposited on the surface of the substrate 401, the substrate 401 being, for example, a silicon substrate, and the pad oxide layer 411 being, for example, silicon oxide.
Next, as shown in fig. 4b, a first hard mask 413 is deposited on the surface of the pad oxide layer 411, and then a resist mask 421 is disposed on the first hard mask 413 above the P-type well region 402, wherein the resist mask 421 is used for forming an N-type drift region, which is a mask required in the conventional process steps.
In step S102, an N-type drift region is formed in the substrate through the opening of the first hard mask, the N-type drift region being spaced apart from and adjacent to the P-type well region.
In one embodiment, the first hard mask 413 is a nitride, such as silicon nitride, and the first hard mask 413 is formed by: forming a nitride layer; forming a resist mask on the nitride layer; and etching the nitride layer through the resist mask to form an opening.
Specifically, as shown in fig. 4b, a resist mask 421 is disposed over the first hard mask 413 over the P-type well region 402, the resist mask 421 being for forming an N-type drift region, preferably, the resist mask 421 being a drift region mask.
As shown in fig. 4c, the first hard mask 413 is etched using the resist mask 421 as a barrier layer, and an N-type drift region is implanted to form an N-type drift region 404 located at a side of the P-type well region 402. The first hard mask 413 above the N-type drift region 404 is etched away using the resist mask 421 as a barrier layer to expose the pad oxide layer 411, and then ion implantation is performed to form the N-type drift region 404.
In step S103, a second hard mask is deposited on the first hard mask and the surface of the pad oxide layer.
Next, as shown in fig. 4d, a second nitride layer, i.e., a second hard mask 414, is deposited on the remaining surfaces of the first hard mask 413 and the pad oxide layer 411, and at this time, the second hard mask 414 covers the first hard mask 413 and the pad oxide layer 411.
Preferably, first hard mask 413 and second hard mask 414 are both nitride layers, such as silicon nitride, and in one embodiment, first hard mask 413 and second hard mask 414 are deposited using chemical vapor deposition.
In this step, the first hard mask 413 is etched using the resist mask 421 as a barrier layer to define the deposition area of the second hard mask 212, thereby forming a distribution of nitride layers with decreasing thickness from the P-well region 402 to the N-drift region 404. Compared with the traditional process in which a single mask 221 is used for etching the second pad oxide layer 212, the method saves one mask, simplifies the process steps and saves the process cost.
In step S104, a field oxide layer is formed over the N-type drift region through the opening of the second hard mask.
Specifically, as shown in fig. 4e, a resist mask 422 is disposed over the second hard mask 414, the resist mask 422 is an active area mask, and the second hard mask 414 is block-etched using the resist mask 422 to form an opening. The active area mask, when located over the second hard mask 414, exposes the second hard mask 414 over the N-type drift region 404.
In this step, the formation process of the second hard mask 414 is the same as the formation process of the first hard mask 413, and both include the following steps: forming a nitride layer; forming a resist mask on the nitride layer; and etching the nitride layer through the resist mask to form an opening.
Further, a field oxide layer 431 is formed over the N-type drift region 404 through the opening of the second hard mask 414, including the steps of:
in step one, a portion of the second hard mask 414 above the N-type drift region 404 is etched to expose a portion of the surface of the pad oxide layer 411. As shown in fig. 4f, the second hard mask 414 is etched such that the second hard mask 414 over the N-type drift region 404 is etched away, exposing the underlying pad oxide layer 411.
In this step, it is necessary to ensure that after etching second hard mask 414, the thickness of all nitride layers above N-type drift region 404 is less than the thickness of all nitride layers above P-type well region 402.
In one embodiment, the second hard mask 414 over the P-well region 402, which is not etched away, covers the surface of the first hard mask 413 and a portion of the pad oxide layer 411, such that the P-well region has a greater thickness of nitride layer over the P-well region 402 than over the N-drift region 404.
In another embodiment, the thickness of the second hard mask 414 is less than the thickness of the first hard mask 413, such that even if the second hard mask 414 does not cover the first hard mask 413, the thickness of the nitride layer on the N-type drift region 404 is less than the thickness of the nitride layer above the P-type well region 402 because the thickness of the second hard mask 414 is less than the thickness of the first hard mask 413.
In step two, a field oxide layer is grown on the exposed region of the pad oxide layer 411. As shown in fig. 4f, the pad oxide 411 not covered by the second hard mask 414 reacts under certain conditions to form a field oxide 431, e.g., at high temperature, reflecting the formation of silicon dioxide.
As shown in fig. 4g, the field oxide layer 431 forms a bird's beak region at the contact edge of the second hard mask 414 and the pad oxide layer 411, and the thickness of the second hard mask 414 above the N-type drift region 404 is thinner, and the thickness of the nitride layer above the N-type drift region 404 is smaller than that of the nitride layer in other regions, so the length of the bird's beak above the N-type drift region 404 is longer, and the length of the bird's beak is similar to that of the conventional process because the nitride layer in other regions is of normal thickness. Thereby increasing the length of the bird's beak region of the field oxide 431 and thus forming a thickness transition region before the pad oxide 411 and the field oxide 431 to reduce the electric field under the bird's beak region. Due to the presence of the field oxide layer 431, the edge of the second hard mask 414 contacting the pad oxide layer 411 is tilted up to conform to the shape of the bird's beak region.
Further, in the present embodiment, the thickness of the second hard mask 413 above the N-type drift region 404 is smaller than the thickness of the second hard mask 213 above the N-type drift region 204 in the conventional transistor shown in fig. 2d, so the length of the bird's beak in the bird's beak region formed in the present embodiment is larger than the length of the bird's beak formed in the conventional process, so that equivalently, a thickness transition region is introduced, the bird's beak is no longer in a momentarily reduced structure, the electric field below the bird's beak region is reduced, and the breakdown voltage is increased.
In one embodiment, the method for manufacturing the LDMOS device of the present invention further includes steps S105 to S107. The description is developed below.
In step S105, the second hard mask, the first hard mask, and the pad oxide layer are etched away.
Next, as shown in fig. 4h, the second hard mask 414, the first hard mask 413 and the exposed pad oxide layer 411 are removed by etching, and a gate oxide layer is subsequently formed at the position of the pad oxide layer 411 above the P-well region 202. After the etching, only the field oxide layer 431 remains.
In step S107, a gate oxide layer is formed adjacent to the bird' S beak region of the field oxide layer.
Further, as shown in fig. 4i, a gate oxide layer 441 is grown. A gate oxide layer 441 is grown on the silicon substrate 401 around the field oxide layer 431 by a certain deposition process, and the gate oxide layer 441 covers the channel, i.e., covers part of the surfaces of the well region 402 and part of the N-type drift region 404. The gate oxide layer 441 is, for example, silicon dioxide, and serves as a gate insulating layer of a transistor.
In step S108, a field plate layer is deposited on the gate oxide layer, and then a gate is formed by etching, and source and drain implants are performed.
As shown in fig. 4j, a field plate layer 451 is deposited over the gate oxide layer 441 and then etched to remove unwanted portions so that the remaining field plate layer 451 sequentially covers the gate oxide layer 441 and the field oxide layer 431. The field plate layer 451 includes, for example, a polysilicon layer, thereby forming a gate electrode. Then, N-type ions are implanted into the P-type well region 402 and the N-type well region 403 to form a source region and a drain region, respectively. Thereby completing the preparation of the LDMOS as shown in fig. 4 j.
In the transistor, because a bird's beak with a long length is formed between the gate oxide 441 and the field oxide 431, which is equivalent to an oxide region with a transitional thickness, the electric field at the star mark is reduced, and the breakdown voltage is improved. In the preparation process, the drift region mask is used as the blocking layer to change the thickness of the nitride layer at each position on the substrate 401, so that one mask is saved, the process steps are simplified, and the breakdown voltage of the transistor is improved under the condition of not increasing the process cost.
In the present invention, the NLDMOS (N-type drift region is an N-type semiconductor) is described as an example, but the manufacturing method is also applicable to the PLDMOS. But also can be applied to other field oxide layer preparation processes.
In summary, according to the manufacturing method of the lateral double-diffused transistor in the embodiment of the invention, the first hard mask is etched to form the opening, the N-type drift region is formed through the opening, and the opening of the first hard mask is formed while the N-type drift region is manufactured, so that the mask is saved, the process steps are simplified, and the process cost is saved; and deposit the second hard mask above the first hard mask, so that the thickness of the nitride layer above the drift region of N type is smaller than the thickness of the nitride layer of other areas, thus make the bird's beak length of the drift region of N type increase, introduce a area of thickness transition gradually between gate oxide and field oxide equivalently, thus reduce the electric field of the silicon substrate under the bird's beak area, thus promote the breakdown voltage of the transistor effectively, because adopt the drift region mask of N type to do the corrasion of the first hard mask as the barrier layer at the same time, does not need to use the separate mask, has simplified the difficulty of the process, has saved the process cost.
Furthermore, the thickness of the second hard mask is smaller than that of the first hard mask, so that the thickness of the nitride layer above the N-type drift region is further ensured to be smaller than that of the nitride layer on the P-type well region, the length of the bird's beak of the N-type drift region is increased, a thickness transition region is formed between the field oxide layer and the gate oxide layer instead of the bird's beak with the instantaneously reduced thickness, the electric field of the silicon substrate below the bird's beak region is greatly reduced, and the breakdown voltage of the transistor is effectively improved and the on-resistance is reduced.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A method of fabricating a lateral double diffused transistor, comprising:
sequentially depositing a pad oxide layer and a first hard mask on the surface of a substrate, wherein the substrate is provided with a P-type well region and an N-type well region which are separated from each other;
forming an N-type drift region in the substrate through an opening of a first hard mask, the N-type drift region being spaced apart from and abutting the P-type well region;
depositing a second hard mask on the first hard mask and the surface of the pad oxide layer; and
a field oxide layer is formed over the N-type drift region through an opening of a second hard mask.
2. The method of manufacturing a lateral double diffused transistor according to claim 1, wherein the first hard mask and the second hard mask are formed by using the following steps, respectively:
forming a nitride layer;
forming a resist mask on the nitride layer; and
the nitride layer is etched through the resist mask to form an opening.
3. The method of manufacturing a lateral double diffused transistor according to claim 2, wherein the resist mask used in forming the opening of the first hard mask is an N-type drift region mask, and the resist mask used in forming the opening of the second hard mask is an active region mask.
4. The method of claim 1, wherein forming a field oxide layer over the N-type drift region via the opening of the second hard mask comprises:
etching a part of the second hard mask positioned above the N-type drift region to expose a part of the surface of the pad oxide layer; and
growing a field oxide layer on the exposed region of the pad oxide layer.
5. The method of claim 4, wherein a thickness of all nitride layers above the drift region is less than a thickness of all nitride layers above the P-type well region after forming the opening of the second hard mask.
6. The method of claim 5, wherein the second hard mask over the P-well region that is not etched away covers a surface of the first hard mask and a portion of a surface of the pad oxide layer.
7. The method of claim 5, wherein a thickness of the second hard mask is less than a thickness of the first hard mask.
8. The method of claim 1, wherein the opening through the second hard mask is followed by forming a field oxide layer over the N-type drift region, further comprising:
etching to remove the second hard mask, the first hard mask and the pad oxide layer;
forming a gate oxide layer adjacent to the bird's beak region of the field oxide layer; and
and depositing a field plate layer above the gate oxide layer, etching to form a gate, and injecting a source electrode and a drain electrode.
9. The method of claim 8, wherein the field plate layer sequentially covers the gate oxide layer and a portion of the field oxide layer.
10. The method of fabricating a lateral double diffused transistor according to claim 8 wherein the field plate layer comprises a layer of polysilicon.
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| CN111710719A (en) * | 2020-06-23 | 2020-09-25 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
| CN114823482A (en) * | 2022-06-20 | 2022-07-29 | 北京芯可鉴科技有限公司 | Method for preparing lateral diffusion metal oxide semiconductor and device |
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