CN114461142B - Method, system, device and medium for reading and writing Flash data - Google Patents
Method, system, device and medium for reading and writing Flash data Download PDFInfo
- Publication number
- CN114461142B CN114461142B CN202210017456.3A CN202210017456A CN114461142B CN 114461142 B CN114461142 B CN 114461142B CN 202210017456 A CN202210017456 A CN 202210017456A CN 114461142 B CN114461142 B CN 114461142B
- Authority
- CN
- China
- Prior art keywords
- data
- main control
- flash memory
- control chip
- cpld
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 59
- 230000001360 synchronised effect Effects 0.000 claims abstract description 31
- 238000004590 computer program Methods 0.000 claims description 12
- 238000012806 monitoring device Methods 0.000 abstract description 7
- 238000012544 monitoring process Methods 0.000 abstract description 6
- 238000004891 communication Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 230000009471 action Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 3
- 238000013473 artificial intelligence Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000009877 rendering Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
The CPLD is connected with the main control chip and the Flash memory respectively, the CPLD receives the data transmitted by the Flash memory and transmits the data to the main control chip, the CPLD is used as a monitoring device when the main control chip reads and writes the data in the Flash memory, whether the main control chip is synchronous with the data in the Flash memory or not is judged, if the main control chip is not synchronous with the data in the Flash memory, a reset signal is transmitted to the main control chip and the Flash memory by the CPLD at the same time, and the CPLD realizes the monitoring when the main control chip reads and writes the data in the Flash memory.
Description
Technical Field
The present invention relates to the field of data reading technologies, and in particular, to a method, a system, an apparatus, and a medium for reading and writing Flash data.
Background
Servers are an important component of information infrastructure and play an increasingly important role in the rapidly growing information society. The design of the server is generally provided with a Flash memory for storing an operating program, and when the system is started, the main control chip loads the program in the Flash memory, so that the configuration of the system and the like are correctly carried out, and the normal operation of the server is ensured. In the prior art, a main control chip is directly connected with a Flash memory, and when a system is started, the main control chip directly starts to read data in the Flash memory, and after reading is completed, the data is loaded into an internal register to configure the register, and a program is run.
The process of the main control chip for reading the data in the Flash memory is uncontrolled, if loading failure occurs in the data loading process, effective positioning analysis cannot be performed, the Flash memory cannot follow system reset together in the hardware circuit design of the Flash memory, and conflict that the address mode of the main control chip is inconsistent with the address mode of the Flash memory after reset exists, so that the data in the Flash memory is damaged and erased.
Therefore, how to strengthen the monitoring of the main control chip to read and write the Flash memory is a technical problem to be solved urgently by the person skilled in the art.
Disclosure of Invention
The application aims to provide a method, a system, a device and a medium for reading and writing Flash data.
In order to solve the technical problems, the application provides a Flash data read-write method which is applied to a CPLD, wherein the CPLD is respectively connected with a main control chip and a Flash memory, and the method comprises the following steps:
receiving data sent by the Flash memory;
the data are sent to the main control chip and stored to a UFM register of the CPLD;
judging whether the main control chip is synchronous with data in the Flash memory or not;
if not, a reset signal is sent to the main control chip and the Flash memory, and the reset signal is used for controlling the main control chip and the Flash memory to be reset at the same time.
Preferably, in the Flash data read-write method, after storing the data in the UFM register, the method further includes:
and when the main control chip is restarted or the data loading fails, a reset signal is sent to the main control chip and the Flash memory.
Preferably, in the Flash data read-write method, after storing the data in the UFM register, the method further includes:
and when receiving a signal that the data in the Flash memory and the data in the UFM register sent by the BMC are inconsistent, sending a reset signal to the main control chip and the Flash memory.
Preferably, in the Flash data read-write method, after the data is sent to the main control chip, the method further includes:
and when the main control chip fails to read the data, storing the current data.
The application also provides a Flash data read-write system, which comprises:
the host chip, CPLD, flash memory;
the CPLD comprises a UFM register;
the main control chip is connected with the CPLD, the CPLD is connected with the Flash memory,
the CPLD is used for receiving the data sent by the Flash memory, sending the data to the main control chip and storing the data to the UFM register; the CPLD is also used for sending a reset signal to the main control chip and the Flash memory when the main control chip and the data in the Flash memory are not synchronous, and the reset signal is used for controlling the main control chip and the Flash memory to be reset at the same time.
Preferably, in the Flash data read-write system, the method further includes: BMC;
and the BMC is connected with the CPLD and the Flash memory and is used for checking whether the data in the Flash memory and the data in the UFM register are consistent.
Preferably, in the Flash data read-write system, the main control chip is connected with the CPLD through an SPI bus, the CPLD is connected with the Flash memory through the SPI bus, and the CPLD is connected with the BMC through an IIC bus.
The application also provides a Flash data read-write device, which is applied to the CPLD, wherein the CPLD is respectively connected with the main control chip and the Flash memory, and the device comprises:
the receiving module is used for receiving the data sent by the Flash memory;
the storage module is used for sending the data to the main control chip and storing the data to a UFM register of the CPLD;
the judging module is used for judging whether the main control chip is synchronous with the data in the Flash memory or not; if not, triggering a reset module.
The reset module is used for sending a reset signal to the main control chip and the Flash memory, and the reset signal is used for controlling the main control chip and the Flash memory to be reset at the same time.
And the sending module is used for sending a reset signal to the main control chip and the Flash memory when the main control chip is restarted or the data loading fails.
And the receiving control module is used for sending a reset signal to the main control chip and the Flash memory when receiving a signal which is sent by the BMC and is inconsistent with the data in the UFM register.
And the error storage module is used for storing the current data when the main control chip fails to read the data.
The application also provides a Flash data read-write device, which comprises:
a memory for storing a computer program;
and the processor is used for realizing the steps of the Flash data read-write method when executing the computer program.
The present application also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the Flash data read-write method as described.
The Flash data read-write method is applied to a complex programmable logic device (Complex Programmable Logic Device) CPLD, wherein the CPLD is respectively connected with a main control chip and a Flash memory, and the CPLD receives data sent by the Flash memory, then sends the data to the main control chip and stores the data to a UFM register of the CPLD; the CPLD judges whether the main control chip is synchronous with the data in the Flash memory; if not, sending a reset signal to the main control chip and the Flash memory. The CPLD is used as a monitoring device when the main control chip reads and writes the data in the Flash memory, judges whether the main control chip is synchronous with the data in the Flash memory, and if the main control chip is not synchronous with the data in the Flash memory, the CPLD simultaneously sends a reset signal to the main control chip and the Flash memory, and the CPLD monitors the Flash memory when the main control chip reads and writes the data.
In addition, the application also provides a Flash data read-write system, a device and a computer readable storage medium, which correspond to the method and have the same effects.
Drawings
For a clearer description of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a Flash data read-write method provided in an embodiment of the present application;
FIG. 2 is a block diagram of a Flash data read-write system according to an embodiment of the present application;
fig. 3 is a structural diagram of a Flash data read-write device provided in an embodiment of the present application;
fig. 4 is a block diagram of a Flash data read-write device according to another embodiment of the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments herein without making any inventive effort are intended to fall within the scope of the present application.
The core of the application is to provide a method for enhancing the monitoring and management of data read-write in a Flash memory.
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description.
Fig. 1 is a flowchart of a Flash data read-write method provided in an embodiment of the present application, applied to a CPLD22, where the CPLD22 is respectively connected to a main control chip 21 and a Flash memory 24, as shown in fig. 1, the Flash data read-write method includes:
s10: receiving data sent by the Flash memory 24;
s11: the UFM register 23 that sends data to the main control chip 21 and stores data to the CPLD 22;
s12: judging whether the main control chip 21 and the data in the Flash memory 24 are synchronous or not;
s13: if not, a reset signal is sent to the main control chip 21 and the Flash memory 24, and the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to be reset at the same time.
The CPLD22 referred to in this embodiment is a complex programmable logic device, which is composed of a fully programmable and/or array and a macrocell library. The AND/OR array is reprogrammable AND capable of performing numerous logic functions. Macro cells are functional blocks that perform combinational or sequential logic while also providing greater flexibility in true or complement output and feedback in different paths. In addition, CPLD22 includes a user memory space (User Flash Memory, UFM), and the data stored in UFM register 23 remains after CPLD22 is powered down and cannot be emptied.
The Flash memory 24 is also called Flash memory, not only has the performance of electronic erasable and programmable, but also can not lose data due to power failure, and can quickly read data, and is used for storing BIOS programs, BMC25 programs and the like on a server. The main control chip 21 of the server reads the data stored in the Flash memory 24, and loads the data into an internal register after reading, configures the register and runs a program. In the process of reading data by the main control chip 21, if the main control chip 21 fails to read or the main control chip 21 is suddenly powered off, the main control chip 21 will be powered on again, but the Flash memory 24 will not reset along with the main control chip 21, so that the data between the main control chip 21 and the Flash memory 24 will not be synchronized.
The CPLD22 mentioned in step S10 receives the data sent by the Flash memory 24, and step S11 sends the data to the main control chip 21, so that the main control chip 21 can read and load the data, in this process, the CPLD22 only serves as an intermediary in the process of reading the data of the Flash memory 24 by the main control chip 21, and the CPLD22 is serially connected to the connection line between the main control chip 21 and the Flash memory 24. In step S11, the CPLD22 stores data in the UFM register 23 of the CPLD22, or may be regarded as that when the main control chip 21 reads data in the Flash memory 24, the CPLD22 reads data on the communication bus between the main control chip 21 and the Flash memory 24, and stores the data in the UFM register 23. In addition, data is stored in the UFM register 23, and when the main control chip 21 fails to read the data, the reason of the loading failure of the main control chip 21 can be analyzed by loading the data stored in the CPLD22, so as to solve the error.
Step S12 determines whether the data in the main control chip 21 and the data in the Flash memory 24 are synchronous, including determining whether the clock status and the address status of the data in the main control chip 21 and the data in the Flash memory 24 are synchronous, and if the data in the main control chip 21 and the data in the Flash memory 24 are not synchronous, the memory stored in the Flash memory 24 may be damaged because the main control chip 21 and the Flash memory 24 operate in different address modes. Through step S12, it is determined whether the data in the main control chip 21 and the Flash memory 24 are synchronous, if not, step S13 sends a reset signal to the main control chip 21 and the Flash memory 24, where the reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously, and the main control chip 21 and the Flash memory 24 perform a reset operation simultaneously, so that the main control chip 21 and the Flash memory 24 operate in the same address mode, and the problem that the content of the Flash memory 24 is damaged is avoided.
In addition, the connection mode of the main control chip 21 and the CPLD22 is not limited, and the connection mode of the CPLD22 and the Flash memory 24 is not limited, so that the device is designed according to actual needs; in addition, the specific type of the main control chip 21, for example CPU, MCU, PCH, MCH, is not limited in this embodiment.
By the method provided by the embodiment, the CPLD22 is serially arranged between the main control chip 21 and the Flash storage, the CPLD22 receives the data sent by the Flash storage 24, then sends the data to the main control chip 21, and stores the data to the UFM register 23 of the CPLD 22; the CPLD22 judges whether the main control chip 21 and the data in the Flash memory 24 are synchronous or not; if not, a reset signal is sent to the main control chip 21 and the Flash memory 24. The CPLD22 is used as a monitoring device when the main control chip 21 reads and writes data in the Flash memory 24, and judges whether the main control chip 21 and the data in the Flash memory 24 are synchronous, if the main control chip 21 and the data in the Flash memory 24 are not synchronous, the CPLD22 simultaneously sends a reset signal to the main control chip 21 and the Flash memory 24, so that the data in the main control chip 21 and the Flash memory 24 are synchronous, and the CPLD22 monitors the read and write operations of the main control chip 21 on the Flash memory 24.
According to the above embodiment, when the main control chip 21 is restarted due to power failure or other reasons, the main control chip 21 is likely to be out of synchronization with the data in the Flash memory 24, so the present embodiment provides a preferred scheme, and after storing the data in the UFM register 23 in step S11, the method further includes: when the main control chip 21 is restarted or fails to load data, a reset signal is sent to the main control chip 21 and the Flash memory 24.
When the CPLD22 detects that the main control chip 21 is powered down and restarted or fails to load data, a reset signal is directly sent to the main control chip 21 and the Flash memory 24, the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to reset simultaneously, and the main control chip 21 and the Flash memory 24 perform reset actions simultaneously, so that the main control chip 21 and the Flash memory 24 are ensured to work in the same address mode, and the problem that the content of the Flash memory 24 is damaged is solved.
By the method provided by the embodiment, when the main control chip 21 is restarted or data loading fails, a reset signal is sent to the main control chip 21 and the Flash memory 24, and the CPLD22 simultaneously sends the reset signal to the main control chip 21 and the Flash memory 24, so that the data synchronization in the main control chip 21 and the Flash memory 24 is ensured, and the CPLD22 monitors the Flash memory 24 during the read-write operation of the main control chip 21.
According to the above embodiment, in order to ensure that the CPLD22 reads the data from the Flash memory 24 accurately, this embodiment provides a preferred scheme, and after storing the data into the UFM register 23 in step S11, the method further includes: when receiving a signal that the data in the Flash memory 24 and the UFM register 23 sent by the baseboard management controller (Baseboard Management Controller, BMC 25) are inconsistent, a reset signal is sent to the main control chip 21 and the Flash memory 24.
The baseboard management controller BMC25 mentioned in this embodiment is connected to the CPLD22 and the Flash memory 24, and is used to monitor whether the data information stored in the CPLD22 is consistent with the data in the Flash memory 24, and to check the accuracy of the data, and a worker can analyze the problem existing in the data communication between the main control chip 21 and the Flash memory 24 by reading the checking result of the BMC 25. When BMC25 detects that the data stored in UFM register 23 of CPLD22 is inconsistent with the data in Flash memory 24, BMC25 transmits signals to CPLD22, CPLD22 transmits reset signals to main control chip 21 and Flash memory 24, thus ensuring the data synchronization of main control chip 21 and Flash memory 24, and CPLD22 realizes the monitoring of main control chip 21 in reading and writing operation of Flash memory 24.
By the method provided by the embodiment, the BMC25 participates in data read-write verification, so that the safety and reliability of data are improved, and the overall reliability of the system is further improved.
According to the above embodiment, when the main control chip 21 reads the data in the Flash memory 24, the main control chip 21 may fail to read, so as to analyze the reason of the failure of the main control chip 21 to read the data, and in order to solve the problem, the embodiment provides a preferred scheme, and after step S11 sends the data to the main control chip 21, the method further includes:
when the main control chip 21 fails to read data, the current data is stored.
When the main control chip 21 fails to read the data, the main control chip 21 can lose the data, the CPLD22 is provided for storing the data, and a worker can analyze the reason of the failure of reading by checking the type of the data so as to solve the problem.
The embodiment of the application also provides a Flash data read-write system, and fig. 2 is a structural diagram of the Flash data read-write system provided in the embodiment of the application, as shown in fig. 2, including:
a main control chip 21, a CPLD22 and a flash memory 24;
CPLD22 contains UFM register 23;
the main control chip 21 is connected with the CPLD22, the CPLD22 is connected with the Flash memory 24,
the CPLD22 is configured to receive data sent by the Flash memory 24, send the data to the main control chip 21, and store the data to the UFM register 23; the CPLD22 is further configured to send a reset signal to the main control chip 21 and the Flash memory 24 when the main control chip 21 is not synchronized with the data in the Flash memory 24, where the reset signal is used to control the main control chip 21 and the Flash memory 24 to perform a reset at the same time.
The CPLD22 stores data into the UFM register 23 of the CPLD22, and may also be regarded as that when the main control chip 21 reads data of the Flash memory 24, the CPLD22 reads data on the communication bus of the main control chip 21 and the Flash memory 24, and stores the data into the UFM register 23. In addition, data is stored in the UFM register 23, and when the main control chip 21 fails to read the data, the reason of the loading failure of the main control chip 21 can be analyzed by loading the data stored in the CPLD22, so as to solve the error.
When the data in the main control chip 21 and the data in the Flash memory 24 are not synchronous, the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24, wherein the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to reset simultaneously, and the main control chip 21 and the Flash memory 24 perform reset simultaneously, so that the main control chip 21 and the Flash memory 24 work in the same address mode, and the problem that the content of the Flash memory 24 is damaged is solved.
Through the Flash data read-write system provided by the embodiment, the CPLD22 is serially arranged between the main control chip 21 and the Flash memory, and after receiving the data sent by the Flash memory 24, the CPLD22 sends the data to the main control chip 21 and stores the data to the UFM register 23 of the CPLD 22; when the data in the main control chip 21 and the data in the Flash memory 24 are not synchronous, the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24, the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to be reset simultaneously, the CPLD22 is used as a monitoring device when the main control chip 21 reads and writes the data in the Flash memory 24, the data in the main control chip 21 and the data in the Flash memory 24 are ensured to be synchronous, and the CPLD22 monitors when the main control chip 21 reads and writes the data in the Flash memory 24.
According to the above embodiment, the present application further provides a preferred solution, a Flash data read-write system, further including: BMC25;
the BMC25 is connected with the CPLD22 and the Flash memory 24, and the BMC25 is used for checking whether the data in the Flash memory 24 and the data in the UFM register 23 are consistent.
The baseboard management controller BMC25 is connected with the CPLD22 and the Flash memory 24, and is used for monitoring whether the data information stored in the CPLD22 is consistent with the data in the Flash memory 24, checking the accuracy of the data, and a worker can analyze the problem of data communication between the main control chip 21 and the Flash memory 24 by reading the checking result of the BMC 25. When BMC25 detects that the data stored in UFM register 23 of CPLD22 is inconsistent with the data in Flash memory 24, BMC25 transmits signals to CPLD22, CPLD22 transmits reset signals to main control chip 21 and Flash memory 24, thus ensuring the data synchronization of main control chip 21 and Flash memory 24, and CPLD22 realizes the monitoring of main control chip 21 in reading and writing operation of Flash memory 24.
According to the above embodiment, the present application further provides a preferred scheme, namely, a Flash data read-write system, where the main control chip 21 is connected with the CPLD22 through a serial peripheral interface (Serial Peripheral Interface, SPI) bus, the CPLD22 is connected with the Flash memory 24 through the SPI bus, and the CPLD22 is connected with the BMC25 through an integrated circuit bus (Inter-Integrated Circuit, IIC) bus.
It should be noted that the SPI bus is a high-speed, full duplex, synchronous communication bus, supporting full duplex communication, simple communication, and a data transfer rate block. The IIC bus is mainly used for connecting an overall circuit, and IIC is a multi-directional control bus, that is, a plurality of chips can be connected to the same bus structure, and each chip can be used as a control source for real-time data transmission. This approach simplifies the signaling bus interface.
Communication connection between the CPLD22 and the main control chip 21 and Flash memory 24 is realized through an SPI bus, so that the communication is simple, and the data transmission rate is high; the communication connection between the CPLD22 and the BMC25 is realized through the IIC bus, and the device has the advantages of simple structure, low power consumption, strong interference resistance and long transmission distance.
In the above embodiment, the detailed description is given to the Flash data read-write method, and the application also provides a corresponding embodiment of the Flash data read-write device. It should be noted that the present application describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.
Fig. 3 is a structural diagram of a Flash data read-write device provided in an embodiment of the present application, and as shown in fig. 3, the Flash data read-write device includes:
a receiving module 31, configured to receive data sent by the Flash memory 24;
a storage module 32, configured to send data to the main control chip 21 and store the data to the UFM register 23 of the CPLD 22;
the judging module 33 is configured to judge whether the data in the main control chip 21 and the data in the Flash memory 24 are synchronous; if not, the reset module 34 is triggered.
The reset module 34 is configured to send a reset signal to the main control chip 21 and the Flash memory 24, where the reset signal is used to control the main control chip 21 and the Flash memory 24 to perform a reset at the same time.
The Flash data read-write device is applied to the CPLD22, the CPLD22 is respectively connected with the main control chip 21 and the Flash memory 24, the receiving module 31 receives data sent by the Flash memory 24, the storage module 32 sends the data to the main control chip 21 and stores the data to the UFM register 23 of the CPLD22, and the judging module 33 judges whether the data in the main control chip 21 and the Flash memory 24 are synchronous or not; if not, the reset module 34 is triggered, and a reset signal is sent to the main control chip 21 and the Flash memory 24, wherein the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to be reset at the same time.
The CPLD22 is serially arranged between the main control chip 21 and the Flash memory, and is used as a monitoring device when the main control chip 21 reads and writes data in the Flash memory 24, so as to judge whether the main control chip 21 and the data in the Flash memory 24 are synchronous, and if the main control chip 21 and the data in the Flash memory 24 are judged to be asynchronous, the CPLD22 simultaneously sends a reset signal to the main control chip 21 and the Flash memory 24, so that the data synchronization between the main control chip 21 and the Flash memory 24 is ensured, and the CPLD22 monitors the read and write actions of the main control chip 21 on the Flash memory 24.
The apparatus further comprises:
and the sending module is used for sending a reset signal to the main control chip and the Flash memory when the main control chip is restarted or fails to load data.
And the receiving control module is used for sending a reset signal to the main control chip and the Flash memory when receiving a signal that the data in the Flash memory and the UFM register sent by the BMC are inconsistent.
And the error storage module is used for storing the current data when the main control chip fails to read the data.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
Fig. 4 is a structural diagram of a Flash data read-write device according to another embodiment of the present application, as shown in fig. 4, the Flash data read-write device includes: a memory 40 for storing a computer program;
the processor 41 is configured to implement the steps of the Flash data read/write method according to the above embodiment when executing the computer program.
The Flash data read-write device provided by the embodiment can include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer or the like.
Processor 41 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc., among others. The processor 41 may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 41 may also comprise a main processor, which is a processor for processing data in an awake state, also called central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 41 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content required to be displayed by the display screen. In some embodiments, the processor 41 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.
Memory 40 may include one or more computer-readable storage media, which may be non-transitory. Memory 40 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 40 is at least used for storing a computer program 401, where the computer program can implement the relevant steps of the Flash data read/write method disclosed in any of the foregoing embodiments after being loaded and executed by the processor 41. In addition, the resources stored in the memory 40 may further include an operating system 402, data 403, and the like, where the storage manner may be transient storage or permanent storage. Operating system 402 may include, among other things, windows, unix, linux. The data 403 may include, but is not limited to, steps involved in implementing a Flash data read/write method, and the like.
In some embodiments, the Flash data read-write device may further include a display screen 42, an input-output interface 43, a communication interface 44, a power supply 45, and a communication bus 46.
Those skilled in the art will appreciate that the structure shown in fig. 4 does not constitute a limitation of the Flash data read-write device, and may include more or fewer components than shown.
The Flash data read-write device provided by the embodiment of the application comprises a memory and a processor, wherein when the processor executes a program stored in the memory, the processor can realize the following method: the CPLD22 is used as a monitoring device when the main control chip 21 reads and writes data in the Flash memory 24, judges whether the main control chip 21 and the data in the Flash memory 24 are synchronous, and if the main control chip 21 and the data in the Flash memory 24 are judged to be asynchronous, the CPLD22 simultaneously sends a reset signal to the main control chip 21 and the Flash memory 24, so that the data synchronization in the main control chip 21 and the Flash memory 24 is ensured, and the CPLD22 monitors the read and write actions of the main control chip 21 on the Flash memory 24.
Finally, the present application also provides a corresponding embodiment of the computer readable storage medium. The computer readable storage medium stores a computer program which, when executed by a processor, implements the steps described in the Flash data read/write method embodiments.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. With such understanding, the technical solution of the present application, or a part contributing to the prior art or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, performing all or part of the steps of the method described in the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RandomAccess Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The computer readable storage medium provided in this embodiment has a computer program stored thereon, which when executed by a processor, can implement the following method: the CPLD22 is used as a monitoring device when the main control chip 21 reads and writes data in the Flash memory 24, judges whether the main control chip 21 and the data in the Flash memory 24 are synchronous, and if the main control chip 21 and the data in the Flash memory 24 are judged to be asynchronous, the CPLD22 simultaneously sends a reset signal to the main control chip 21 and the Flash memory 24, so that the data synchronization in the main control chip 21 and the Flash memory 24 is ensured, and the CPLD22 monitors the read and write actions of the main control chip 21 on the Flash memory 24.
The Flash data read-write method, the Flash data read-write system, the Flash data read-write device and the Flash data read-write medium provided by the application are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. The Flash data read-write method is characterized by being applied to a CPLD, wherein the CPLD is respectively connected with a main control chip and a Flash memory, and the method comprises the following steps:
receiving data sent by the Flash memory;
the data are sent to the main control chip and stored to a UFM register of the CPLD;
judging whether the main control chip is synchronous with data in the Flash memory or not;
if not, a reset signal is sent to the main control chip and the Flash memory, and the reset signal is used for controlling the main control chip and the Flash memory to be reset at the same time.
2. The Flash data read-write method according to claim 1, wherein after storing the data in the UFM register of the CPLD, further comprising:
and when the main control chip is restarted or the data loading fails, a reset signal is sent to the main control chip and the Flash memory.
3. The Flash data read-write method according to claim 1, wherein after storing the data in the UFM register of the CPLD, further comprising:
when a signal that the data in the Flash memory and the data in the UFM register sent by the BMC are inconsistent is received, a reset signal is sent to the main control chip and the Flash memory;
and the BMC is connected with the CPLD and the Flash memory and is used for checking whether the data in the Flash memory and the data in the UFM register are consistent.
4. The Flash data read-write method according to claim 1, wherein after said sending the data to the main control chip, further comprising:
and when the main control chip fails to read the data, storing the current data.
5. A Flash data read-write system, comprising:
the host chip, CPLD, flash memory;
the CPLD comprises a UFM register;
the main control chip is connected with the CPLD, the CPLD is connected with the Flash memory,
the CPLD is used for receiving the data sent by the Flash memory, sending the data to the main control chip and storing the data to a UFM register of the CPLD; the CPLD is also used for sending a reset signal to the main control chip and the Flash memory when the main control chip and the data in the Flash memory are not synchronous, and the reset signal is used for controlling the main control chip and the Flash memory to be reset at the same time.
6. The Flash data read-write system according to claim 5, further comprising: BMC;
and the BMC is connected with the CPLD and the Flash memory and is used for checking whether the data in the Flash memory and the data in the UFM register are consistent.
7. The Flash data read-write system according to claim 6, wherein the main control chip is connected with the CPLD through an SPI bus, the CPLD is connected with the Flash memory through the SPI bus, and the CPLD is connected with the BMC through an IIC bus.
8. The Flash data read-write device is characterized by being applied to a CPLD, wherein the CPLD is respectively connected with a main control chip and a Flash memory, and the device comprises:
the receiving module is used for receiving the data sent by the Flash memory;
the storage module is used for sending the data to the main control chip and storing the data to a UFM register of the CPLD;
the judging module is used for judging whether the main control chip is synchronous with the data in the Flash memory or not; if not, triggering a reset module;
the reset module is used for sending a reset signal to the main control chip and the Flash memory, and the reset signal is used for controlling the main control chip and the Flash memory to be reset at the same time.
9. A Flash data read-write device, characterized by comprising:
a memory for storing a computer program;
a processor for implementing the steps of the Flash data read-write method according to any one of claims 1 to 4 when executing said computer program.
10. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the Flash data read-write method according to any of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210017456.3A CN114461142B (en) | 2022-01-07 | 2022-01-07 | Method, system, device and medium for reading and writing Flash data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210017456.3A CN114461142B (en) | 2022-01-07 | 2022-01-07 | Method, system, device and medium for reading and writing Flash data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114461142A CN114461142A (en) | 2022-05-10 |
| CN114461142B true CN114461142B (en) | 2023-08-08 |
Family
ID=81410371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210017456.3A Active CN114461142B (en) | 2022-01-07 | 2022-01-07 | Method, system, device and medium for reading and writing Flash data |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114461142B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101206162A (en) * | 2007-12-14 | 2008-06-25 | 哈尔滨工程大学 | System for data acquisition and signal treatment of testing flat wheel |
| CN202424658U (en) * | 2011-12-28 | 2012-09-05 | 天津市亚安科技股份有限公司 | Synchronous resetting circuit for master control chip and video camera |
| CN110187923A (en) * | 2019-05-10 | 2019-08-30 | 杭州迪普科技股份有限公司 | A kind of CPU starting method and apparatus applied to multi -CPU board |
-
2022
- 2022-01-07 CN CN202210017456.3A patent/CN114461142B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101206162A (en) * | 2007-12-14 | 2008-06-25 | 哈尔滨工程大学 | System for data acquisition and signal treatment of testing flat wheel |
| CN202424658U (en) * | 2011-12-28 | 2012-09-05 | 天津市亚安科技股份有限公司 | Synchronous resetting circuit for master control chip and video camera |
| CN110187923A (en) * | 2019-05-10 | 2019-08-30 | 杭州迪普科技股份有限公司 | A kind of CPU starting method and apparatus applied to multi -CPU board |
Non-Patent Citations (1)
| Title |
|---|
| 嵌入式Nor Flash数据安全存储***设计;方彬浩;;计算机产品与流通(第02期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114461142A (en) | 2022-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8898517B2 (en) | Handling a failed processor of a multiprocessor information handling system | |
| CN113568848B (en) | Processor, signal adjusting method and computer system | |
| CN112506745B (en) | Memory temperature reading method and device and computer readable storage medium | |
| CN112231005A (en) | Method for managing FPGA (field programmable Gate array) version based on UBOOT (Universal boot on Board) | |
| CN111782446A (en) | Method and device for testing normal power failure of SSD, computer equipment and storage medium | |
| CN113672306B (en) | Server component self-checking abnormity recovery method, device, system and medium | |
| CN113608684B (en) | Memory information acquisition method, device and system, electronic equipment and storage medium | |
| CN114461142B (en) | Method, system, device and medium for reading and writing Flash data | |
| EP2750030A1 (en) | Method, apparatus and processor for reading BIOS | |
| CN114461286B (en) | Server starting method and device, electronic equipment and readable storage medium | |
| CN115766410A (en) | Method, system, device and medium for switching working states of machine | |
| CN113886148A (en) | CPU diagnosis system, method, device and medium | |
| CN111061603B (en) | Motherboard capable of recording self-checking data, computer and recording method of self-checking data | |
| CN113849355A (en) | I2C rate self-adaptive adjusting method, system, terminal and storage medium | |
| CN114968629A (en) | Computer system and special crash dump device thereof and method for recording error data | |
| CN114153303B (en) | Power consumption control system, power consumption control method, device and medium | |
| TWI794997B (en) | Method and apparatus and computer program product for debugging solid state disk devices | |
| CN114153388B (en) | Hard disk system, hard disk configuration information refreshing method, device and medium | |
| CN115454906A (en) | Data communication system, method, device and readable storage medium | |
| CN118069057A (en) | Data writing method, device, equipment and medium | |
| CN116089139A (en) | Method, device and medium for processing serial hard disk faults | |
| CN115858433A (en) | Method, system, device, equipment and storage medium for controlling retimer mode | |
| CN114780310A (en) | Method and device for verifying influence of D3cold on enabled SSD HMB | |
| CN115729573A (en) | Firmware upgrading method, device, chip and computer storage medium | |
| CN114116306A (en) | Data backup method, system, terminal and storage medium under power failure of disk array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |