CN111355914B - Video system signal generating device and method - Google Patents
Video system signal generating device and method Download PDFInfo
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- CN111355914B CN111355914B CN201811584132.8A CN201811584132A CN111355914B CN 111355914 B CN111355914 B CN 111355914B CN 201811584132 A CN201811584132 A CN 201811584132A CN 111355914 B CN111355914 B CN 111355914B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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Abstract
The invention provides a video system signal generating device and a method, wherein the device comprises: the input buffer module is used for simultaneously buffering a left half image and a right half image of an input video image and converting the left half image and the right half image into an image; the system configuration module is used for receiving the system configuration parameters and sending the system configuration parameters to the system control module; the system control module is used for receiving the system configuration parameters sent by the system configuration module and generating system information according to the system configuration parameters; the system generating module is used for reading image data cached in the caching module according to the system information generated by the system control module, packaging the image data to generate a video system signal and outputting the video system signal to the parallel-serial conversion module; and the parallel-serial conversion module is used for dividing the video system signal output by the system generation module into two clocks for serial output. The scheme provided by the invention can realize the conversion of the video image into the signal output of the ultra-high definition video system.
Description
Technical Field
The present invention relates to the field of video technologies, and in particular, to a video format signal generating apparatus and method.
Background
Video images are widely applied to various aspects of life, and mobile phones, televisions and other equipment can display and play videos; the video image can be correctly displayed only by converting the video image into a standard system supported by related display equipment; with the improvement of video resolution, the clock frequency of a video system is also synchronously improved, and particularly after an ultra-clear video (4Kx2K) appears, the clock frequency of the corresponding video system is improved to 600MHz, so that the requirement on the design of a video system generating circuit is improved, and a common circuit design cannot work at such a high frequency.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and to provide a video format signal generating apparatus and method, so as to solve the problem that the conventional video format generating circuit in the prior art cannot work at a higher frequency.
One aspect of the present invention provides a video format signal generating apparatus, including: the input buffer module is used for simultaneously buffering a left half image and a right half image of an input video image and converting the left half image and the right half image into an image; the system configuration module is used for receiving system configuration parameters and sending the received system configuration parameters to the system control module; the system control module is used for receiving the system configuration parameters sent by the system configuration module and generating system information according to the system configuration parameters; the system generating module is used for reading image data cached in the caching module according to the system information generated by the system control module, packaging the image data to generate a video system signal and outputting the video system signal to the parallel-serial conversion module; and the parallel-serial conversion module is used for dividing the video system signal output by the system generation module into two clocks for serial output.
Optionally, the input buffer module buffers the left half image and the right half image of the input video image simultaneously, and converts the left half image and the right half image into an image, including: simultaneously caching a left half image and a right half image of an input video image in a line caching mode; after the left half image line cache and the right half image line cache are finished every line, the cached left half image data and right half image data are read out in sequence until an image data is generated.
Optionally, the system configuration parameters include: line synchronization information, line synchronization trailing edge, line synchronization leading edge, field synchronization information, field synchronization trailing edge, field synchronization leading edge, image effective width information, and image effective height information.
Optionally, the input buffer module includes: a static memory; the input buffer module comprises: a left half graph line cache unit and a right half graph line cache unit; and/or, a bit width of the static memory, including: two input data widths.
Optionally, the system information includes: a horizontal sync signal, a field sync signal, and a data valid signal; the system control module generates system information according to the system configuration parameters, and the method comprises the following steps: and outputting two line synchronizing signals, two field synchronizing signals and two effective data signals in each clock cycle according to the system configuration parameters.
Optionally, the system generating module, configured to read image data cached in the cache module according to the system information generated by the system control module, includes: reading the image data in the input buffer module according to the data effective signals in sequence to generate image signals; packing the image data to generate a video format signal, comprising: and packaging the generated image signal with the line synchronizing signal and the field synchronizing signal to generate a video system signal.
Optionally, sequentially reading the image data in the input buffer module according to the data valid signal to generate an image signal, including: and reading the image data of two pixel points each time, thereby generating a double-pixel image signal.
Another aspect of the present invention provides a method for generating a video format signal, including: an input caching step, which is used for caching the left half image and the right half image of an input video image to an input caching module at the same time and converting the left half image and the right half image into an image; a system configuration step, which is used for receiving system configuration parameters; a system control step, which is used for generating system information according to the system configuration parameters; a format generation step, which is used for reading the image data cached in the input caching module according to the format information and packaging the image data to generate a video format signal; and a parallel-serial conversion step for dividing the generated video system signal into two clocks for serial output.
Optionally, buffering the left half image and the right half image of the input video image to the input buffer module at the same time, and converting the left half image and the right half image into an image, includes: simultaneously caching a left half image and a right half image of an input video image in a line caching mode; after the left half image line cache and the right half image line cache are finished every line, the cached left half image data and right half image data are read out in sequence until an image data is generated.
Optionally, the system configuration parameters include: line sync information HSYNC, line sync trailing edge, line sync leading edge, field sync information, field sync trailing edge, field sync leading edge, image effective width information, and image effective height information.
Optionally, the input buffer module includes: a static memory; the static memory includes: a left half graph line cache unit and a right half graph line cache unit; and/or, a bit width of the static memory, including: two input data widths.
Optionally, the system information includes: a horizontal sync signal, a field sync signal, and a data valid signal; generating system information according to the system configuration parameters, wherein the method comprises the following steps: and outputting two line synchronizing signals, two field synchronizing signals and two effective data signals in each clock cycle according to the system configuration parameters.
Optionally, reading image data cached in an input cache module according to the format information, including: reading the image data in the input buffer module according to the data effective signals in sequence to generate image signals; packing the image data to generate a video format signal, comprising: and packaging the generated image signal with the line synchronizing signal and the field synchronizing signal to generate a video system signal.
Optionally, sequentially reading the image data in the input buffer module according to the data valid signal to generate an image signal, including: and reading the image data of two pixel points each time, thereby generating a double-pixel image signal.
According to the technical scheme of the invention, in a dual-mode processing mode, two data are simultaneously output in each clock period and converted into high-frequency clock domain serial output through serial-parallel conversion, so that the conversion of a video image into a high-definition video mode signal output can be realized, and the conversion of an ultra-high-definition video image into an ultra-high-definition video mode signal output to display equipment or an HDMI (high-definition multimedia interface) interface is realized; the input cache module, the system control module and the system generation module can simultaneously output two pixels or two blanking area points, and the efficiency is twice of that of single output.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of an embodiment of a video format signal generating apparatus provided in the present invention;
fig. 2 is a functional block diagram of each module of the video format generation apparatus according to the embodiment of the present invention;
FIG. 3 is a block diagram of a design of an input cache module according to an embodiment of the invention;
FIG. 4 is a signal diagram of a video format according to an embodiment of the invention;
fig. 5 is a schematic diagram of outputting a synchronization signal according to a system configuration parameter according to an embodiment of the present invention;
fig. 6 is a schematic method diagram of an embodiment of a video format signal generation method provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic structural diagram of an embodiment of a video format signal generating apparatus according to the present invention.
As shown in fig. 1, according to an embodiment of the present invention, the video format signal generating apparatus includes an input buffer module 110, a format configuration module 120, a format control module 130, a format generating module 140, and a parallel-serial conversion module 150. Fig. 2 is a functional block diagram of each module of the video format generation apparatus according to the embodiment of the present invention.
The input buffer module 110 is configured to buffer a left half image and a right half image of an input video image at the same time, and convert the left half image and the right half image into an image; the system configuration module 120 is configured to receive a system configuration parameter, and send the received system configuration parameter to the system control module; the system control module 130 is configured to receive the system configuration parameter sent by the system configuration module, and generate system information according to the system configuration parameter; the format generating module 140 is configured to read image data cached in the input cache module 110 according to format information generated by the format control module 130, and package the image data to generate a video format signal and output the video format signal to the parallel-serial conversion module 150; the parallel-serial conversion module 150 is configured to divide the video format signal output by the format generation module into two clocks for serial output.
The input buffer module 110 simultaneously buffers the left half image and the right half image of the input video image and converts the left half image and the right half image into an image. Specifically, the input caching module caches a left half image and a right half image of an input video image simultaneously in a line caching mode; after the left half image line cache and the right half image line cache are finished every line, the cached left half image data and right half image data are read out in sequence until an image data is generated.
The input video image is equally divided into two half images from the middle position, and the input buffer module 110 simultaneously buffers the left half image and the right half image, so that two pixel points can be buffered in each input clock period (for example, 300M), and the reading rate requirement of a single pixel point of a double output clock (for example, 600M) is met; when the left half image line buffer memory and the right half image line buffer memory half-line images, the left half line data is read out first and then the right half line data is read out in sequence, the whole line of image data is read out in the mode, and the image can be converted into an image by the same operation for N times (N is the line number of the image). Referring specifically to fig. 3, fig. 3 is a block diagram of a design of an input buffer module according to an embodiment of the present invention. As shown in fig. 3, the input buffer module includes a left half line buffer unit and a right half line buffer unit. The input cache module may specifically include a static memory SRAM. The SRAM is divided into two blocks, which are a left half line cache and a right half line cache, respectively, and caches a line of image, each SRAM address stores two pixel points, as shown in fig. 3, the pixel points of the left half are written into the left half line cache in sequence, the points of the right half are written into the right half line cache in sequence, after the left half line image and the right half line image are all cached, the pixels are read out in sequence from left to right, and two pixel points are output each time. After a line of image is cached, reading out the cached image data in sequence, wherein the bit width of the static memory SRAM is preferably two input data widths, two pixel point data are stored into the SRAM each time when the image is cached, and two pixel points can be read by each clock when the SRAM is read.
The system configuration module 120 receives the system configuration parameters and sends the received system configuration parameters to the system control module. Specifically, the system configuration parameters are written into the system configuration module according to the video system to be output. Fig. 4 is a signal diagram of a video format according to an embodiment of the present invention. As shown in fig. 4, the format configuration parameters include line synchronization information HSYNC, line synchronization trailing edge HBP, line synchronization leading edge HFP, field synchronization information VSYNC, field synchronization trailing edge VBP, field synchronization leading edge VFP, image effective width information Active width, and image effective height information Active height. In fig. 4, Total Height is the Total Height of the video signal, Total width is the Total width of the video signal, VSYNC width is the field sync signal width, HSYNC is the Line sync signal width, Active Display Area is the Display Area of the effective image, Data1 is the first Data of the effective image, Line1 represents the first Data of the effective image, and so on.
The system control module 130 receives the system configuration parameters sent by the system configuration module 120, and generates system information according to the system configuration parameters. Wherein the system information includes: a line sync signal HSYNC, a field sync signal VSYNC, and a data valid signal. Preferably, the system control module 130 outputs two line synchronization signals, two field synchronization signals, and two data valid signals per clock cycle according to the system configuration parameters, so as to achieve twice output efficiency.
Fig. 5 is a schematic diagram of outputting a synchronization signal according to system configuration parameters according to an embodiment of the present invention. Referring to fig. 5, HSYNC is a row sync signal, CLK is a clock signal, and HSYNC is 12 clock cycles, for example, and system control module 130 outputs two timing signals HSYNC [1:0] every clock cycle, where HSYNC [0] is an HSYNC value of an even clock (0/2/4/6/8/10) and HSYNC [1] is an HSYNC value of an odd clock (1/3/5/7/9/11), so that six clocks and 12 HSYNC values can be output. The system control module 130 outputs HSYNC [1:0], HSYNC [1:0], ACTIVE [1:0] in each clock cycle, and sends the output to the system generation module 140.
The format generating module 140 reads the image data buffered in the input buffer module 110 according to the format information generated by the format control module 130, and packs the image data to generate a video format signal, and outputs the video format signal to the parallel-serial conversion module 150. Specifically, after receiving the format information HSYNC [1:0], VSYNC [1:0], and ACTIVE [1:0], the format generation module 140 sequentially reads the image data in the input buffer module according to the data valid signal to generate an image signal. Preferably, the format generating module 140 reads the image DATA of two pixels at a time, so as to generate a dual-pixel image signal, i.e. a dual DATA signal, where DATA is an image pixel input into the buffer when ACTIVE is 1, and DATA is blanking area DATA when ACTIVE is 0.
The step of packing the image data to generate a video format signal specifically includes: and packaging the generated image signal with the line synchronizing signal and the field synchronizing signal to generate a video system signal. That is, the HSYNC [1:0], VSYNC [1:0] and dual DATA signals are packed together as a set of DATA { HSYNC [1:0], VSYNC [1:0], DATA }, where the DATA of each packet contains two pixel values and synchronization information, in effect two sets of DATA, and output to the parallel-to-serial conversion module 150.
The parallel-serial conversion module 150 divides the video format signal output by the format generation module 140 into two clocks for serial output. As shown in fig. 2, the video format signal generated by the format generation module is divided into two clocks to be output serially, and each clock outputs DATA, HSYNC, and VSYNC signals. The input buffer module 110, the format configuration module 120, the format control module 130, and the format generation module 140 are signals in the same clock domain as the input video image. The input buffer module 110, the format configuration module 120, the format control module 130, and the format generation module 140 work in a clock domain with a first clock frequency (i.e., data is transmitted with the first clock frequency), and the parallel-serial conversion module 150 works in a clock domain with a second clock frequency (i.e., data is transmitted with the second clock frequency), where the second clock frequency is equal to twice the first clock frequency, so that the parallel-serial conversion module 150 can receive two data of the first clock frequency and output one data with the double clock frequency of the first clock frequency, thereby achieving twice data transmission efficiency. For example, the parallel-serial conversion module 150 receives two data transmitted by the format generation module 140 at 300M clock, and outputs one data at 600M clock, thereby realizing output of super-definition video format signal at 600M clock.
For clearly explaining the technical solution of the present invention, an execution flow of generating a video format signal by a video format signal generating apparatus according to the present invention is described below with a specific embodiment.
Firstly, the system writes system configuration parameters into a system configuration module according to a high-definition video system to be output, the configuration parameters include HSYNC, HBP, HFP, VSYNC, VBP, VFP, Active width, Active height, and the like, and the (enable) system configuration module 120 can be enabled after the system configuration parameters are written. After enabling, the system control module 130 outputs system information including VSYNC, HSYNC, and ACTIVE signals according to the system configuration parameters of the system configuration module 120, in order to improve twice output efficiency, the system control module 120 outputs two synchronization signals per clock cycle, as shown in fig. 3, outputs HSYNC [1:0], and ACTIVE [1:0], and at the same time, the input buffer module 110 receives the input left half-image and right half-image data, stores the data in an internal static memory SRAM, the SRAM is divided into two blocks, which are respectively a left half-image line buffer and a right half-image line buffer, and after buffering one line of image, sequentially reads out the buffered images, the storage mode is shown in fig. 2, the SRAM has two input data widths, and each clock outputs two pixels. The format generation module 140 receives format information HSYNC [1:0], VSYNC [1:0], and ACTIVE [1:0], sequentially reads the image in the input buffer module 110 according to the ACTIVE information, generates a dual DATA signal by reading two pixels at a time, DATA is the image pixel of the input buffer when ACTIVE is 1, DATA is blanking area DATA when ACTIVE is 0, and packets HSYNC [1:0], VSYNC [1:0], and DATA together as a set of DATA { HSYNC [1:0], VSYNC [1:0], and DATA }, where the DATA of each packet includes two pixel values and synchronization information and is output to the parallel-serial conversion module 150, and the serial conversion module 150 divides the DATA of the format generation module 140 into two clock serial outputs, each clock outputs HSYNC, VSYNC, and the parallel-serial conversion module receives two DATA transmitted in a certain clock domain, and outputs a single DATA in a double clock domain, a two-fold data efficiency match is achieved.
The input cache module, the system control module and the system generation module in the device can simultaneously output two pixels or two blanking area points, and the efficiency is twice of that of single output.
The invention also provides a video standard signal generating method.
Fig. 6 is a schematic method diagram of an embodiment of a video format signal generation method provided by the present invention. As shown in fig. 6, the video format signal generating method includes an input buffer step S110, a format configuration step S120, a format control step S130, a format generating step S140, and a parallel-serial conversion step S150.
The input buffer step S110 is used for simultaneously buffering the left half image and the right half image of the input video image to the input buffer module, and converting the left half image and the right half image into an image.
Specifically, a left half image and a right half image of an input video image are simultaneously cached in a line cache mode; after the left half image line cache and the right half image line cache are finished every line, the cached left half image data and right half image data are read out in sequence until an image data is generated.
An input video image is equally divided into two half images from a middle position, and the left half image and the right half image are cached to an input caching module at the same time, so that two pixel points can be cached in each input clock period (for example, 300M), and the reading speed requirement of a single pixel point of a double output clock (for example, 600M) is met; when the left half image line buffer memory and the right half image line buffer memory half-line images, the left half line data is read out first and then the right half line data is read out in sequence, the whole line of image data is read out in the mode, and the image can be converted into an image by the same operation for N times (N is the line number of the image). Referring specifically to fig. 3, fig. 3 is a block diagram of a design of an input buffer module according to an embodiment of the present invention. As shown in fig. 3, the input buffer module includes a left half line buffer unit and a right half line buffer unit. The input cache module may specifically include a static memory SRAM. The SRAM is divided into two blocks, which are a left half line cache and a right half line cache, respectively, and caches a line of image, each SRAM address stores two pixel points, as shown in fig. 3, the pixel points of the left half are written into the left half line cache in sequence, the points of the right half are written into the right half line cache in sequence, after the left half line image and the right half line image are all cached, the pixels are read out in sequence from left to right, and two pixel points are output each time. After a line of image is cached, reading out the cached image data in sequence, wherein the bit width of the static memory SRAM is preferably two input data widths, two pixel point data are stored into the SRAM each time when the image is cached, and two pixel points can be read by each clock when the SRAM is read.
The system configuration step S120 is configured to receive system configuration parameters. Fig. 4 is a signal diagram of a video format according to an embodiment of the present invention. As shown in fig. 4, the format configuration parameters include line synchronization information HSYNC, line synchronization trailing edge HBP, line synchronization leading edge HFP, field synchronization information VSYNC, field synchronization trailing edge VBP, field synchronization leading edge VFP, image effective width information Active width, and image effective height information Active height. In fig. 4, Total Height is the Total Height of the video signal, Total width is the Total width of the video signal, VSYNC width is the field sync signal width, HSYNC is the Line sync signal width, Active Display Area is the Display Area of the effective image, Data1 is the first Data of the effective image, Line1 represents the first Data of the effective image, and so on.
The system control step S130 is configured to generate system information according to the system configuration parameter.
The system information includes: a line sync signal HSYNC, a field sync signal VSYNC, and a data valid signal. Preferably, according to the system configuration parameters, two line synchronization signals, two field synchronization signals and two data valid signals are output in each clock cycle, so as to achieve twice output efficiency.
Fig. 5 is a schematic diagram of outputting a synchronization signal according to system configuration parameters according to an embodiment of the present invention. Referring to FIG. 5, HSYNC is a row synchronization signal, CLK is a clock signal, and for example, HSYNC is 12 clock cycles, and each clock cycle outputs two timing signals HSYNC [1:0], HSYNC [0] is an HSYNC value of an even clock (0/2/4/6/8/10), and HSYNC [1] is an HSYNC value of an odd clock (1/3/5/7/9/11), so that six clocks and 12 HSYNC values can be output. The system control module 130 outputs HSYNC [1:0], HSYNC [1:0], ACTIVE [1:0] in each clock cycle, and sends the output to the system generation module 140.
The format generating step S140 is configured to read image data cached in the input caching module according to the format information, and package the image data to generate a video format signal.
Specifically, after system information HSYNC [1:0], VSYNC [1:0] and ACTIVE [1:0] are received, image data in the input buffer module is sequentially read according to an ACTIVE signal (data valid signal) to generate an image signal. Preferably, the format generating module 140 reads the image DATA of two pixels at a time, so as to generate a dual-pixel image signal, i.e. a dual DATA signal, where DATA is an image pixel input into the buffer when ACTIVE is 1, and DATA is blanking area DATA when ACTIVE is 0.
The step of packing the image data to generate a video format signal specifically includes: and packaging the generated image signal with the line synchronizing signal and the field synchronizing signal to generate a video system signal. That is, the HSYNC [1:0], VSYNC [1:0] and dual DATA signals are packed together as a set of DATA { HSYNC [1:0], VSYNC [1:0], DATA }, where the DATA of each packet contains two pixel values and synchronization information, in effect two sets of DATA, and is transmitted to the parallel-to-serial conversion module and output to the parallel-to-serial conversion module 150.
The parallel-serial conversion step S150 is configured to divide the generated video format signal into two clocks and output them serially. As shown in fig. 2, the generated video system signal is divided into two clocks to be serially output, and each clock outputs DATA, HSYNC, and VSYNC signals. The signal transmitted in the input buffer step S110, the format configuration step S120, the format control step S130, and the format generation step S140 is a signal in the same clock domain as the input video image. The input buffer step S110, the format configuration step S120, the format control step S130, and the format generation step S140 transmit data at a first clock frequency, and the parallel-serial conversion step S150 transmits data at a second clock frequency, where the second clock frequency is twice as high as the first clock frequency, so that the parallel-serial conversion step S150 can receive two data of the first clock frequency and output one data at the double clock frequency of the first clock frequency, thereby achieving twice data transmission efficiency. For example, two data are transmitted by receiving 300M clock, and one data is output by 600M clock, thereby realizing that the super-definition video system signal is output by 600M clock.
Therefore, according to the scheme provided by the invention, two data are simultaneously output in each clock period in a dual-mode processing mode, and are converted into high-frequency clock domain serial output through serial-parallel conversion, so that the conversion of a video image into a high-definition video mode signal output can be realized, and the conversion of an ultra-high-definition video image into an ultra-high-definition video mode signal output to display equipment or an HDMI (high-definition multimedia interface) is realized; the input cache module, the system control module and the system generation module can simultaneously output two pixels or two blanking area points, and the efficiency is twice of that of single output.
The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or a combination of any of these. In addition, each functional unit may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and the parts serving as the control device may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The above description is only an example of the present invention, and is not intended to limit the present invention, and it is obvious to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (4)
1. A video system signal generating apparatus, comprising:
the input buffer module is used for simultaneously buffering a left half image and a right half image of an input video image and converting the left half image and the right half image into an image;
the system configuration module is used for receiving system configuration parameters and sending the received system configuration parameters to the system control module;
the system control module is used for receiving the system configuration parameters sent by the system configuration module and generating system information according to the system configuration parameters;
the system generating module is used for reading image data cached in the caching module according to the system information generated by the system control module, packaging the image data to generate a video system signal and outputting the video system signal to the parallel-serial conversion module;
the parallel-serial conversion module is used for dividing the video standard signal output by the standard generation module into two clocks for serial output;
the system information includes: a horizontal sync signal, a field sync signal, and a data valid signal;
the system control module generates system information according to the system configuration parameters, and the method comprises the following steps:
outputting two line synchronizing signals, two field synchronizing signals and two effective data signals in each clock period according to the system configuration parameters;
the system configuration parameters comprise:
line synchronization information, line synchronization trailing edge, line synchronization leading edge, field synchronization information, field synchronization trailing edge, field synchronization leading edge, image effective width information, and image effective height information;
the input buffer module comprises: a static memory;
the input buffer module comprises: a left half graph line cache unit and a right half graph line cache unit; and/or, a bit width of the static memory, including: two input data widths;
reading and inputting image data cached in a cache module according to the format information generated by the format control module, wherein the image data comprises:
reading the image data in the input buffer module according to the data effective signals in sequence to generate image signals;
packing the image data to generate a video format signal, comprising:
packing the generated image signal with the line synchronizing signal and the field synchronizing signal to generate a video system signal;
reading the image data in the input buffer module in sequence according to the data valid signal to generate an image signal, comprising:
and reading the image data of two pixel points each time, thereby generating a double-pixel image signal.
2. The apparatus of claim 1, wherein the input buffer module simultaneously buffers the left half image and the right half image of the input video image and converts the left half image and the right half image into an image, comprising:
simultaneously caching a left half image and a right half image of an input video image in a line caching mode;
after the left half image line cache and the right half image line cache are finished every line, the cached left half image data and right half image data are read out in sequence until an image data is generated.
3. A video format signal generating method, comprising:
an input caching step, which is used for caching the left half image and the right half image of an input video image to an input caching module at the same time and converting the left half image and the right half image into an image;
a system configuration step, which is used for receiving system configuration parameters;
a system control step, which is used for generating system information according to the system configuration parameters;
a format generation step, which is used for reading the image data cached in the input caching module according to the format information and packaging the image data to generate a video format signal;
a parallel-serial conversion step for dividing the generated video system signal into two clocks for serial output;
the system information includes: a horizontal sync signal, a field sync signal, and a data valid signal;
generating system information according to the system configuration parameters, wherein the method comprises the following steps:
outputting two line synchronizing signals, two field synchronizing signals and two effective data signals in each clock period according to the system configuration parameters;
the system configuration parameters comprise:
line synchronization information, line synchronization trailing edge, line synchronization leading edge, field synchronization information, field synchronization trailing edge, field synchronization leading edge, image effective width information, and image effective height information;
the input buffer module comprises: a static memory;
the static memory includes: a left half graph line cache unit and a right half graph line cache unit; and/or the presence of a gas in the gas,
a bit width of the static memory, comprising: two input data widths;
reading and inputting the image data cached in the caching module according to the system information, wherein the reading and inputting method comprises the following steps:
reading the image data in the input buffer module according to the data effective signals in sequence to generate image signals;
packing the image data to generate a video format signal, comprising:
packing the generated image signal with the line synchronizing signal and the field synchronizing signal to generate a video system signal;
reading the image data in the input buffer module in sequence according to the data valid signal to generate an image signal, comprising:
and reading the image data of two pixel points each time, thereby generating a double-pixel image signal.
4. The method of claim 3, wherein simultaneously buffering the left half and the right half of the input video image into the input buffer module and converting the left half and the right half into one image comprises:
simultaneously caching a left half image and a right half image of an input video image in a line caching mode;
after the left half image line cache and the right half image line cache are finished every line, the cached left half image data and right half image data are read out in sequence until an image data is generated.
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