CN103647918A - Video synchronization method and device - Google Patents
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Abstract
The invention discloses a video synchronization method and device. The video synchronization method comprises detecting line timing and field timing parameters of input video signals, storing effective video pixel data into a BUFFER; calculating new timing parameters through calculation and utilization of a proportional relation of pixel clocks of input and output videos; delaying field-synchronizing signals of the input videos N-line time to serve as the field-synchronizing signals of input signals; generating BUFFER read enable signals which are used for reading pixel data from the BUFFER; aligning line synchronizing signals, the field-synchronizing signals and data effective signals with the pixel data and outputting post-encapsulation video streaming. The video synchronization method and device can achieve video synchronization without an external memory and reduce costs; can support synchronization processing of video signals of any resolution, enables the frame rate of the output video to be in accordance with the input video, and can maintain line and field timing formats of VESA (Video Electronics Standards Association) standards.
Description
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Technical field
The present invention relates to video signal processing field, more specifically, relate to a kind of method and device of video synchronization.
Background technology
The form of display video signal is comprised of pixel clock, line synchronizing signal, field sync signal, data useful signal and pixel data.Sequential format as shown in Figure 2.
The pixel clock of the video of different resolution is different, and for video signal collective chip, inner processing is all to carry out under unified clock, and this just need to be synchronized to the video pixel data of input in inner processing clock.Common way has following mode:
One, adopt external memory storage to do frame buffer, the transmission method of a kind of picture signal of the Patent Application Publication that application number is 201010578864.3, device and formatting method, device.Its disclosed method is that the video pixel data of input is all left in external memory storage, and then uses inner processing clock that data are read out, and realizes synchronization.This method needs external memory storage, has taken PCB area, has also increased cost simultaneously.And can only for input resolution, be less than the video of 2160x1250, surpassed this resolution and cannot support.No matter the frame per second of video flowing of input is how many, the later frame per second of synchronization is fixing frame per second, can not reflect really the characteristic of input video stream in addition, for keeping the application scenario of the frame per second of input video stream script to support.
Two, adopt an inner BUFFER, data are first cached in this BUFFER, then as long as this BUFFER non-NULL just reads out data, such as the self-defining ST stream of FPGA vendor A ltera bus format.This mode adopts a BUFFER just can realize video pixel data is synchronized in inner processing clock, but has destroyed the original row of vision signal, a sequential.If the processing module of rear end need to retain the sequential that meets VESA standard, this mode is infeasible.
Summary of the invention
Not enough in order to overcome above-mentioned prior art, first the present invention proposes a kind of method of video synchronization, adopts the method without external memory storage, can reduce PCB area, thereby reduce costs.
Another object of the present invention is the device that proposes a kind of video synchronization.
To achieve these goals, technical scheme of the present invention is:
A method for video synchronization, comprising:
Input video format detection, detect row, a time sequence parameter of incoming video signal, and effective video pixel data is saved in buffer memory BUFFER, wherein said row, a time sequence parameter comprise the synchronous width of row, the synchronous crop of row, the synchronous back porch of row, row total time, field synchronization width, field synchronization crop, field synchronization back porch, a total time, row resolution, a resolution and pixel clock frequency;
Output video form calculates, utilize the proportionate relationship of input video pixel clock and output video pixel clock to calculate the time sequence parameter making new advances, the wherein capable total time/input video of the capable total time=output video of output video pixel clock frequency * input video pixel clock frequency; It is identical with the vision signal of input that other parameters keep;
Field sync signal postpones, and the field sync signal of input video is postponed to N line time as the field sync signal of output signal, N >=1 by the Depth determination of the buffer memory BUFFER arranging;
Output video sequential occurs, and produces the video clock signal of output video, comprises line synchronizing signal, field sync signal and data useful signal; Produce buffer memory BUFFER simultaneously and read enable signal, for pixel data is read out from buffer memory BUFFER;
The encapsulation of frame of video form, by line synchronizing signal, field sync signal, data useful signal and pixel data alignment, the video flowing after output encapsulation.
A device for video synchronization, comprises
Input video format detection module, row, a time sequence parameter for detection of incoming video signal, and effective video pixel data is saved in buffer memory BUFFER, wherein said row, a time sequence parameter comprise the synchronous width of row, the synchronous crop of row, the synchronous back porch of row, row total time, field synchronization width, field synchronization crop, field synchronization back porch, a total time, row resolution, a resolution and pixel clock frequency;
Output video form computing module, for utilizing the proportionate relationship of input video pixel clock and output video pixel clock, calculate the time sequence parameter making new advances, the wherein capable total time/input video of the capable total time=output video of output video pixel clock frequency * input video pixel clock frequency; It is identical with the vision signal of input that other parameters keep;
Field sync signal Postponement module, for the field sync signal of input video is postponed to N line time as the field sync signal of output signal, N >=1 by the Depth determination of the buffer memory BUFFER arranging;
Output video timing sequencer, for generation of the video clock signal of output video, comprises line synchronizing signal, field sync signal and data useful signal; Produce buffer memory BUFFER simultaneously and read enable signal, for pixel data is read out from buffer memory BUFFER;
Frame of video form package module, for by line synchronizing signal, field sync signal, data useful signal and pixel data alignment, exports the video flowing after encapsulation.
Compared with prior art, beneficial effect of the present invention is:
1) adopt the video synchronization of realizing of the present invention without external memory storage, the cross clock domain that only needs a very little storage BUFFER of internal capacity just can complete video flowing is synchronous, has reduced the device cost of system, has also reduced difficulty and the cost of PCB design;
2) internal work clock can configure a suitable clock according to the scope of the resolution of inputting in actual use procedure.The present invention can be synchronized to internal clocking territory by the arbitrary resolution in the supported scope of internal work clock, applied widely;
3) the present invention can guarantee that the video of output meets the row field synchronization form of VESA standard, from external interface, it seems, the video flowing of output is consistent on form with the video flowing of input, can meet the interface requirements of generic video processing module;
4) frame per second of output video of the present invention and the frame per second of input video are consistent, and can reflect truly the characteristic of input video.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the device of video synchronization.
Fig. 2 is the form schematic diagram of existing display video sequential.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described, but embodiments of the present invention are not limited to this.
As Fig. 1, input video format detection: by counter I, under each input video timeticks, add up 1, zero clearing when every a line finishes, counter I can be added up the information such as the synchronous width of trip, the synchronous crop of row, the synchronous back porch of row, effective row resolution; Zero clearing while being added up 1, one frame end after every row finishes by counter II, counter II can count the information such as field synchronization width, field synchronization crop, field synchronization back porch, effective field resolution.Utilize a reference clock, produce the clock interval of T millisecond, the pulse number N of statistical pixel clock within each time interval, the pixel clock that can obtain input video is that N*1000/T(unit is Hz).
Output video form calculates: the proportionate relationship of utilizing input video pixel clock and output video pixel clock, according to the row total time of input video, calculate the row total time of output video, guarantee that the absolute time of the output video scanning absolute time of a line and scanning a line of input video is consistent.Specific formula for calculation is as follows:
Capable total time/the input video of the capable total time=output video of output video pixel clock frequency * input video pixel clock frequency.
It is identical with input video that other parameters keep.According to the parameter after calculating, generate the synchronous sequence of output video, can dynamically adjust the horizontal blanking sector width of output video, with this, guarantee that buffer memory BUFFER enters abnormal empty or full state, also can guarantee that the frame per second of input and the frame per second of output are consistent.
Field sync signal postpones: by the field sync signal of input video is postponed to N line time as the field sync signal of output signal, N >=1 and be by the buffer memory BUFFER Depth determination arranging, in buffer memory BUFFER, at least deposit the capable valid data of N and just started reads pixel data as the pixel data of output video, prevent that buffer memory BUFFER from being read sky singularly, guarantee the correctness of output video pixel data.
Output video timing sequencer: utilize two counters, in the field sync signal of output after field sync signal postpones, start to start when effective counting, the every horizontal reset of counter 1 once, each output pixel clock cumulative 1, the every frame of counter 2 resets once, and output video adds up 1 after having scanned a line.According to output video form, calculate the parameter of obtaining, when counter 1, counter 2 arrive corresponding count value, field sync signal, line synchronizing signal, data useful signal complete 0 to 1 or 1 to 0 upset.Data useful signal is read out as the data of reading to enable in BUFFER simultaneously.
The encapsulation of frame of video form, is that line synchronizing signal, field sync signal, data useful signal are postponed to a bat, aligns, then the video flowing after output encapsulation with pixel data.
Above-described embodiments of the present invention, do not form limiting the scope of the present invention.Any modification of having done within spiritual principles of the present invention, be equal to and replace and improvement etc., within all should being included in claim protection range of the present invention.
Claims (5)
1. a method for video synchronization, is characterized in that, comprising:
Input video format detection, detect row, a time sequence parameter of incoming video signal, and effective video pixel data is saved in buffer memory BUFFER, wherein said row, a time sequence parameter comprise the synchronous width of row, the synchronous crop of row, the synchronous back porch of row, row total time, field synchronization width, field synchronization crop, field synchronization back porch, a total time, row resolution, a resolution and pixel clock frequency;
Output video form calculates, utilize the proportionate relationship of input video pixel clock and output video pixel clock to calculate the time sequence parameter making new advances, the wherein capable total time/input video of the capable total time=output video of output video pixel clock frequency * input video pixel clock frequency; It is identical with the vision signal of input that other parameters keep;
Field sync signal postpones, and the field sync signal of input video is postponed to N line time as the field sync signal of output signal, N >=1 by the Depth determination of the buffer memory BUFFER arranging;
Output video sequential occurs, and produces the video clock signal of output video, comprises line synchronizing signal, field sync signal and data useful signal; Produce buffer memory BUFFER simultaneously and read enable signal, for pixel data is read out from buffer memory BUFFER;
The encapsulation of frame of video form, by line synchronizing signal, field sync signal, data useful signal and pixel data alignment, the video flowing after output encapsulation.
2. the method for video synchronization according to claim 1, is characterized in that, adopts counter I sum counter II in input video format detection,
Wherein by counter I, under each input video timeticks, add up 1, zero clearing when every a line finishes, counter I is used for adding up the synchronous width of trip, the synchronous crop of row, the synchronous back porch of row, effective row resolution;
Zero clearing while being added up 1, one frame end after every row finishes by counter II, counter II is used for counting field synchronization width, field synchronization crop, field synchronization back porch, effective field resolution.
3. the method for video synchronization according to claim 2, is characterized in that, in sync signal delay on the scene, at least deposits the capable valid data of N in buffer memory BUFFER.
4. the method for video synchronization according to claim 3, is characterized in that, the write operation of described buffer memory BUFFER and input video format detection are operated in input video clock zone; Described output video form calculating, field sync signal delay, the generation of output video sequential and frame of video form encapsulation work are at output video clock zone.
5. a device for video synchronization, is characterized in that, comprises
Input video format detection module, row, a time sequence parameter for detection of incoming video signal, and effective video pixel data is saved in buffer memory BUFFER, wherein said row, a time sequence parameter comprise the synchronous width of row, the synchronous crop of row, the synchronous back porch of row, row total time, field synchronization width, field synchronization crop, field synchronization back porch, a total time, row resolution, a resolution and pixel clock frequency;
Output video form computing module, for utilizing the proportionate relationship of input video pixel clock and output video pixel clock, calculate the time sequence parameter making new advances, the wherein capable total time/input video of the capable total time=output video of output video pixel clock frequency * input video pixel clock frequency; It is identical with the vision signal of input that other parameters keep;
Field sync signal Postponement module, for the field sync signal of input video is postponed to N line time as the field sync signal of output signal, N >=1 by the Depth determination of the buffer memory BUFFER arranging;
Output video timing sequencer, for generation of the video clock signal of output video, comprises line synchronizing signal, field sync signal and data useful signal; Produce buffer memory BUFFER simultaneously and read enable signal, for pixel data is read out from buffer memory BUFFER;
Frame of video form package module, for by line synchronizing signal, field sync signal, data useful signal and pixel data alignment, exports the video flowing after encapsulation.
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| CN104469462A (en) * | 2014-12-03 | 2015-03-25 | 成都德芯数字科技有限公司 | Digital video signal processing system and method |
| CN106791552A (en) * | 2016-12-23 | 2017-05-31 | 龙迅半导体（合肥）股份有限公司 | A kind of method and device of reconstructing video sequential |
| CN106937157A (en) * | 2017-04-05 | 2017-07-07 | 上海矽奥微电子有限公司 | The autosynchronous device of cross clock domain video and its operating method |
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| CN107734386A (en) * | 2017-09-13 | 2018-02-23 | 东莞市爱协生智能科技有限公司 | The method and its system that a kind of video image based on MIPI agreements reduces |
| CN107846587A (en) * | 2017-10-30 | 2018-03-27 | 威创集团股份有限公司 | Field synchronization checking method for width and system |
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| CN103647918B (en) | 2017-04-12 |
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