CN206021233U - The memory of the random real time access of video flowing pixel DBMS - Google Patents
The memory of the random real time access of video flowing pixel DBMS Download PDFInfo
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- CN206021233U CN206021233U CN201620794469.1U CN201620794469U CN206021233U CN 206021233 U CN206021233 U CN 206021233U CN 201620794469 U CN201620794469 U CN 201620794469U CN 206021233 U CN206021233 U CN 206021233U
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Abstract
A kind of memory of the random real time access of video flowing pixel DBMS.Memory is constituted for mutually isostructural two groups of modules, each group of module constitutes block combiner using the QDR2 memory modules combination extension of two pieces of identical data burst read-write Burst 2, and two pieces of QDR2 memory modules are connected in parallel by address bus group, clock cable group, control signal wire group and data bus group.In each group of memory module combination, setting structure is identical, be exclusively used in each view data accesses the memory cell that reads and writes by two data bursts.Two groups of memory module combinations of memory are set to strange line storage unit and even line storage unit according to two adjacent strange rows of view data, even row, respectively the strange row data of storage image in strange line storage unit, storage image idol row data in even line storage unit.Sheet is new to make full use of memory space, it is ensured that the read-write of 2 burst modes of Burst effectively, is realized reading while write 4 pixel values with a pixel clock period.
Description
First, technical field
The utility model belongs to video image applied technical field, is related to the storage of high-definition video stream data, specifically
A kind of memory of the random real time access of video flowing pixel DBMS.
2nd, background technology
In video image application, the random real time access of data flow high-definition video stream pixel DBMS is in video figure
Essential in the generation of picture, the fluency of random real time access, pixel clock period, reading data efficiency direct relation video
The quality of image.
For high-definition video stream data handling system, memory cell therein, except needing enough storages
Space, outside enough data access bandwidths, in addition it is also necessary to can be in whole pixel address of frame in by the pixel data of input picture
Random read-write, this random read-write function are necessary for the full-screen pixels mapping transformation of view data.
Each pixel of output image comes from the data combination of multiple pixels of source image data.Prior art
In, each four pixel of the source images required for output image pixel is adjacent, but its position on source images can
Can be random, so, the address of the source image pixels point provided according to algorithm then reads this purpose pixel from memory
Four required pixel number evidences.
For the storage of high-definition video stream data, pixel rgb value (24bit) of the video flowing per two field picture is by being input into
Four adjacent pixels of image are obtained by multiply-add operation by proportion, i.e., output image pixel data by this algorithm by
Pixel, each pixel for generating output image line by line.That is, often generate a purpose pixel to be required for carrying out four
Secondary data read operation.General source images are stored in sram, when obtaining this four pixels and not only needing the pixel for expending four times
The clock cycle, in addition it is also necessary to which Large Copacity SRAM is storing, and Large Copacity SRAM is expensive, for high-resolution image is processed, special
It is not the storage of pixel DBMS, prior art exists clearly disadvantageous, it is impossible to meet high-resolution video image growing
Demand.
3rd, utility model content
The purpose of this utility model is long for prior art data read cycle, need to be stored with Large Copacity SRAM, valency
The expensive deficiency of lattice, there is provided one kind can reduce data acquisition cycle and time, reduces memory module expense, meets and visits in real time at random
The memory of the high-definition video stream data that asks.
The purpose of this utility model is achieved in that：
The memory of the random real time access of video flowing pixel DBMS be based on high-performance image processing platform application, platform with
FPGA is controller.
Memory is constituted for mutually isostructural two groups of modules, and each group of module is using two pieces of identical data burst read-writes
The QDR2 memory modules combination extension of Burst 2 constitutes block combiner, and two pieces of QDR2 memory modules pass through address bus group, clock
Signal line group, control signal wire group and data bus group are connected in parallel, and control signal is entered simultaneously to two pieces of QDR2 memory modules
Row control.
In each group of memory module combination, setting structure is identical, be exclusively used in each view data accesses by two
The memory cell of data bursts read-write；Two groups of memory modules combination of memory is strange according to adjacent two of view data
Capable, even row is set to strange line storage unit QDR2_1 and even line storage unit QDR2_2, stores strange line number respectively in QDR2_1
According to the even row data of storage in QDR2_2.
In each group of QDR2 memory modules combination, two pieces of QDR2 memory modules are believed by address bus group, clock
Number line group, control signal wire group and data bus group are connected in parallel, and arrange with offline group：
(1) three groups of clock cable group：C1_qdr_c [0], c1_qdr_c_n [0] are to read differential clocks；c1_qdr_cq
[0], c1_qdr_cq_n [0] is to read effective differential clocks；C1_qdr_k [0], c1_qdr_k_n [0] are read/write address, read-write control
Differential clocks processed；
(2) two groups of data/address bus group；c1_qdr_d[0:35] it is 36 input datas, c1_qdr_q [0:35] be 36 defeated
Go out data；
(3) a group of address bus group：c1_qdr_sa[20:0], due to two data bursts read-write (Burst2) the characteristics of,
The highway width of 4M address spaces is 21；
(4) a group of control signal：C1_qdr_bw_n [0], c1_qdr_bw_n [1], c1_qdr_bw_n [2] c1_qdr_
Bw_n [3] is byte effective control, and each byte is 9 bit positions, two panels QDR2 corresponding low 18 data and high 18 digit respectively
According to；C1_qdr_r_n is read control signal；C1_qdr_w_n is write control signal.
QDR2 memory module combination of each group of block combiner using two pieces of identical data burst read-write Burst 2
Extension is constituted, and each piece of QDR2 memory modules space size is 4M × 18bit, and the space size of each group of QDR2 memory module is
4M × 36bit, the storage space size of two groups of block combiner compositions is 4M × 72bit, and data access bandwidth is 36bit × 2
× 2 × 300MHz=43.2Gbps；
Each strange row, the memory space of even line storage unit storage meet 3 pixel datas of pixel data structure identical,
Requirement of each pixel data structure bit wide for 24bit.
Good effect of the present utility model is：
1st, the utility model memory the combination of two groups of memory modules respectively according to two adjacent strange rows of view data,
Even row is set to strange line storage unit QDR2_1 and even line storage unit QDR2_2, stores strange row data in QDR2_1,
Even row data are stored in QDR2_2, are guaranteed the read-write of 2 burst modes of Burst effectively, and then are combined this storage organization, realize
With a pixel clock period, 4 pixel values are read while write.
2nd, by the way of the strange row of view data, even row are stored respectively, data access is in not waste bandwidth for the utility model
In the case of resource, memory space is fully used, and reduces storage space and takes.
3rd, using the composition memory module combination of QDR2 memory modules, combined by two groups of memory modules and constitute memory, solved
Prior art is conducive to market development using Large Copacity SRAM expensive problems.
4th, illustrate
Fig. 1 is that four pixel numbers arrange situation according to the position in source images in prior art.
Fig. 2 is memory construction schematic diagram of the present utility model.
Fig. 3-Fig. 4 is the side circuit schematic diagram of the utility model QDR2 memory modules combination.
5th, specific embodiment
The size and bandwidth of the memory space of memory module have relation with the resolution ratio of video flowing, refresh rate index.Pressing should
With video streaming image ultimate resolution 2560 × 1600,60Hz refresh rate requisite spaces：2560 × 1600 × 3 × 8bits=
93.75Mbits, the space needed for by the way of the ping-pong buffer double as 187.5Mbits.Video stream data desire bandwidth：
2560 × 1600 × 60 × 24 (bit) × 4 (4 pixels)=23.6Gbps.
Referring to accompanying drawing 1.
In prior art, to the random real time access of video flowing pixel DBMS, required for each output image pixel
Four pixels of source images be adjacent, but its position on source images be probably random.So, according to source image pixels
The address of point, reads this four pixel number evidence required for purpose pixel from memory.Four pixel numbers are according in source
If the position arrangement situation in image is as shown in figure 1, two adjacent side by side up and down pixels of each reading, often generate one
Purpose pixel is required for carrying out four secondary data read operations.If source images are stored in sram, obtaining this four pixels needs
Expend four times of pixel clock period.In addition, Large Copacity SRAM is expensive, for high-resolution image is processed, conventional
Memory technology is infeasible.
Therefore it provides one kind can reduce the picture number stream storage time cycle, reduce memory module expense, meet random real-time
The memory of the high-definition video stream data of access is very necessary.
Referring to accompanying drawing 2.
The memory of the random real time access of video flowing pixel DBMS of the present utility model is based on patting at high-performance image
Platform application, platform is with FPGA as controller.Memory is covered from the two sets of data buses for having read-write independent, 36bit/, clock
Double sampled, 300MHz, and the QDR2 memories of Burst 2 are read and write by two data bursts.Obviously, the two of this burst read-write
Individual data are exactly corresponding two neighboring pixel.
Memory is constituted for mutually isostructural two groups of block combiners, and each group of module is read using two pieces of identical data bursts
The QDR2 memory modules combination extension for writing Burst 2 constitutes block combiner, two pieces of QDR2 memory modules by address bus group, when
Clock signal line group, control signal wire group and data bus group are connected in parallel, control signal to two pieces of QDR2 memory modules simultaneously
It is controlled.
In each group of memory module combination, setting structure is identical, be exclusively used in each view data accesses by two
The memory cell of data bursts read-write.Two groups of memory modules combination of memory is respectively according to adjacent two of view data
Strange row, even row are set to strange line storage unit QDR2_1 and even line storage unit QDR2_2, store strange row respectively in QDR2_1
Data, store even row data in QDR2_2.Meanwhile, two groups of memory modules store odd frame one by the way of ping-pong buffer respectively
Half view data, the even frame half view data of storage, and concurrent working.
Referring to accompanying drawing 3-4.
In the combination of each group of QDR2 memory module, by address bus group, clock cable group, control signal wire group and
Data/address bus group is connected in parallel.
The present embodiment is arranged with offline group：
(1) three groups of clock cable group：C1_qdr_c [0], c1_qdr_c_n [0] are to read differential clocks；c1_qdr_cq
[0], c1_qdr_cq_n [0] is to read effective differential clocks；C1_qdr_k [0], c1_qdr_k_n [0] are read/write address, read-write control
Differential clocks processed；
(2) two groups of data/address bus group；c1_qdr_d[0:35] it is 36 input datas, c1_qdr_q [0:35] be 36 defeated
Go out data；
(3) a group of address bus group：c1_qdr_sa[20:0], due to the spy of two data bursts read-write (Burst 2)
Point, the highway width of 4M address spaces is 21；
(4) a group of control signal：C1_qdr_bw_n [0], c1_qdr_bw_n [1], c1_qdr_bw_n [2] c1_qdr_
Bw_n [3] is byte effective control, and each byte is 9 bit positions, two panels QDR2 corresponding low 18 data and high 18 digit respectively
According to；C1_qdr_r_n is read control signal；C1_qdr_w_n is write control signal.
By with group of reaching the standard grade, by two pieces of QDR2 and a memory module combination is unified into, structures are combined using two groups of memory modules
Into memory of the present utility model.
QDR2 memory module combination extension structure of one group of block combiner using two pieces of identical data burst read-write Burst 2
Into each piece of QDR2 memory modules space size is 4M × 18bit, and the space size of each group of QDR2 memory modules combination is 4M
× 36bit, the storage space size of two groups of block combiners composition is 4M × 72bit=288Mbits, and data access bandwidth is
36bit × 2 × 2 × 300MHz=43.2Gbps.The size and bandwidth of the memory space of memory meets application requirement, it is possible to
Other resolution image data storage demands backward compatible.
The characteristics of this memory cell using redundancy storage bit wide space can redundant storage every time a pixel data,
To guarantee the read-write of 2 burst modes of each Burst effectively, and then this memory hardware structure is combined, when realizing with a pixel
In the clock cycle, 4 pixel values are read while write, meet the application requirement of the random real time access of high-definition video stream pixel DBMS.
From the foregoing, it will be observed that the data access of QDR memory cell is in the case of without waste bandwidth resource, memory space makes full use of.
Claims (3)
1. the memory of the random real time access of a kind of video flowing pixel DBMS, it is characterised in that：Video flowing pixel DBMS with
The memory of machine real time access is based on high-performance image processing platform application, and platform is with FPGA as controller；
Memory is constituted for mutually isostructural two groups of block combiners, and each group of module is using two pieces of identical data burst read-writes
The QDR2 memory modules combination extension of Burst 2 constitutes block combiner, and two pieces of QDR2 memory modules pass through address bus group, clock
Signal line group, control signal wire group and data bus group are connected in parallel, and control signal is entered simultaneously to two pieces of QDR2 memory modules
Row control；
In each group of memory module combination, setting structure is identical, be exclusively used in each view data accesses by two data
The memory cell of burst mode read-write；Two groups of memory modules combination of memory is strange according to adjacent two of view data respectively
Capable, even row is set to strange line storage unit QDR2_1 and even line storage unit QDR2_2, respectively in strange line storage unit QDR2_1
The strange row data of middle storage, store even row data in even line storage unit QDR2_2.
2. memory as claimed in claim 1, it is characterised in that：In each group of QDR2 memory modules combination, described two pieces
QDR2 memory modules are connected in parallel by address bus group, clock cable group, control signal wire group and data bus group, if
Put with offline group of connection：
(1) three groups of clock cable group：C1_qdr_c [0], c1_qdr_c_n [0] are to read differential clocks；C1_qdr_cq [0],
C1_qdr_cq_n [0] is to read effective differential clocks；C1_qdr_k [0], c1_qdr_k_n [0] are that read/write address, Read-write Catrol are poor
Timesharing clock；
(2) two groups of data/address bus group；c1_qdr_d[0:35] it is 36 input datas, c1_qdr_q [0:35] it is 36 output numbers
According to；
(3) a group of address bus group：c1_qdr_sa[20:0], due to having two data burst read-write Burst2 the characteristics of, 4M
The highway width of address space is 21；
(4) a group of control signal：C1_qdr_bw_n [0], c1_qdr_bw_n [1], c1_qdr_bw_n [2] c1_qdr_bw_n
[3] it is byte effective control, each byte is 9 bit positions, two panels QDR2 corresponding low 18 data and high 18 data respectively；
C1_qdr_r_n is read control signal；C1_qdr_w_n is write control signal.
3. memory as claimed in claim 1, it is characterised in that：The each group of block combiner adopts two pieces of identical data
The QDR2 memory modules combination extension of burst read-write Burst 2 is constituted, each piece of QDR2 memory modules space size be 4M ×
18bit, the space size of each group of QDR2 memory module is 4M × 36bit, and the storage space of two groups of block combiner compositions is big
Little for 4M × 72bit, data access bandwidth is 36bit × 2 × 2 × 300MHz=43.2Gbps；
Each strange row, the memory space of even line storage unit storage meet 3 pixel datas of pixel data structure identical, each
Requirement of the pixel data structure bit wide for 24bit.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106201363A (en) * | 2016-07-26 | 2016-12-07 | 四川大学 | The memorizer of the random real time access of video flowing Pixel-level data and storage method |
| CN111355914A (en) * | 2018-12-24 | 2020-06-30 | 珠海格力电器股份有限公司 | Video system signal generating device and method |
-
2016
- 2016-07-26 CN CN201620794469.1U patent/CN206021233U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106201363A (en) * | 2016-07-26 | 2016-12-07 | 四川大学 | The memorizer of the random real time access of video flowing Pixel-level data and storage method |
| CN111355914A (en) * | 2018-12-24 | 2020-06-30 | 珠海格力电器股份有限公司 | Video system signal generating device and method |
| CN111355914B (en) * | 2018-12-24 | 2021-09-21 | 珠海格力电器股份有限公司 | Video system signal generating device and method |
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Granted publication date: 20170315 Termination date: 20200726 |