CN111326570A - 一种新型键合硅片及其制备方法 - Google Patents

一种新型键合硅片及其制备方法 Download PDF

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CN111326570A
CN111326570A CN202010219325.4A CN202010219325A CN111326570A CN 111326570 A CN111326570 A CN 111326570A CN 202010219325 A CN202010219325 A CN 202010219325A CN 111326570 A CN111326570 A CN 111326570A
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silicon wafer
diffusion
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杨朔
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Shanghai Anwei Electronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

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Abstract

本发明的主要目的为提供一种新型键合硅片及其制备方法，此方法采用衬底硅片和浅结扩散硅片键合替代成本高的外延片或深结扩散片，降低成本。制造过程采用对有源区硅片先进行扩散，再直接键合衬底硅片作为支撑，减少高低浓度过渡区，如图结构，硅片由高浓度衬底片10和扩散硅片30两部分直接键合而成，键合区20厚度小于2nm，扩散片30分为高浓扩散区31，过渡区32，低浓度有源区33组成。此种硅片可广泛用于垂直导通的半导体器件，降低成本，又保证低正向压降。

Description

一种新型键合硅片及其制备方法
技术领域
本发明属于硅片及其制备的技术领域，特别是涉及一种不用外延低成本而 用键合方式形成多层浓度硅片及其制备方法。
背景技术
上述所用的基片生长的方法通常有三种方式：1.外延生长。在高浓度的高 纯度的单晶片上通过外延生长的方式，此种方式简单，生长的外延层和衬底浓 度过渡区窄，使导通电阻小。缺点是生长成本高，特别是厚外延，随着厚度增 加，成本也增加；制作的器件的反向电压的耐压和反向漏电方面都不如单晶片； 所使用的衬底质量要求高。2.三重扩散生长方式。在单晶片上双面扩散高浓度杂 质，如扩磷形成N+/扩鹏形成P+层，然后经过高温长时间扩散，为了达到支撑 作用的厚度，结深通常达到150um以上，则需要高温如1280℃一周以上时间， 再进行单面减薄抛光。优点是制造成本低，单晶层质量好；缺点是形成的过渡区宽，通常大于50um,导致导通电阻大；扩散周期长；单晶质量要求高。3.直接 硅片键合方式：通过将两硅片直接键合，形成N-/N+或P-/P+型。优点成本低， 缺点是当上层硅片低于10um,在减薄抛光时容易脱落或碎片。
发明内容
本发明的主要目的为提供一种新型键合硅片及其制备方法，此方法采用 衬底硅片和浅结扩散硅片键合替代成本高的外延片或深结扩散片，降低成本， 易于减薄等。制造过程采用对有源区硅片先进行扩散，再直接键合衬底硅片作 为支撑，减少高低浓度过渡区，如图2结构，硅片由高浓度衬底片10和扩散硅 片30两部分直接键合而成，键合区20厚度小于2nm，扩散片30分为高浓 散区31，过渡区32，低浓度有源区33组成。
衬底片为高浓度层，以降低导通电阻；扩散硅片分为高浓扩散区，过渡区， 低浓度有源区组成。过渡区宽度为1-20um.键合区的氧化层厚度低于2nm.衬底 片可采用半导体级纯度单晶片，也可采用太阳能光伏级别纯度单晶片。
本发明的键合硅片的制备方法，其步骤包括：先扩散上硅片，形成高浓度 区和过渡区，再对扩散和衬底片的抛光面相对进行直接键合，然后对扩散减薄 抛光，形成根据器件需要的低浓度区。
扩散形成的过渡层宽度与高浓度层深度密切相关，结深越深则过渡区越 宽。当希望减少过渡区宽度时，要尽可能减少高浓度层结深。如图3所示的过 渡区比较。1为外延方式生长的基片，过渡区最窄；2为本发明的键合扩散硅片， 过渡略宽于外延片，但可控制在较适当的范围；3为深扩散片，过渡区宽。
本发明的基片通过直接键合高浓度衬底片来作为支撑，通常后续芯片加工 的基片厚度要大于450um,本发明的衬底片要大于450um,避免碎片。衬底片因 不参与有源区电场分布等功能，可以使用更低成本的低纯度单晶片，如 99.9999％纯度的太阳能光伏级别片。扩散片部分，高浓度扩散区扩散结深可以 降低至几微米级，使过渡区可低至1um。根据不同器件的需求，如高反压器件， 低阻区要求厚度高，如600V器件，厚度达到50um以上，过渡区希望宽些，达到 场终止穿通结构，增加耐压能力，同时降低导通电阻，则增加高浓度区结深，来增 加过渡区宽度，但宽度不超过20um.因此扩散区结深不超过50um，以保证过渡区低于20um。
本发明新型键合硅片制备方法，其步骤包括：N+/P+型衬底片—单面抛光 ---N-/P-型单晶片---单面抛光---扩散高浓度N+/P+层---两片抛光面贴合—低温100-200℃烘烤2小时以上--高温1000℃以上键合2小时—扩散片减薄--抛光
所述的键合硅片键合采用低温处理和高温键合两步，抛光面避免有氧化层， 氧化层厚度低于2nm，载流子以隧道穿通的方式直接通过，不产生阻挡.
通过此方案的键合基片片和采用外延方法制作的基片比较，材料成本降低 50％以上，正向压降和反向漏电流也有所降低。
附图说明
图1标准基片的结构示意图。10：高浓度的衬底片；21：过渡层；22： 低浓度层
图2本发明的键合型扩散基片示意图。10：高浓度的衬底片；20：键合区； 31：高浓度的扩散层；32：过渡区；33：低浓度的单晶片。
图3过渡区比较示意图。1为外延方式生长的基片，过渡区最窄；2为本 发明的键合扩散硅片，过渡略宽于外延片，但可控制在较适当的范 围；3为深扩散片，过渡区宽。
图4实施例I-V曲线示意图。
具体实施方式
以下通过具体实施例对本发明作进一步说明，但实施例并不限制本发明的 保护范围。
实施例
取一片单面抛光的N-型单晶片(电阻率2Ω.cm，厚度300um)，在1100℃ 通POCL3扩散源30分钟，令取一片N+型的单晶片(电阻率<5E-3Ω.cm，厚度 450um)单面抛光，进行RCA清洗，漂DHF，甩干，将两片抛光面贴合，在 200℃烘箱烘2小时，再放入扩散炉中1100℃2小时，减薄抛光至N-区厚度为 8um.所得的扩散区为6um，过渡区宽度近2um。
用上述的基片制作肖特基二极管，采用通用的平面肖特基二极管制作方法， 如图4所示，所得二极管反向截止(击穿)电压135V，反向漏电流1uA,正向 压降0.75V.和用外延方法所制的基片相比较，反向电压和反向漏电流键合片更 优，正向压降相当。
当然，本技术领域中的普通技术人员应当认识到，以上的实施例仅是用来 说明本发明，而并非作为对本发明的限定，只要在本发明的实质精神范围内， 对以上所述实施例的变化、变形都将落在本发明权利要求书的范围内。

Claims (5)

1.一种新型键合硅片，其结构包括：硅片由高浓度衬底片、扩散硅片直接键合而成。
2.根据权利要求1所述的新型键合硅片，其特征在于，衬底片为高浓度层，以降低导通电阻；扩散硅片分为高浓扩散区，过渡区，低浓度有源区组成。过渡区宽度为1-20um.键合区的氧化层厚度低于2nm.衬底片可采用半导体级纯度单晶片，也可采用太阳能光伏级别纯度单晶片。
3.一种新型键合硅片的制备方法，其步骤包括：先扩散上硅片，形成高浓度区和过渡区，再对扩散和衬底片的抛光面相对进行直接键合，然后对扩散减薄抛光，形成根据器件需要的低浓度区。
4.根据权利要求3所述的键合硅片制备方法，其特征在于，高温形成高浓度扩散区，扩散区宽度不超过50um，以保证过渡区低于20um。
5.根据权利要求3所述的键合硅片键合采用低温处理和高温键合两步，抛光面避免有氧化层，氧化层厚度低于2nm。
CN202010219325.4A 2020-05-12 2020-05-12 一种新型键合硅片及其制备方法 Pending CN111326570A (zh)

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