CN111279474B - 具有分层保护机制的半导体装置及相关***、装置及方法 - Google Patents

具有分层保护机制的半导体装置及相关***、装置及方法 Download PDF

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CN111279474B
CN111279474B CN201880069079.XA CN201880069079A CN111279474B CN 111279474 B CN111279474 B CN 111279474B CN 201880069079 A CN201880069079 A CN 201880069079A CN 111279474 B CN111279474 B CN 111279474B
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enclosure
die
substrate
metal
semiconductor device
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CN111279474A (zh
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卫·周
B·K·施特雷特
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Micron Technology Inc
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Micron Technology Inc
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Abstract

一种半导体装置包含：第一裸片；第二裸片，其经附接于所述第一裸片上方；第一金属围封壳及第二金属围封壳，其两者直接接触所述第一裸片及所述第二裸片，且在所述第一裸片与所述第二裸片之间垂直延伸，其中所述第一金属围封壳***地环绕一组一或多个内部互连件，且所述第二金属围封壳***地环绕所述第一金属围封壳而未直接接触所述第一金属围封壳；第一围封壳连接器，其将所述第一金属围封壳电连接到第一电压电平；第二围封壳连接器，其将所述第二金属围封壳电连接到第二电压电平；且其中所述第一金属围封壳、所述第二金属围封壳、所述第一围封壳连接器及所述第二围封壳连接器经配置以提供围封电容。

Description

具有分层保护机制的半导体装置及相关***、装置及方法
相关申请案
本申请案含有与周伟(Wei Zhou)、布雷特·斯特里特(Bret Street)及马克·塔特尔(Mark Tuttle)的标题为“具有保护机制的半导体装置及相关***、装置及方法(SEMICONDUCTOR DEVICE WITH A PROTECTION MECHANISM AND ASSOCIATED SYSTEMS,DEVICES,AND METHODS)”的先前申请的美国专利申请案相关的标的物。相关申请案经让与给美光科技公司(Micron Technology,Inc.)，且由2017年8月31日申请的第15/693,230号申请案识别。所述申请案的标的物以引用的方式并入本文中。
本申请案含有与周伟及布雷特·斯特里特的标题为“具有电耦合保护机制的半导体装置及相关***、装置及方法(SEMICONDUCTOR DEVICE WITH AN ELECTRICALLY-COUPLEDPROTECTION MECHANISM AND ASSOCIATED SYSTEMS,DEVICES,AND METHODS)”的同时申请的美国专利申请案相关的标的物。相关申请案经让与给美光科技公司，且由档案号010829-9263.US00识别。所述申请案的标的物以引用的方式并入本文中。
技术领域
本技术涉及半导体装置，且特定来说涉及具有分层保护机制的半导体装置。
背景技术
半导体装置裸片(包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装于另一结构(例如，衬底、另一裸片等)上且包在塑料保护罩中的半导体裸片。裸片包含例如用于存储器单元、处理器电路及成像器装置的功能特征以及电连接到功能特征的互连件。互连件可电连接到保护罩外部的端子以将裸片连接到较高级电路。
如图1中说明，半导体装置100(例如，三维互连(3DI)类型的装置或半导体封装装置)可包含其上具有裸片互连件104的裸片102，裸片102连接到其上具有衬底互连件108的衬底结构106(例如，印刷电路板(PCB)、半导体或晶片级衬底、另一裸片等)。裸片102及衬底结构106可通过裸片互连件104及衬底互连件108彼此电耦合。此外，裸片互连件104及衬底互连件108可(例如，通过接合工艺，例如扩散接合或混合接合)彼此直接接触或通过中间结构(例如，焊料)接触。半导体装置100可进一步包含囊封剂(例如底胶填充110)，所述囊封剂包围或囊封裸片102、裸片互连件104、衬底结构106、衬底互连件108、其一部分或其组合。
随着其它领域的技术进步及增加的应用，市场一直在寻找更快且更小的装置。为了满足市场需求，半导体装置的物理大小或尺寸正在被推向极限。举例来说，正努力减小裸片102与衬底结构106之间的分离距离(例如，针对3DI装置及裸片堆叠封装)。
然而，归因于各种因素(例如，底胶填充110的粘度电平、陷留空气/气体、底胶填充110的不均匀流动、互连件之间的空间等)，囊封工艺可能不可靠，例如在裸片102与衬底结构106之间留下空隙114(例如，其中互连件的部分未能直接接触底胶填充110)。空隙114可能引起互连件之间(例如，衬底互连件108之间及/或裸片互连件104之间)的短路及泄漏而引起半导体装置100的电气故障。此外，由于装置越来越小，制造成本可增长(例如，基于使用纳米粒子底胶填充而非传统底胶填充)。
附图说明
图1是半导体装置的横截面视图。
图2是根据本技术的实施例的半导体装置的平面图。
图3是根据本技术的实施例的沿图2的线2--2取得的半导体装置的横截面视图。
图4是根据本技术的实施例的半导体装置的平面图。
图5是根据本技术的实施例的沿图4的线4--4取得的半导体装置的横截面视图。
图6是根据本技术的实施例的半导体装置的平面图。
图7是根据本技术的实施例的沿图6的线6--6取得的半导体装置的横截面视图。
图8到11是说明根据本技术的实施例的在制造方法中的选定阶段处的半导体装置的横截面视图。
图12是说明根据本技术的实施例的制造半导体装置的实例方法的流程图。
图13是说明根据本技术的实施例的并入半导体装置的***的框图。
具体实施方式
本文中揭示的技术涉及半导体装置、具有半导体装置的***及用于制造半导体装置的相关方法。术语“半导体装置”一般指代包含一或多个半导体材料的固态装置。半导体装置的实例包含逻辑装置、存储器装置及二极管等。此外，术语“半导体装置”可指代成品装置或在成为成品装置之前的各个处理阶段处的组合件或其它结构。取决于使用其内容背景，术语“衬底”可指代支撑电子组件(例如，裸片)的结构，例如晶片级衬底或单粒化裸片级衬底、用于裸片堆叠或3DI应用的另一裸片，或印刷电路板(PCB)。所属领域的一般技术人员将认识到，可在晶片级或裸片级执行本文中描述的方法的合适步骤。此外，除非上下文另有指示，否则本文中揭示的结构可使用常规半导体制造技术形成。可例如使用化学气相沉积、物理气相沉积、原子层沉积、旋涂及/或其它合适技术来沉积材料。类似地，可例如使用等离子体蚀刻、湿式蚀刻、化学-机械平坦化或其它合适技术来移除材料。
下文在保护半导体裸片及相关电连接且进一步利用保护结构来提供包围有效信号(active signal)的电容例如用于屏蔽有效信号的内容背景中描述本技术的许多实施例。举例来说，半导体装置(例如，3DI封装解决方案)可各自包含其上具有裸片互连件的一或多个半导体裸片，所述一或多个半导体裸片连接到衬底结构(例如，PCB或另一裸片)。为保护裸片及裸片互连件(例如，针对环境因素，例如水分、碎屑等)，半导体装置可各自包含沿水平面包围裸片互连件的多个金属(例如，铜、铝、合金等)围封壳。金属围封壳可进一步在裸片与衬底之间垂直延伸及/或直接接触裸片及衬底，以围封裸片互连件且将裸片互连件与外部环境隔离。因而，半导体装置可使用金属围封壳代替任何囊封剂(例如，底胶填充)以将裸片互连件与周围外部空间及/或环境隔离。
对于包围一组裸片互连件的一组金属围封壳，第一金属围封壳可包围裸片互连件且一或多个围封壳(例如，第二金属围封壳)可包围第一金属围封壳而未直接接触第一金属围封壳。在一些实施例中，所述组金属围封壳可同心地布置。在一些实施例中，所述组金属围封壳可为非同心的。
所述组金属围封壳可经配置以提供电容电平。在一些实施例中，半导体装置可包含根据一组中的一对相邻金属围封壳之间的围封壳分离距离的围封壳分离空间。在一些实施例中，围封壳分离空间可填充有直接接触相邻金属围封壳的电介质材料(例如，形成电介质层)。分离空间及/或电介质材料可提供包围进行通过裸片互连件的有效信号的电容电平。举例来说，金属围封壳中的一或多者可电连接到第一电压电平(例如，接地)且其它金属围封壳中的一或多者可电连接到第二电压电平(例如，供应电压)。因此，电力输送可通过围封电容改进。此外，环境保护及电屏蔽可基于分层金属围封壳而改进。
在一些实施例中，半导体装置可包含各自包含多个裸片的一或多个裸片堆叠。裸片堆叠可各自包含安置于一对相邻裸片之间的一组金属围封壳。不同对的相邻裸片之间的每一层金属围封壳(例如，最***封壳、最内围封壳、第一中间围封壳等)可例如使用硅穿孔(TSV)、导电膏、导线(例如，接合导线)或其组合电连接。
此外，一或多个金属围封壳可经电耦合以传导电信号或电势(例如，用于提供接地连接或源电压)。在一些实施例中，最外金属围封壳可(例如，经由直接接触或通过另一导体)连接到电磁干扰(EMI)屏蔽。在一些实施例中，第一金属围封壳及第二金属围封壳中的一者或两者可经接地。在一些实施例中，第一金属围封壳及第二金属围封壳可替代地连接到电源及接地(例如，将最外环接地)。
如本文中使用，术语“垂直”、“横向”、“上”及“下”可指代鉴于图中展示的定向，半导体裸片组合件中的特征部的相对方向或位置。举例来说，“上”或“最上”可指代定位成比另一特征部更靠近页面的顶部的特征部。然而，这些术语应广义地解释为包含具有其它定向(例如倒转或倾斜定向)的半导体装置，其中取决于定向，顶部/底部、上/下、上方/下方、向上/向下及左/右可互换。
图2是根据本技术的实施例的半导体装置200(例如，半导体裸片组合件，其包含3DI装置或裸片堆叠封装)的平面图。半导体装置200可包含安装于衬底(例如，另一裸片或PCB)上或连接到所述衬底的一或多个半导体裸片。举例来说，半导体装置200可包含半导体裸片202(“裸片202”)。在裸片之间(例如在裸片202上方及/或下方)，半导体装置200可包含经配置以直接连接且电耦合结构(例如，裸片及/或PCB)的内部互连件218。在一些实施例中，内部互连件218可为源自接合或结合(例如，例如通过扩散接合或混合接合)柱、垫或互连结构的结构。
半导体装置200可进一步包含沿平面包围/环绕内部互连件218的***(periphery)或周边(perimeter)的一或多个金属(例如，铜、铝、合金等)围封壳。举例来说，半导体装置200可包含至少一第一金属围封壳220(“第一围封壳220”)及第二金属围封壳222(“第二围封壳222”)。在一些实施例中，第一围封壳220可为包围内部互连件218的内部围封壳，且第二围封壳222可包围第一围封壳220，其两者都沿水平面。第一围封壳220可嵌套于第二围封壳222内而彼此未直接接触。
第一围封壳220及第二围封壳222各自可为形成***地包围内部互连件218的壁的连续及固体金属(例如铜或焊料)结构。在一些实施例中，第一围封壳220及第二围封壳222(例如，固体铜或焊料结构)可通过接合工艺(例如，扩散接合工艺、热压缩接合、批量回焊(mass reflow)等)形成。在一些实施例中，第一围封壳220及第二围封壳222可各自具有小于或等于20μm的垂直尺寸或高度。在一些实施例中，第一围封壳220及第二围封壳222可同心地布置。在一些实施例中，围封壳可包含可通过热压缩接合或批量回焊而接合的焊料。
在裸片之间或在裸片与PCB衬底之间，第一围封壳220、第二围封壳222或其组合可用作内部空间224(“经围封空间224”)的水平或***边界(例如，例如沿水平面标记***边缘的垂直结构/平面)。经围封空间224可为真空的或填充有惰性/特定气体及/或其它电介质材料，只有内部互连件218除外(例如，其中无任何囊封剂材料或底胶填充)。因此，第一围封壳220及/或第二围封壳222可将内部互连件218与围封壳的相对侧上的外部空间隔离。
在一些实施例中，一对围封壳(例如，第一围封壳220及第二围封壳222)可由围封壳分离空间226分离。举例来说，围封壳分离空间226可为第一围封壳220与第二围封壳222之间的空间。如图2中说明，经围封空间224可为第一围封壳220内的空间，且围封壳分离空间226可为包围第一围封壳220的空间，其中第二围封壳222形成***边界。在一些实施例中，经围封空间224可为由第二围封壳222包围的空间，且围封壳分离空间226可为经围封空间224的外部***部分。
在一些实施例中，围封壳(例如，最***封壳，例如如图2中说明的第二围封壳222)可定位于距裸片***边缘240的边缘偏移距离228(例如，沿水平方向测量的距离)处。举例来说，边缘偏移距离228可为裸片***边缘240与第二外表面232(例如，第二围封壳222的外部***表面)之间的沿水平方向的距离。在一些实施例中，最***封壳可经定位，使得其边缘或表面沿垂直平面或线与裸片***边缘240共面或重合(例如，其中边缘偏移距离228为0)。
在一些实施例中，围封壳可分离达围封壳分离距离230。举例来说，围封壳分离距离230可为第二内表面234(例如，第二围封壳222的内部***表面)与第一外表面236(例如，第一围封壳220的外部***表面)之间的沿水平方向的距离。围封壳分离距离230可对应于经围封空间224。
半导体装置200可具有围封壳分离距离230，及经配置以提供围封电容242的围封壳(例如，第一围封壳220及第二围封壳222)。围封电容242可提供包围内部互连件218及/或有效信号的电容。举例来说，围封壳中的一或多者(例如，第二围封壳222或第一围封壳220)可经连接到第一电压电平(例如，接地)，且其它围封壳中的一或多者(例如，第一围封壳220或第二围封壳222)可经连接到第二电压电平(例如，供应电压)。此外，围封电容242可基于围封壳分离距离230及/或围封壳分离空间226中的气体/真空/电介质材料。
分离达围封壳分离距离230且经配置以提供围封电容242的围封壳可改进射频(RF)屏蔽且增加封装级电容。围封电容242还可改进高电流浪涌装置的电路完整性。
围封壳可进一步提供半导体装置的整体大小的减小。因为不需要底胶填充，所以接合线厚度可减小，而导致多裸片堆叠的非常低的封装高度。此外，排除焊料(例如，例如源自Cu-Cu扩散接合的固体铜结构)的围封壳通过消除柱凸块来提供制造成本的减低。此外，排除焊料的围封壳通过提供无焊料帽的清洁接头来移除与焊料桥接、塌陷、匮乏、金属间化合物(IMC)、电磁(EM)效应等相关联的故障模式，从而提供故障率的降低。
本发明还因为封装高度减小而提供制造成本及故障率的减低。围封壳可保护且隔离内部互连件218免受环境因素(例如，水分、碎屑等)的影响，此消除对底胶填充(例如，纳米粒子底胶填充)的需要。因此，可基于使用围封壳取代底胶填充而消除与底胶填充层压或流动工艺相关联的成本及错误率(其两者随着相邻裸片之间的空间减小而迅速增加)。此外，围封壳提供满足先前由底胶填充提供的机械、热及电气特质或优点的接头。
出于阐释性目的，围封壳被展示为具有矩形形状、均匀厚度或宽度且与对应裸片的形状或轮廓同心。然而，应了解，围封壳可为不同的。举例来说，围封壳可具有椭圆形形状、不规则或不对称形状或任何N边多边形形状。此外，举例来说，围封壳可在不同部分处具有变化厚度或宽度。此外，举例来说，围封壳可相对于内部互连件218或其布置、裸片的形状或轮廓或其组合偏移或非同心。
图3是根据本技术的实施例的沿图2的线2--2取得的半导体装置的横截面视图。半导体装置200可包含安装于衬底(例如，另一裸片或PCB)上或连接到所述衬底的一或多个半导体裸片。举例来说，半导体装置200可包含裸片堆叠302，裸片堆叠302包含多个半导体裸片304(“裸片304”)，其中第一围封壳220及第二围封壳222安置于一或多对相邻裸片之间。在一或多对相邻裸片之间，第一围封壳220及/或第二围封壳222可包围经围封空间306(例如，图2的经围封空间224的例子)，且围封壳分离空间308(例如，图2的围封壳分离空间226的例子)可由第一围封壳220及第二围封壳222形成，其两者都沿水平方向。沿垂直方向，对置相邻裸片的第一边界表面322及第二边界表面324可形成经围封空间306及围封壳分离空间308的边界。经围封空间306及/或围封壳分离空间308可为真空的或填充有惰性/特定气体或其它电介质材料，如上文论述。
在一些实施例中，裸片堆叠302可在裸片304中的一或多者中包含用于跨或穿过对应裸片电耦合电路/组件的TSV。内部互连件218可(例如，通过直接接触及/或通过另一电导体，例如迹线)连接到一或多个TSV，例如内部TSV及/或***TSV。此外，一或多个TSV可将一或多个金属围封壳电连接到电信号或电势(例如，电接地或供应电压)。
举例来说，裸片中的一或多者可包含定位于对应裸片的***部分上的一或多个第一***TSV 342及/或一或多个第二***TSV 344。第一***TSV 342及第二***TSV 344可用于跨裸片电耦合第一围封壳220及/或第二围封壳222及/或将第一围封壳220及/或第二围封壳222电耦合到电信号/电势。如图3中说明，第一***TSV 342可跨裸片直接接触并电耦合(例如，例如通过穿过所述裸片而电连接)第一围封壳220的例子，且第二***TSV 344可跨裸片直接接触并电耦合第二围封壳222的例子。此外，举例来说，裸片中的一或多者可包含定位于对应裸片的内部或中心部分上的一或多个内部TSV 346。如图3中说明，内部TSV346可跨裸片直接接触并电耦合内部互连件218的例子。
半导体装置200可包含附接到装置衬底362(例如，PCB)或附接于装置衬底362上方的裸片堆叠302。装置衬底362可包含用于电耦合到裸片堆叠302的接合垫366。举例来说，半导体装置200可包含直接接触接合垫366及TSV中的一或多者以将裸片堆叠302电耦合到装置衬底362及/或其它电组件/电路的装置互连件364(例如，焊料)。在一些实施例中，装置互连件364可嵌入于安置于裸片堆叠302的底表面与装置衬底362的顶表面之间的底胶填充/囊封剂368(“底胶填充368”)中。在一些实施例中，一或多个金属围封壳可取代底胶填充368，及/或内部互连件218可取代装置互连件364。
在一些实施例中，TSV可将围封壳电连接成组。举例来说，裸片堆叠302可包含第一裸片372(例如，最下方裸片，例如直接接触装置互连件364、底胶填充368等的裸片)、附接于第一裸片372正上方的第二裸片374、附接于第二裸片374正上方的第三裸片376等。半导体装置200可包含介于第一裸片372与第二裸片374之间的第一层级围封壳群组382(例如，第一围封壳220及第二围封壳222)、第二层级围封壳群组384(例如，额外/第二组的第一围封壳220及第二围封壳222)等。
针对此布置，第一***TSV 342可沿垂直方向连接一或多个内部围封壳(例如，第一围封壳220的例子)，且第二***TSV 344可沿垂直方向连接一或多个外部/***围封壳(例如，第二围封壳222的例子)。在一些实施例中，裸片堆叠中的全部垂直对应围封壳可电连接在一起。举例来说，全部内部围封壳可例如使用第一***TSV 342电耦合在一起，及/或全部外部围封壳可例如使用第二***TSV 344电耦合在一起。
在一些实施例中，围封壳可经对准用于垂直连接。举例来说，跨不同层级围封壳群组的内部围封壳的中心部分及/或***边缘/部分/表面可沿垂直线/平面重合。此外，举例来说，跨不同层级围封壳群组的外部围封壳的中心部分及/或***边缘/部分/表面可沿垂直线/平面重合。
使用电连接器(例如，迹线、接合垫366、装置互连件364或其组合)及TSV，围封壳可各自连接到电压电平(例如，电接地、供应电压等)。因此，围封壳可用于跨水平方向或跨裸片提供围封电容242。
另外，跨裸片垂直地连接多个围封壳(例如，沿如图3中展示的垂直方向，例如将第一层级围封壳群组382连接到第二层级围封壳群组384)可进一步增加半导体装置200的围封电容242。使用***TSV垂直地连接多个围封壳可增加能够保持电荷的表面积及/或质量。因此，围封电容242及封装级电容可基于跨裸片连接围封壳而增加。因此，垂直连接的围封壳(例如，围封壳的内部组及外部组)可进一步改进RF屏蔽能力。
图4是根据本技术的实施例的半导体装置400(例如，半导体裸片组合件，其包含3DI装置或裸片堆叠封装)的平面图。半导体装置400可类似于图2的半导体装置200，但其具有填充金属围封壳之间的围封壳空间的电介质材料。
举例来说，半导体装置400可包含安装于衬底(例如，另一裸片或PCB)上或连接到所述衬底的一或多个半导体裸片，包含图4中说明的半导体裸片402(“裸片402”)。此外，举例来说，半导体装置400可包含经配置以直接连接且电耦合不同结构(例如，裸片及/或PCB)上的电路的内部互连件418(例如，源自接合或结合(例如通过扩散接合或混合接合)柱、垫或互连结构的结构)。
此外，举例来说，半导体装置400可进一步包含各自形成沿平面包围/环绕内部互连件418的***或周界的壁的一或多个连续及固体金属(例如，铜、铝、合金等)围封壳(例如，第一金属围封壳420(“第一围封壳420”)、第二金属围封壳422(“第二围封壳422”)等)。在一些实施例中，第一围封壳420可为***地包围内部互连件418且嵌套于第二围封壳422内的内部围封壳(例如，经嵌套围封壳)，第二围封壳422***地包围第一围封壳420、其两者都沿水平面。在一些实施例中，第一围封壳420及第二围封壳422(例如，固体铜结构)可通过扩散接合工艺形成。在一些实施例中，第一围封壳420及第二围封壳422可各自具有小于或等于40μm的垂直尺寸或高度。在一些实施例中，第一围封壳420及第二围封壳422可同心地布置。
在裸片之间或在裸片与PCB衬底之间，第一围封壳420、第二围封壳422或其组合可用作内部空间424(“经围封空间424”)的水平或***边界(例如，例如沿水平面标记***边缘的垂直结构/平面)。经围封空间424可为真空的或填充有惰性/特定气体及/或其它电介质材料，只有内部互连件418除外(例如，其中无任何囊封剂材料或底胶填充)。因此，第一围封壳420及/或第二围封壳422可将内部互连件418与围封壳的相对侧上的外部空间隔离。
在一些实施例中，围封壳(例如，最***封壳，例如如图4中说明的第二围封壳422)可定位于距裸片***边缘440的边缘偏移距离428(例如，沿水平方向测量的距离)处。举例来说，边缘偏移距离428可为裸片***边缘440与第二外表面432(例如，第二围封壳422的外部***表面)之间的沿水平方向的距离。在一些实施例中，最***封壳可经定位使得其边缘或表面沿垂直平面或线与裸片***边缘440共面或重合(例如，其中边缘偏移距离428为0)。
在一些实施例中，围封壳可分离达围封壳分离距离430。举例来说，围封壳分离距离430可为第二内表面434(例如，第二围封壳422的内部***表面)与第一外表面436(例如，第一围封壳420的外部***表面)之间的沿水平方向的距离。围封壳分离距离430可对应于经围封空间424。
半导体装置400可具有围封壳分离距离430及经配置以提供围封电容442的围封壳(例如，第一围封壳420及第二围封壳422)。围封电容442可提供包围内部互连件418及/或有效信号的电容。举例来说，围封壳中的一或多者(例如，第二围封壳422或第一围封壳420)可连接到第一电压电平(例如，接地)，且其它围封壳中的一或多者(例如，第一围封壳420或第二围封壳422)可连接到第二电压电平(例如，供应电压)。
在一些实施例中，一对围封壳(例如，第一围封壳420及第二围封壳422)可由围封壳分离空间(例如，第一围封壳420与第二围封壳422之间的空间)分离，所述围封壳分离空间由电介质材料426(例如，可能由施加电场极化的电绝缘体)填充。如图4中说明，电介质材料426可介于第一围封壳420与第二围封壳422之间且直接接触第一围封壳420及第二围封壳422两者。举例来说，电介质材料426可介于第一外表面436与第二内表面434之间且直接接触第一外表面436及第二内表面434。
连同围封壳分离距离430，电介质材料426可经配置以实现围封电容442的所要电平。与使围封壳分离空间为真空或填充有气体相比，第一围封壳420与第二围封壳422之间的电介质材料426可增加围封电容442。
分离达围封壳分离距离430且填充有电介质材料426用于提供围封电容442的围封壳可改进射频(RF)屏蔽且增加封装级电容。围封电容442还可改进高电流浪涌装置的电路完整性。
图5是根据本技术的实施例的沿图4的线4--4取得的半导体装置的横截面视图。类似于图2的半导体装置200，半导体装置400可包含安装于衬底(例如，另一裸片或PCB)上或连接到所述衬底的一或多个半导体裸片。举例来说，半导体装置400可包含裸片堆叠502，裸片堆叠502包含多个半导体裸片504(“裸片504”)，其中第一围封壳420及第二围封壳422安置于一或多对相邻裸片之间。此外，半导体装置400可包含经围封空间506(例如，图4的经围封空间424的例子)及介于一或多对相邻裸片之间的电介质材料508(例如，图4的电介质材料426的例子)。
在一些实施例中，裸片堆叠502可在裸片504中的一或多者中包含用于跨或穿过对应裸片电耦合电路/组件的TSV。举例来说，裸片中的一或多者可包含定位于对应裸片的***部分上的一或多个第一***TSV 542及/或一或多个第二***TSV 544。如图5中说明，第一***TSV 542可跨裸片直接接触并电耦合第一围封壳420的例子，且第二***TSV 544可跨裸片直接接触并电耦合第二围封壳422的例子。此外，举例来说，裸片中的一或多者可包含定位于对应裸片的内部或中心部分上的一或多个内部TSV 546。内部TSV 546可跨裸片直接接触并电耦合内部互连件418的例子。
半导体装置400可包含附接到装置衬底562(例如，PCB)或附接于装置衬底562上方的裸片堆叠502。装置衬底562可包含用于电耦合到裸片堆叠502的接合垫566。举例来说，半导体装置400可包含直接接触接合垫566及TSV中的一或多者以将裸片堆叠502电耦合到装置衬底562及/或其它电组件/电路的装置互连件564(例如，焊料)。在一些实施例中，装置互连件564可嵌入于安置于裸片堆叠502的底表面与装置衬底562的顶表面之间的底胶填充/囊封剂568(“底胶填充568”)中。在一些实施例中，一或多个金属围封壳可取代底胶填充568，及/或内部互连件418可取代装置互连件564。
使用电连接器(例如，迹线、接合垫566、装置互连件564或其组合)及TSV，围封壳可各自连接到电压电平(例如，电接地、供应电压等)。因此，围封壳可用于跨水平方向或跨裸片提供围封电容442。
另外，跨裸片(例如，沿如图5中展示的垂直方向)垂直地连接多个围封壳可进一步增加半导体装置400的围封电容442。使用***TSV垂直地连接多个围封壳可增加能够保持电荷的表面积及/或质量。因此，围封电容442及封装级电容可基于跨裸片连接围封壳而增加。因此，垂直连接的围封壳(例如，围封壳的内部组及外部组)可进一步改进RF屏蔽能力。
图6是根据本技术的实施例的半导体装置600(例如，半导体裸片组合件，其包含3DI装置或裸片堆叠封装)的平面图。半导体装置600可类似于图2的半导体装置200及/或图4的半导体装置400，但其具有嵌套于外部金属围封壳内的多个非重叠内部金属围封壳。
举例来说，半导体装置600可包含经安装于衬底(例如，另一裸片或PCB)上或经连接到所述衬底的一或多个半导体裸片，包含图6中说明的半导体裸片602(“裸片602”)。此外，举例来说，半导体装置600可包含内部互连件，例如源自接合或结合(例如通过扩散接合或混合接合)柱、垫或互连结构的结构。在一些实施例中，半导体装置600可包含经配置以直接连接且电耦合不同结构(例如，裸片及/或PCB)上的电路的单独互连件组，例如第一互连件组604及第二互连件组606。
此外，举例来说，半导体装置600可进一步包含各自形成沿平面(例如，水平面)包围/环绕互连件及/或其它围封壳的***或周界的壁的一或多个连续及固体金属(例如，铜、铝、合金等)围封壳。在一些实施例中，半导体装置600可包含经嵌套于外部围绕金属围封壳(例如，外部围封壳616)内的多个非重叠内部金属围封壳(例如，第一内部围封壳612及第二内部围封壳614)。第一内部围封壳612可包围/环绕第一互连件组604，且第二内部围封壳614可包围/环绕第二互连件组606。外部围封壳616可包围/环绕嵌套于其中的内部围封壳(例如，第一内部围封壳612及第二内部围封壳614)及围封/包围于其中的互连件组(例如，第一互连件组604及第二互连件组606)。
在裸片之间或在裸片与PCB衬底之间，围封壳可用作经围封空间的水平或***边界(例如，例如沿水平面标记***边缘的垂直结构/平面)。外部围封壳可环绕空间，且内部围封壳中可环绕单独及排他空间。举例来说，外部围封壳616可环绕外部经围封空间626。第一内部围封壳612可环绕第一内部空间622，且第二内部围封壳614可环绕与第一内部空间622分离且排他的第二内部空间624。第一内部空间622及第二内部空间624两者可为外部经围封空间626内的空间/部分。
经围封空间可为真空的或经填充有惰性/特定气体(例如，其中无任何囊封剂材料或底胶填充)。在一些实施例中，围封壳之间的经围封空间的部分可经填充有电介质材料(例如，图4的电介质材料426)。因此，围封壳可将互连件与结构的相对侧上的外部空间隔离。
在一些实施例中，内部围封壳可为分离的，而无任何直接接触。在一些实施例中，内部围封壳可经电连接在一起，或共享/重叠其中的部分。在一些实施例中，围封壳(例如，固体铜结构)可通过扩散接合工艺形成。在一些实施例中，围封壳可各自具有小于或等于60μm的垂直尺寸或高度。
在一些实施例中，外部围封壳616可定位成与裸片的***边缘/表面共面。在一些实施例中，外部围封壳616可从***边缘/表面水平偏移，如上文论述。
内部围封壳可与外部围封壳分离达类似于上文论述的围封壳分离距离的一或多个围封壳分离距离。举例来说，第一内部围封壳612可对应于第一分离距离且第二内部围封壳614可对应于第二分离距离，其两者都相对于外部围封壳616。
半导体装置600可具有围封壳分离距离及经配置以提供围封电容642的围封壳。围封电容642可提供各自包围一组内部互连件及/或有效信号的电容。与分离距离、电介质填料等一起，用于围封壳的电连接可经配置以实现包围各组有效信号的围封电容642的所要电平。举例来说，围封壳中的一或多者(例如，外部围封壳616)可连接到第一电压电平(例如，接地)，且其它围封壳中的一或多者(例如，内部围封壳)可连接到不同电压电平(例如，供应电压或不同电压电平)。环绕有效信号/电路的所得电容可改进射频(RF)屏蔽且增加封装级电容。围封电容642还可改进高电流浪涌装置的电路完整性。
图7是根据本技术的实施例的沿图6的线6--6取得的半导体装置的横截面视图。类似于图2的半导体装置200及/或图4的半导体装置400，半导体装置600可包含安装于衬底(例如，另一裸片或PCB)上或连接到所述衬底的一或多个半导体裸片。举例来说，半导体装置600可包含裸片堆叠702，裸片堆叠702包含多个半导体裸片704(“裸片704”)，其中围封壳(例如第一内部围封壳712(例如，图6的第一内部围封壳612的例子)、第二内部围封壳714(例如，图6的第二内部围封壳614的例子)、外部围封壳716(例如，图6的外部围封壳616的例子)等)安置于一或多对相邻裸片之间。此外，半导体装置600可包含介于一或多对相邻裸片之间的经围封空间，例如第一内部空间722(例如，图6的第一内部空间622的例子)、第二内部空间724(图6的第二内部空间624的例子)、外部经围封空间726(图6的外部经围封空间626的例子)等。
在一些实施例中，裸片堆叠702可在裸片704中的一或多者中包含用于跨或穿过对应裸片电耦合电路/组件的TSV。举例来说，裸片中的一或多者可包含一或多个第一围封壳TSV 742、一或多个第二围封壳TSV 744、一或多个外部围封壳TSV 746、一或多个互连件TSV等。第一围封壳TSV 742可跨对应裸片直接接触并电耦合相邻对的第一内部围封壳712，第二围封壳TSV 744可跨对应裸片直接接触并电耦合相邻对的第二内部围封壳714，且外部围封壳TSV 746可跨对应裸片直接接触并电耦合相邻对的外部围封壳716。类似地，互连件TSV可跨裸片直接接触并电耦合对应组的内部互连件。
类似于上文论述的半导体装置。半导体装置600可包含附接到装置衬底(例如，PCB)或附接于所述装置衬底上方的裸片堆叠702。装置衬底可包含用于电耦合到裸片堆叠702的接合垫、装置互连件(例如，焊料)。在一些实施例中，装置互连件可嵌入于安置于裸片堆叠702的底表面与装置衬底的顶表面之间的底胶填充/囊封剂中。在一些实施例中，一或多个金属围封壳可取代底胶填充，及/或内部互连件可取代装置互连件。
使用电连接器(例如，迹线、接合垫、装置互连件或其组合)及TSV，围封壳可各自连接到电压电平(例如，电接地、供应电压等)。因此，围封壳可用于跨水平方向或跨裸片提供围封电容642。
另外，跨裸片(例如，沿如图5中展示的垂直方向)垂直地连接多个围封壳可进一步增加半导体装置400的围封电容442。使用***TSV垂直地连接多个围封壳可增加能够保持电荷的表面积及/或质量。因此，围封电容442及封装级电容可基于跨裸片连接围封壳而增加。因此，垂直连接的围封壳(例如，围封壳的内部组及外部组)可进一步改进RF屏蔽能力。
图8到11是说明根据本技术的实施例的在制造方法中的选定阶段处的半导体装置的横截面视图。如图8中说明，方法可包含用于提供第一裸片802的阶段。第一裸片802可包含在第一裸片底表面下方突出的第一裸片互连件804(例如，例如内部互连件的一部分的用于提供到第一裸片802内的电路的电连接的固体金属结构)。第一裸片802可进一步包含一或多个第一裸片内部围封壳(例如，第一裸片内部围封壳810)及第一裸片外部围封壳811。第一裸片内部围封壳及第一裸片外部围封壳811各自可为例如金属围封壳结构的一部分的固体金属结构。第一裸片内部围封壳可各自沿水平面环绕对应裸片互连件(例如，第一裸片互连件804)的周界，且第一裸片外部围封壳811可沿水平面环绕第一裸片内部围封壳810。
可使用单独制造工艺(例如，晶片或裸片级制造工艺)来制造具有第一裸片互连件804及裸片围封壳的第一裸片802。所述单独制造工艺可根据突出部测量值812(例如，金属结构的高度，例如在裸片底表面与第一裸片互连件804及裸片围封壳的远端部分之间测量的长度)产生第一裸片互连件804及裸片围封壳。在一些实施例中，突出部测量值812可包含小于20μm的距离。根据突出部测量值812，第一裸片互连件804及裸片围封壳的远端部分(例如，相对于裸片底表面)可沿平行于裸片底表面的水平面共面。在一些实施例中，围封壳可包含可通过热压缩接合或批量回焊接合的焊料。
在一些实施例中，单独制造工艺可包含形成直接接触互连件及/或围封壳的一或多个TSV(例如，内部TSV及/或***TSV)。在一些实施例中，可将电介质填料814(例如，电介质环氧树脂或膏)施覆于内部围封壳中的一或多者与外部围封壳之间、内部围封壳之间等。
如图9中说明，方法可包含用于提供衬底906(例如，PCB或另一裸片，例如第二裸片、内部裸片中的一者等)的阶段。衬底906可包含在衬底顶表面上方突出的衬底互连件904(例如，例如内部互连件的一部分的用于提供到衬底906的电连接的固体金属结构)。衬底906可进一步包含一或多个衬底内部围封壳(例如，衬底内部围封壳910)及衬底外部围封壳911。衬底内部围封壳及衬底外部围封壳911各自可为例如金属围封壳结构的一部分的固体金属结构。衬底内部围封壳可各自沿水平面环绕对应衬底互连件(例如，衬底互连件904)的周界，且衬底外部围封壳911可沿水平面环绕衬底内部围封壳。
可使用单独制造工艺(例如，晶片或裸片级制造工艺或用于制造印刷电路板的工艺)制造具有衬底互连件904及衬底围封壳的衬底906。类似于图8中说明的阶段，所述单独制造工艺可根据突出部测量值912(例如，金属结构的高度，例如在第二边界表面与衬底互连件904及衬底围封壳的远端部分之间测量的长度)产生衬底互连件904及衬底围封壳。在一些实施例中，突出部测量值912可包含小于20μm的距离。根据突出部测量值912，衬底互连件904及衬底围封壳的远端部分(例如，相对于衬底顶表面)可沿平行于衬底顶表面的水平面共面。在一些实施例中，围封壳可包含可通过热压缩接合或批量回焊接合的焊料。
在一些实施例中，单独制造工艺可包含形成直接接触互连件及/或围封壳的一或多个TSV(例如，内部TSV及/或***TSV)。在一些实施例中，可将电介质填料914(例如，电介质环氧树脂或膏)施覆于内部围封壳中的一或多者与外部围封壳之间、内部围封壳之间等。
如图10中说明，方法可包含用于对准衬底906及裸片802的阶段。衬底906及裸片802可基于其对准参考部分(例如，中心部分、***边缘或表面等)沿线或平面(例如，图10的垂直线或平面)对准。结构可经对准使得裸片围封壳(例如，第一裸片内部围封壳810及第一裸片外部围封壳811)及衬底围封壳(例如，衬底内部围封壳910及衬底外部围封壳911)沿线或平面(例如，垂直线或平面)对准。此外，结构可经对准使得裸片围封壳及衬底围封壳彼此直接接触。第一裸片互连件804及衬底互连件904可类似地对准。
在一些实施例中，可在对准结构之前硬化或设置围封壳之间的电介质材料。在一些实施例中，可在对准结构的后在围封壳之间施覆电介质材料。
如图11中说明，方法可包含用于接合金属结构(例如，将裸片围封壳接合到衬底围封壳及/或将第一裸片互连件804接合到衬底互连件904)的阶段。举例来说，图11可表示扩散接合工艺1100(例如，Cu-Cu扩散接合)，其包含用于基于固态扩散而结合金属的固态焊接工艺(例如，其在具有或不具有将结构推到一起的压力/力的情况下利用在本质上低于结构的熔点的温度下的聚结)。扩散接合工艺1100可包含产生真空条件或用惰性气体填充空间(例如，经围封空间)、加热金属表面、将金属结构压在一起或其组合。
基于接合阶段，金属结构可接合或熔合且形成连续结构。举例来说，裸片围封壳及衬底围封壳可经接合以形成上文论述的各种内部及外部围封壳。此外，举例来说，可接合第一裸片互连件804及衬底互连件904以形成上文论述的内部互连件。
将裸片围封壳扩散接合到衬底围封壳(例如，Cu-Cu扩散接合)及将第一裸片互连件804与衬底互连件904扩散接合(例如，Cu-Cu扩散接合)提供减少的制造故障及降低的成本。扩散接合工艺可消除焊料，借此减少与焊接工艺相关联的任何潜在故障且降低成本。此外，可使用一个接合工艺接合互连件及围封壳，这可进一步简化制造工艺。
在一些实施例中，接合阶段可包含硬化/固化围封壳之间的电介质材料。举例来说，用于接合阶段的条件/环境可包含固化电介质材料所需的设置温度、施用光或化学试剂、等待等。在一些实施例中，可在接合结构的后(例如，通过在稍后阶段填充的施覆端口/孔)将电介质材料施覆于围封壳之间且进行固化。
图12是说明根据本技术的实施例的制造半导体装置的实例方法1200(“方法1200”)的流程图。举例来说，方法1200可经实施以制造图2及3的半导体装置200、图4及5的半导体装置400及/或图6及7的半导体装置600。此外，举例来说，方法1200可包含图8到11中说明的阶段。
方法1200可包含提供一或多个半导体裸片(例如，图2到7中说明的一或多个裸片)，如框1202处说明。提供半导体裸片可对应于图8中说明的阶段。经提供裸片可包含裸片互连件(例如，图8的第一裸片互连件804)及从裸片底表面向下突出的裸片围封壳(例如，图8的内部围封壳810或图8的外部围封壳811)。裸片围封壳可在裸片底表面上或沿裸片底表面***地包围裸片互连件。经提供裸片可进一步具有与裸片围封壳的底部或远端部分或表面共面的裸片互连件的底部或远端部分或表面。举例来说，裸片互连件及裸片围封壳的底部或远端部分可沿平行于裸片底表面且从裸片底表面垂直偏移达图8的突出部测量值812的水平面共面。
在一些实施例中，裸片围封壳可包含铜、铝、镍、其它金属或其组合。在一些实施例中，裸片围封壳可包含直接接触裸片底表面或直接附接到金属壁结构的远端表面或部分的焊料。在一些实施例中，裸片围封壳中的每一者可电连接到信号或电压电平(例如，例如电压源或接地)。
可使用单独制造工艺制造或形成裸片，如框1220处说明。举例来说，裸片制造工艺可包含晶片级处理，例如用于形成集成电路的掺杂工艺及用于分离个别裸片的单粒化工艺。此外，举例来说，裸片制造工艺可包含形成TSV。
方法1200可进一步包含提供衬底(例如，图9的衬底906)，如框1204处说明。提供衬底可对应于图9中说明的阶段。经提供衬底可包含衬底互连件(例如，图9的衬底互连件904)及从衬底顶表面向上突出的衬底围封壳(例如，图9的内部围封壳910及图9的外部围封壳911)。衬底围封壳可在衬底顶表面上或沿衬底顶表面***地包围衬底互连件。经提供衬底可进一步具有与衬底围封壳的顶部或远端部分或表面共面的衬底互连件的顶部或远端部分或表面。举例来说，衬底互连件及衬底围封壳的顶部或远端部分可沿平行于衬底顶表面且从衬底顶表面垂直偏移达图9的突出部测量值912的水平面共面。
在一些实施例中，衬底围封壳可包含铜、铝、镍、其它金属或其组合。在一些实施例中，衬底围封壳可包含直接接触衬底顶表面或直接附接到金属壁结构的远端表面或部分的焊料。在一些实施例中，衬底围封壳中的每一者可电连接到信号或电压电平(例如，例如电压源或接地)。
可使用单独制造工艺制造或形成衬底，如框1240处说明。举例来说，(例如，用于制造另一裸片的)衬底制造工艺可包含类似于框1220所说明的工艺的晶片级处理。此外，举例来说，(例如，用于制造PCB衬底的)衬底制造工艺可包含焊料掩模塑形、迹线形成、平坦化等。此外，举例来说，衬底制造工艺可包含形成TSV。
方法1200可进一步包含对准结构(例如，裸片及衬底)，如框1206处说明。对准结构可对应于图10中说明的阶段。举例来说，对准工艺可将裸片对准于衬底上方，其中每一裸片互连件的一部分沿垂直线与每一衬底互连件的对应部分重合及/或裸片围封壳的一部分沿垂直线与衬底围封壳重合。此外，举例来说，对准工艺可将裸片对准于衬底上方，其中裸片围封壳直接接触衬底围封壳。
方法1200可进一步包含接合结构(例如，将裸片互连件接合到衬底互连件及/或将裸片围封壳接合到衬底围封壳)，如框1208处说明。接合工艺可对应于图11中说明的阶段。接合工艺可包含控制结构中的一或多者的温度(例如，加热以接合且接着冷却以固化经结合结构)、对结构施加压力或其组合。举例来说，接合工艺可包含如框1212处所说明的扩散接合(例如，热压缩接合或TCB)及/或如框1214处所说明的回焊焊料(例如，在施用焊料的情况中，批量回焊)。
通过接合工艺，可形成围封壳、经围封空间、互连件等。由于金属(例如，铜、焊料等)充分阻挡水分及其它碎屑，因此制造工艺不再需要底胶填充。因而，接合工艺可接合结构而不需要经围封空间中或衬底顶表面与裸片底表面之间的空间中的任何底胶填充。此外，上文描述的接合工艺可消除氧化物到氧化物接合(例如，针对混合接合)及/或对晶片表面条件(例如，表面粗糙度控制)的要求，这可导致较低制造成本及错误。
图13是说明根据本技术的实施例的并入半导体装置的***的框图。具有上文关于图2到12描述的特征的半导体装置中的任一者可并入到无数更大及/或更复杂***中的任何者中，所述***的代表性实例是图13中示意性地展示的***1390。***1390可包含处理器1392、存储器1394(例如，SRAM、DRAM、快闪存储器及/或其它存储器装置)、输入/输出装置1396及/或其它子***或组件1398。上文关于图2到12描述的半导体组合件、装置及装置封装可包含于图13中展示的元件中的任何者中。所得***1390可经配置以执行各种各样的合适运算、处理、存储、感测、成像及/或其它功能中的任何者。因此，***1390的代表性实例包含但不限于计算机及/或其它数据处理器，例如桌上型计算机、膝上型计算机、因特网设备、手持式装置(例如，手持式计算机、可穿戴计算机、蜂窝式或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器***、基于处理器的电子器件或可编程消费性电子器件、网络计算机及迷你计算机。***1390的额外代表性实例包含灯、相机、车辆等。关于这些及其它实例，***1390可容置于单个单元中或分布在多个互连单元上(例如，通过通信网络)。因此，***1390的组件可包含本地及/或远程存储器存储装置及各种各样的合适计算机可读媒体中的任何者。
从前文将了解，本文中已为说明的目的描述本技术的特定实施例，但可在不脱离本发明的情况下进行各种修改。另外，在特定实施例的内容背景中描述的本发明的某些方面可在其它实施例中组合或消除。此外，虽然已在特定实施例的内容背景中描述与所述实施例相关联的优点，但其它实施例也可展现此类优点。并非全部实施例都必需展现此类优点以落于本发明的范围内。因此，本发明及相关联技术可涵盖本文中未明确展示或描述的其它实施例。

Claims (18)

1.一种半导体装置，其包括：
第一裸片；
第二裸片，其经附接于所述第一裸片上方；
第一金属围封壳，其直接接触所述第一裸片及所述第二裸片且在所述第一裸片与所述第二裸片之间延伸，其中所述第一金属围封壳是连续的且环绕一组一或多个内部互连件，其中所述第一金属围封壳经配置以电连接到第一电压电平；及
第二金属围封壳，其直接接触所述第一裸片及所述第二裸片且在所述第一裸片与所述第二裸片之间延伸，其中所述第二金属围封壳是连续的且环绕所述第一金属围封壳，并且经配置以电连接到第二电压电平；
其中所述第一金属围封壳及所述第二金属围封壳经配置以提供环绕所述组一或多个内部互连件的围封电容，用于屏蔽所述组一或多个内部互连件上的信号，所述第一金属围封壳及所述第二金属围封壳形成所述第一裸片与所述第二裸片之间的围封壳分离空间，所述围封壳分离空间连续地环绕所述组一或多个内部互连件，且其中所述围封壳分离空间经填充有电介质材料。
2.根据权利要求1所述的半导体装置，其中所述第一金属围封壳及所述第二金属围封壳彼此不直接接触。
3.根据权利要求2所述的半导体装置，其中所述第一金属围封壳及所述第二金属围封壳分离达围封壳分离距离，其中所述围封壳分离距离与所述围封电容相关。
4.根据权利要求3所述的半导体装置，其中所述围封壳分离距离在所述第一金属围封壳与所述第二金属围封壳之间是均匀的。
5.根据权利要求1所述的半导体装置，其中所述第一裸片及所述第二裸片是包括裸片堆叠的单粒化半导体裸片。
6.根据权利要求5所述的半导体装置，其中：
所述第二金属围封壳是环绕整体经围封空间的外部围封壳；
所述第一金属围封壳是环绕第一内部空间的第一内部围封壳；及
其进一步包括：
第二内部围封壳，其直接接触所述第一裸片及所述第二裸片且在所述第一裸片与所述第二裸片之间垂直延伸，其中所述第二内部围封壳***地环绕在所述整体经围封空间内且与所述第一内部空间互斥的第二内部空间。
7.根据权利要求1所述的半导体装置，其进一步包括：
第三裸片，其经附接于所述第二裸片上方；
上部层级内部围封壳，其直接接触所述第二裸片及所述第三裸片且在所述第二裸片与所述第三裸片之间垂直延伸，并且经配置以电连接到所述第一电压电平；及
上部层级外部围封壳，其直接接触所述第二裸片及所述第三裸片且在所述第二裸片与所述第三裸片之间垂直延伸，其中所述上部层级外部围封壳***地环绕所述上部层级内部围封壳，并且经配置以电连接到所述第二电压电平。
8.根据权利要求7所述的半导体装置，其中：
所述上部层级内部围封壳及所述第一金属围封壳中的每一者上的一或多个点、表面或部分是沿第一垂直线重合；及
所述上部层级外部围封壳及所述第二金属围封壳中的每一者上的一或多个点、表面或部分是沿第二垂直线重合。
9.根据权利要求1所述的半导体装置，其中：
所述第二金属围封壳是沿水平方向的最***封壳；且
所述第二金属围封壳经电耦合到电接地。
10.一种制造半导体装置的方法，其包括：
提供裸片，所述裸片包含裸片互连件、裸片内部围封壳及裸片外部围封壳，其中：
所述裸片互连件从裸片底表面突出，
所述裸片内部围封壳从所述裸片底表面突出且连续地包围所述裸片互连件，及
所述裸片外部围封壳从所述裸片底表面突出且连续地包围所述裸片内部围封壳；
提供衬底，所述衬底包含衬底互连件、衬底内部围封壳，及衬底外部围封壳，其中：
所述衬底互连件从衬底顶表面突出，
所述衬底内部围封壳从所述衬底顶表面突出且连续地包围所述衬底互连件，及
所述衬底外部围封壳从所述衬底顶表面突出且连续地包围所述衬底内部围封壳而未直接接触所述衬底内部围封壳；
将所述衬底内部围封壳接合到所述裸片内部围封壳，且将所述衬底外部围封壳接合到所述裸片外部围封壳；
基于将所述衬底互连件接合到所述裸片互连件而形成一组一或多个内部互连件，其中所述组一或多个内部互连件电耦合所述裸片及所述衬底；
将所述裸片内部围封壳、所述衬底内部围封壳或其组合连接到第一电压电平；及
将所述裸片外部围封壳、所述衬底外部围封壳或其组合连接到第二电压电平以提供围封电容，所述围封电容连续地环绕所述组一或多个内部互连件，用于屏蔽所述组一或多个内部互连件上的信号；及
所述方法进一步包括：
在所述裸片内部围封壳与所述裸片外部围封壳之间，施覆第一组的电介质材料；及
在所述衬底内部围封壳与所述衬底外部围封壳之间，施覆第二组的所述电介质材料。
11.根据权利要求10所述的方法，其中所述第二电压电平是电接地。
12.根据权利要求10所述的方法，其中：
提供所述裸片包含：提供具有沿水平方向分离达围封壳分离距离的所述裸片内部围封壳及所述裸片外部围封壳的所述裸片；及
提供所述衬底包含：提供具有沿所述水平方向分离达所述围封壳分离距离的所述衬底内部围封壳及所述衬底外部围封壳的所述衬底。
13.根据权利要求10所述的方法，其中：
提供所述裸片包含提供第一裸片；
提供所述衬底包含提供第二裸片；
将所述衬底内部围封壳接合到所述裸片内部围封壳包含：形成包括在所述第一裸片与所述第二裸片之间延伸的固体金属结构的第一金属围封壳；及
将所述衬底外部围封壳接合到所述裸片外部围封壳包含：形成包括在所述第一裸片与所述第二裸片之间延伸的固体金属结构的第二金属围封壳。
14.根据权利要求13所述的方法，其中形成所述第一金属围封壳及所述第二金属围封壳包含：形成包围围封壳分离空间的所述第一金属围封壳及所述第二金属围封壳。
15.根据权利要求10所述的方法，其进一步包括在接合之前，固化所述第一组及所述第二组的电介质材料。
16.根据权利要求10所述的方法，其中接合包含固化所述第一组及所述第二组的电介质材料。
17.根据权利要求10所述的方法，其中接合包含将所述衬底内部围封壳扩散接合到所述裸片内部围封壳，并且将所述衬底外部围封壳扩散接合到所述裸片外部围封壳。
18.一种包含具有至少两个裸片的裸片堆叠的半导体装置，其包括：
多个互连件，其电耦合所述裸片堆叠的两个或更多个相邻裸片；及
第一金属密封部件及第二金属密封部件，其经安置于一对相邻裸片之间，其中所述第一金属密封部件经配置以连接到第一电压电平，
所述第二金属密封部件经配置以连接到第二电压电平，及
所述第一金属密封部件围封一或多个互连件且经嵌套于所述第二金属密封部件内用于提供包围所述一或多个互连件的围封电容，其中所述第一金属密封部件及所述第二金属密封部件形成所述一对相邻裸片之间的密封部件分离空间，所述密封部件分离空间连续地环绕所述一或多个互连件，且其中所述密封部件分离空间经填充有电介质材料。
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