CN111104276B - Chip testing system and method - Google Patents
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- CN111104276B CN111104276B CN202010002126.8A CN202010002126A CN111104276B CN 111104276 B CN111104276 B CN 111104276B CN 202010002126 A CN202010002126 A CN 202010002126A CN 111104276 B CN111104276 B CN 111104276B
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- 238000012360 testing method Methods 0.000 title claims abstract description 177
- 238000000034 method Methods 0.000 title claims description 55
- 238000004891 communication Methods 0.000 claims abstract description 24
- 239000000872 buffer Substances 0.000 claims abstract description 17
- 230000003993 interaction Effects 0.000 claims abstract description 4
- 238000012795 verification Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000002054 transplantation Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2268—Logging of test results
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Abstract
The invention discloses a chip testing system, which comprises a testing terminal and N chips to be tested of the same kind or different kinds, wherein the N chips are connected with the testing terminal through buses. The chip to be tested adopts a Modbus communication Protocol to realize data interaction with the test terminal, and meanwhile, the data format in the system is defined by Protocol buffers.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip verification and test technology.
Background
With the continuous development of chip technology, the chip functions are more and more complex, and in order to ensure the reliability of the chip, functional verification and test are required after the chip design is completed.
Typically, each function of each module of the chip needs to have an independent test item, so for a chip with high internal IP complexity, the number of test items is large, and at the same time, a small batch of chips needs to perform an independent verification test on each chip. When a chip tester changes a test item or parameter, the test of the chip consumes a lot of manpower once the test item changes because a new test program needs to be downloaded again in each chip.
For this phenomenon, it is currently common practice to add multiple test items and add serial port custom communication protocols by using a test program, so as to reduce the work of downloading the test program by the chip, and further gradually improve the automatic test method. However, this approach is limited in that if there are additional test items, the associated test equipment side and the programs on both sides of the chip interior need to be modified simultaneously. And if the subsequent test is carried out by other professional test equipment instead of the Windows system PC, the related test end program also needs to be transplanted again.
Disclosure of Invention
Aiming at part or all of the problems in the prior art, the invention provides a chip test system and a method, when a test item is changed, only a chip end program is required to be modified, and in addition, the system and the method support simultaneous test and verification of multiple chips. The invention provides a chip testing system, which comprises a testing terminal and a chip to be tested, wherein:
the chip to be tested is connected with the test terminal through a bus;
the chip to be tested is used for:
storing a test program and an operation method thereof;
sending the operation method to the test terminal;
receiving test parameters and executing test programs corresponding to the test parameters; and
transmitting the test result to the test terminal;
the test terminal is used for:
receiving and displaying the operation method;
inputting test parameters and sending the test parameters to a chip to be tested; and
and displaying, storing and analyzing the test result.
Further, the operation method, the test parameters and the data format of the test result are defined by protocols.
Further, the chips to be tested may be N chips of the same kind or different kinds, where N is a natural number.
Further, the bus is a CAN bus, and the test terminal is connected with the CAN bus through a CAN-RS232 converter.
Further, the bus is an RS485 bus.
Further, data interaction is achieved between the chip to be tested and the test terminal through a Modbus communication protocol.
The invention also provides a chip testing method, which comprises the following steps:
the method comprises the steps that a test terminal sends an instruction to a chip to be tested to acquire an operation method of a test program of the chip to be tested;
after receiving an operation method sent by the chip to be tested, the test terminal displays the number of test parameters and data types required by the operation method;
the test terminal obtains test parameters and sends the test parameters to the chip to be tested; and
and the test terminal receives the test result sent by the chip to be tested, and displays, stores and analyzes the test result.
Further, the operation method, the test parameters and the data structure of the test result of the chip test program to be tested are defined by protocols.
Further, sending the test parameters to the chip under test includes:
the test terminal sequences the test parameters through protocol buffers and converts the test parameters into binary strings;
the test terminal fills the binary string in a data area of a Modbus communication protocol and sends the binary string to a chip to be tested through a bus; and
and the chip to be tested deserializes the received binary string and executes the test corresponding to the test parameter.
Further, the operation method of the test program and the sending of the test result include:
the chip to be tested sequences the operation method of the test program and the test result through protocols and converts the operation method and the test result into binary strings;
the chip to be tested fills the binary string in a data area of a Modbus communication protocol and sends the binary string to a test terminal through a bus; and
and the test terminal deserializes the received binary string and executes corresponding operation.
According to the chip test system and method provided by the invention, the protocol buffers are applied to chip verification and test, and the discovery operation method mechanism is introduced for the first time, so that the self-adaption of the communication protocol is realized, when the test method is changed and increased, only the program is required to be modified at the chip end, and the program is not required to be modified at the test terminal at the same time.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIG. 1 is a schematic diagram of a chip test system according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a Modbus communication protocol data format according to one embodiment of the invention; and
fig. 3 is a flow chart of a chip testing method according to an embodiment of the invention.
Detailed Description
In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiments of the present invention describe the process steps in a specific order, however, this is merely to illustrate the specific embodiment and not to limit the order of the steps. In contrast, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.
Protocol buffers, which are open source items externally published by *** 7 in 2008, are widely used for various structured information storage and exchange as a custom Remote Procedure Call (RPC) system for communication between almost all devices of ***. The main characteristics are as follows: 1. adopting a binary data coding format; 2. and the system supports multiple languages such as C/C++, JAVA, C#, python and the like, and is convenient for cross-platform operation support. The two main characteristics of Protocol buffers enable the Protocol buffers to run on a single chip microcomputer, and the Protocol buffers have good data analysis and cross-platform characteristics and can solve the problem of possible follow-up transplantation.
According to the system and the method for testing the chip, the protocol buffers are applied to chip verification and testing, so that when the testing method is changed and increased, only a program needs to be modified at the chip end, and in addition, the system and the method adopt Modbus communication protocols for communication, so that simultaneous test verification of multiple chips is realized. The invention is further elucidated below in connection with the embodiments with reference to the drawings.
Fig. 1 shows a schematic structural diagram of a chip testing system according to an embodiment of the present invention, as shown in fig. 1, the chip testing system includes a testing terminal 101, and N chips 102 to be tested of the same kind or different kinds connected to the testing terminal 101 through a bus 103, where N is a natural number. In one embodiment of the present invention, the bus is a CAN bus, and the test terminal is connected to the CAN bus 103 through a CAN-RS232 converter 104. In yet another embodiment of the present invention, the bus is an RS485 bus.
The test terminal 101 is configured to obtain an operation method from the chip to be tested 102, and display the number and types of parameters required by the operation method, so that a user can input corresponding test parameters on the test terminal 101, and the test terminal 101 is further configured to send the test parameters to the chip to be tested 102, and receive, display, store and analyze the test result of the chip to be tested 102.
The chip to be tested 102 stores a test program of the chip and an operation method thereof, and is used for executing a corresponding test and sending a test result to the test terminal 101.
The chip to be tested 102 adopts Modbus communication protocol to realize data interaction with the test terminal 101. As shown in fig. 2, the data frame of the Modbus communication Protocol includes an address code 201, a function code 202, a data area 203 and a check code 204, wherein the address code 201 identifies the addresses of the chips to realize the synchronous test of multiple chips, and the data in the data area 203 is the operation method, the test parameters and the test result after being serialized by the protocols.
When multiple chips are tested simultaneously, the chips need to be put into a communication protocol with an address code data format. As shown in fig. 2, protocol buffers are used as data areas of the Modbus communication Protocol, and address areas of the Modbus are used to solve the problem that one test terminal tests a plurality of chips to be tested. On the basis of the communication protocol, the self-adaptive function is developed on the test terminal by improving the communication protocol, and the communication protocol can be suitable for various series of tested chips. The one-time development work of the test terminal is truly realized, and the subsequent modification risk and work are greatly reduced. Only the tested chip end program needs to be modified.
In the internal test program of the tested chip, the operation method of the tested chip can be obtained in the human-computer interface of the test terminal through the corresponding communication protocol. Through the acquired operation method, the test terminal can display the test parameters which need to be transmitted in by the related operation method, including the information of the number, the data type and the like of the parameters. And the test terminal inputs corresponding parameters, and can sequence and transmit data to a corresponding test chip through the optimized protocol buffers. The chip receives the transferred data, performs the related operation after the data is inversely sequenced, and transfers the related data after the related operation is sequenced to the PC of the test terminal through the bus. And the PC end transmits the reverse serialization of the execution data to the operation interface.
Fig. 3 is a flow chart of a chip testing method according to an embodiment of the invention. A chip testing method comprises the following steps:
step 301, define a data format. Defining an operation method, a parameter data structure and a test result data structure of a chip test program to be tested by adopting protocols;
step 302, a test system is built. Downloading a test program to a chip to be tested, and connecting the chip to be tested to a test terminal through a CAN bus or an RS485 bus;
step 303, obtaining an operation method. Transmitting an instruction from the test terminal to acquire an operation method of the chip test program to be tested, after receiving the instruction, the chip to be tested sequences the operation method through protocols buffers, converts the operation method into binary strings, fills the binary strings in a data area of a Modbus communication protocol, and transmits the binary strings to the test terminal through a bus;
step 304, displaying the parameter information. The test terminal receives Modbus data sent by the chip to be tested, then performs deserialization to obtain the operation method, and extracts the number of test parameters and data types required by the operation method by reading the operation method and displays the number and the data types on display equipment of the test terminal;
in step 305, test parameters are input and sent. According to the number of parameters and the data types displayed by the test terminal, a user inputs corresponding test parameters, the test terminal sequences the test parameters through protocol buffers, converts the test parameters into binary strings, fills the binary strings in a data area of a Modbus communication protocol, and sends the binary strings to the chip to be tested through a bus;
at step 306, a test is performed. After the chip to be tested receives Modbus data sent by the test terminal, performing deserialization to obtain the test parameters, and then executing the test;
step 307, send test results. After the test is finished, the chip to be tested sequences the test result through protocol buffers, converts the test result into a binary string, fills the binary string in a data area of a Modbus communication protocol, and sends the binary string to the test terminal through a bus; and
step 308, result analysis. And after receiving Modbus data sent by the chip to be tested, the test terminal performs deserialization to obtain a test result, displays the test result on display equipment of the test terminal, analyzes the test result at the same time, and stores the test result and analysis conclusion in storage equipment of the test terminal.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (8)
1. The chip testing system comprises a testing terminal and a chip to be tested, and is characterized in that:
the chip to be tested is connected with the test terminal through a bus;
the chip to be tested is used for:
storing a test program and an operation method thereof, wherein the data format of the operation method is defined by protocols;
sending the operation method to the test terminal;
receiving test parameters and executing a test program corresponding to the test parameters, wherein the data format of the test parameters is defined by Protocol buffers; and
transmitting the test result to the test terminal, wherein the data format of the test result is defined by protocols;
the test terminal is used for:
receiving the operation method and displaying the number and types of parameters required by the operation method;
inputting test parameters and sending the test parameters to a chip to be tested; and
and displaying, storing and analyzing the test result.
2. The system of claim 1, wherein the chips to be tested are N chips of the same type or different types, where N is a natural number.
3. The system of claim 1, wherein the bus is a CAN bus and the test terminal is connected to the CAN bus through a CAN-RS232 converter.
4. The system of claim 1, wherein the bus is an RS485 bus.
5. The system according to any one of claims 1 to 4, wherein data interaction is implemented between the chip under test and the test terminal via a Modbus communication protocol.
6. A chip testing method connects a chip to be tested to a testing terminal through a bus, and is characterized by comprising the following steps:
the method comprises the steps that a test terminal sends an instruction to a chip to be tested to acquire an operation method of a test program of the chip to be tested, wherein a data format of the operation method is defined by Protocol buffers;
after receiving an operation method sent by the chip to be tested, the test terminal displays the number of test parameters and data types required by the operation method;
the method comprises the steps that a test terminal obtains test parameters and sends the test parameters to a chip to be tested, wherein the data format of the test parameters is defined by Protocol buffers; and
and the test terminal receives the test result sent by the chip to be tested, and displays, stores and analyzes the test result, wherein the data format of the test result is defined by protocols.
7. The method of claim 6, wherein transmitting the test parameters to the chip under test comprises:
the test terminal sequences the test parameters through protocol buffers and converts the test parameters into binary strings;
the test terminal fills the binary string in a data area of a Modbus communication protocol and sends the binary string to a chip to be tested through a bus; and
and the chip to be tested deserializes the received binary string and executes the test corresponding to the test parameter.
8. The method of claim 7, wherein the method of operation of the test program and the sending of the test results comprise:
the chip to be tested sequences the operation method of the test program and the test result through protocols and converts the operation method and the test result into binary strings;
the chip to be tested fills the binary string in a data area of a Modbus communication protocol and sends the binary string to a test terminal through a bus; and
and the test terminal deserializes the received binary string and executes corresponding operation.
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| CN112118166B (en) * | 2020-09-18 | 2022-05-31 | 上海国微思尔芯技术股份有限公司 | Multi-chip networking system, method and application |
| CN116820867B (en) * | 2023-08-29 | 2023-12-15 | 腾讯科技（深圳）有限公司 | Chip debugging method and device and chip |
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| US10768230B2 (en) * | 2016-05-27 | 2020-09-08 | International Business Machines Corporation | Built-in device testing of integrated circuits |
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| CN106054058A (en) * | 2016-04-28 | 2016-10-26 | 芯海科技（深圳）股份有限公司 | System and method capable of performing testing and temperature control on multiple Sigma-Delta ADC chips |
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