CN111081648A - 包括支承上芯片层叠物的支承块的半导体封装件 - Google Patents

包括支承上芯片层叠物的支承块的半导体封装件 Download PDF

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CN111081648A
CN111081648A CN201811561180.5A CN201811561180A CN111081648A CN 111081648 A CN111081648 A CN 111081648A CN 201811561180 A CN201811561180 A CN 201811561180A CN 111081648 A CN111081648 A CN 111081648A
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chip
semiconductor
support block
package substrate
chip stack
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CN111081648B (zh
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姜敃圭
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SK Hynix Inc
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SK Hynix Inc
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Abstract

包括支承上芯片层叠物的支承块的半导体封装件。一种半导体封装件包括封装基板、第一芯片层叠物、第二芯片层叠物和支承块。所述第一芯片层叠物包括以在第一方向上偏移的方式层叠在所述封装基板上的第一半导体芯片，并且所述第二芯片层叠物包括以在第二方向上偏移的方式层叠在所述第一芯片层叠物上的第二半导体芯片。所述支承块包括穿通孔结构。所述第二芯片层叠物被所述第一芯片层叠物和所述支承块支承。

Description

包括支承上芯片层叠物的支承块的半导体封装件
技术领域
本公开涉及半导体封装技术，并且更具体地，涉及一种包括支承上芯片层叠物的支承块的半导体封装件。
背景技术
在各种电子产品中需要具有大容量的半导体封装件。因此，已经提出了各种封装结构来增加嵌入在一个半导体封装件中的半导体芯片的数目。例如，可以将至少两个半导体芯片层叠以提供层叠封装件。已将大量努力付诸于层叠多个半导体芯片以增加嵌入在单个半导体封装件的有限空间中的半导体芯片的数目。
发明内容
根据一个实施方式，一种半导体封装件包括第一芯片层叠物，所述第一芯片层叠物包括在竖直方向层叠在封装基板上的第一半导体芯片，其中，所述第一半导体芯片在第一方向上偏移。该半导体封装件还包括中介层，所述中介层包括重分配层(RDL)图案，其中，所述中介层被设置在所述封装基板上并且与所述第一芯片层叠物横向地间隔开。所述RDL图案包括第一连接部、第二连接部和将所述第一连接部连接到所述第二连接部的延伸部。该半导体封装件还包括支承块，所述支承块在竖直方向层叠在所述中介层上，其中，所述支承块包括穿通孔结构，所述穿通孔结构的下端电连接到所述中介层的所述第一连接部。该半导体封装件附加包括第二芯片层叠物，所述第二芯片层叠物包括在竖直方向层叠在所述第一芯片层叠物和所述支承块二者上的第二半导体芯片，其中，所述第二半导体芯片在第二方向上偏移。该半导体封装件还包括：第一互连器，所述第一互连器将所述第一半导体芯片电连接到所述封装基板；第二互连器，所述第二互连器将所述第二半导体芯片电连接到所述穿通孔结构的上端。该半导体封装件还包括第三互连器，所述第三互连器将所述RDL图案的所述第二连接部电连接到所述封装基板。
根据另一个实施方式，一种半导体封装件包括封装基板，所述封装基板包括接合指。该半导体封装件还包括第一芯片层叠物，所述第一芯片层叠物以与所述接合指间隔开的方式设置在所述封装基板上，所述第一芯片层叠物包括被层叠成在第一方向上偏移的第一半导体芯片。该半导体封装件还包括支承块，所述支承块以与所述第一芯片层叠物间隔开的方式设置在所述封装基板上，所述支承块包括穿通孔结构，所述穿通孔结构具有电连接到所述接合指的下端。该半导体封装件还包括第二芯片层叠物，所述第二芯片层叠物包括在竖直方向层叠在所述第一芯片层叠物和所述支承块二者上的第二半导体芯片，其中，所述第二半导体芯片在第二方向上偏移。该半导体封装件还包括：第一互连器，所述第一互连器将所述第一半导体芯片电连接到所述封装基板；以及第二互连器，所述第二互连器将所述第二半导体芯片电连接到所述穿通孔结构的上端。
附图说明
图1示出了说明根据一个实施方式的半导体封装件的截面图。
图2示出了说明图1的半导体封装件中所包括的中介层和支承块的接合部的放大视图。
图3例示了图1中示出半导体封装件的中介层。
图4示出了说明图1中示出的半导体封装件的支承块的立体图。
图5示出了说明图1的半导体封装件中所包括的支承块和第二芯片层叠物的平面图。
图6示出了说明比较例中的因引线接合工艺引起的接合失效的示意图。
图7示出了说明根据另一个实施方式的半导体封装件的截面图。
图8示出了说明图7的半导体封装件中所包括的封装基板和支承块的接合部的放大视图。
图9示出了说明采用包括根据一个实施方式的半导体封装件的存储卡的电子***的框图。
图10示出了说明包括根据一个实施方式的半导体封装件的另一电子***的框图。
具体实施方式
本文中所使用的术语可以对应于考虑到它们在所提出的实施方式中的功能而选择的词语，并且术语的含义可以被解释为根据实施方式所属领域的普通技术人员而不同。如果被详细定义，则术语可以根据所提供的定义来解释。除非另外定义，否则本文中使用的术语(包括技术术语和科学术语)具有与实施方式所属领域的普通技术人员通常理解的含义相同的含义。
将理解的是，虽然可以在本文中使用术语“第一”、“第二”、“第三”等来描述各种元件，但是这些元件不应该受这些术语限制。这些术语仅用于将一个元件与另一个元件区分开，而并不用于暗指层级或特定顺序。
还应该理解，当元件或层被称为在另一个元件或层“上”、“上方”、“下”、“下方”或“外部”时，该元件或层可以与其它元件或层直接接触，或者可能存在中间元件或层。用于描述元件或层之间的关系的其它词语应该以类似的方式来解释(例如，“在…之间”与“直接在…之间”或者“相邻”与“直接相邻”)。
可以使用诸如“之下”、“下方”、“下部的”、“上方”、“上部的”、“顶部的”、“底部的”等的空间相对术语来描述例如图中例示的一个元件和/或特征与其它元件和/或特征的关系。将理解的是，空间相对术语旨在涵盖除了附图中描绘的方位之外的装置在使用和/或操作时的不同方位。例如，当附图中的装置被翻转时，被描述为在其它元件或特征下方或之下的元件随后将被定向为在其它元件或特征上方。装置可以按其它方式来定向(例如，旋转90度或处于其它方位)，并且相应解释本文中使用的空间相对描述符。
半导体封装件可以包括诸如半导体芯片或半导体晶片这样的电子器件。可以通过使用晶片锯切工艺将诸如晶圆的半导体基板分离成多个块来获得半导体芯片或半导体晶片。半导体芯片可以对应于存储器芯片、逻辑芯片(包括专用集成电路(ASIC)芯片)或片上***(SoC)。存储器芯片可以包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪速存储器电路、NOR型闪速存储器电路、磁性随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电式随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可以包括集成在半导体基板上的逻辑电路。半导体封装件可以被用在诸如移动电话这样的通信***、与生物技术或健康护理关联的电子***或可穿戴电子***中。
在整个说明书中，相同的参考标号表示相同的元件。即使没有参照一附图提及或描述一参考标号，也会参照其它附图提及或描述该参考标号。另外，即使在一附图中未示出一参考标号，也会参照其它附图来提及或描述该参考标号。
图1示出了说明根据一个实施方式的半导体封装件10的截面图。
参照图1，半导体封装件10可以被配置为包括封装基板100、第一芯片层叠物300和中介层510。第一芯片层叠物300可以按照与中介层510横向间隔开的方式设置在封装基板100上。第二芯片层叠物400可以被附加层叠在第一芯片层叠物300上。支承块550可以被设置为垂直竖立在中介层510上。第二芯片层叠物400可以延伸到支承块550上。因此，第二芯片层叠物400可以被支承块550和第一芯片层叠物300支承。
第一芯片层叠物300可以包括以在第一偏移方向上偏移的方式层叠的多个第一半导体芯片310。第一半导体芯片310可以通过设置在其间的粘合层330彼此附接。第二芯片层叠物400可以包括按照在与第一偏移方向基本相反的第二偏移方向上偏移的方式层叠的多个第二半导体芯片410。第二半导体芯片410可以通过设置在其间的粘合层430彼此附接。
第一半导体芯片310可以是存储器半导体芯片，例如，NAND型闪速存储器装置。第一半导体芯片310中的每一个可以包括用于其电连接的第一芯片焊盘315。如果第一半导体芯片310中的一个与第一上半导体芯片310U对应并且第一半导体芯片310中的另一个与位于第一上半导体芯片310U下方的第一下半导体芯片310L对应，则第一上半导体芯片310U可以在第一偏移方向上相对于第一下半导体芯片310L偏移，以使第一下半导体芯片310L的第一芯片焊盘315暴露。
第二半导体芯片410可以是存储器半导体芯片，例如，NAND型闪速存储器装置。第二半导体芯片410中的每一个可以包括用于其电连接的第二芯片焊盘415。如果第二半导体芯片410中的一个与第二上半导体芯片410U对应并且第二半导体芯片410中的另一个与位于第二上半导体芯片410U下方的第二下半导体芯片410L对应，则第二上半导体芯片410U可以在第二偏移方向上相对于第二下半导体芯片410L偏移，以使第二下半导体芯片410L的第二芯片焊盘415暴露。
在第一半导体芯片310被层叠成在第一偏移方向上偏移并且第二半导体芯片410被层叠成在与第一偏移方向相反的第二偏移方向上偏移的情况下，与第一半导体芯片310和第二半导体芯片410全部被层叠成在一个偏移方向上偏移的情况相比，包括全部第一半导体芯片310和第二半导体芯片410的整个结构的宽度W可以减小。如果第二半导体芯片410层叠在第一芯片层叠物300上以在与第一半导体芯片310的第一偏移方向相同的偏移方向上连续偏移，则包括被层叠成仅在第一偏移方向上偏移的第一半导体芯片310和第二半导体芯片410的整个结构的宽度可以大于图1中例示的包括全部第一半导体芯片310和第二半导体芯片410的结构的宽度W。如此，因为第一半导体芯片310的偏移方向(即，第一偏移方向)与第二半导体芯片410的偏移方向(即，第二偏移方向)相反，所以半导体封装件10的整个宽度可以减小。
第一芯片层叠物300可以通过第一互连器370电连接到封装基板100。也就是说，第一互连器370可以将第一半导体芯片310电连接到封装基板100。第一互连器370可以包括第一接合导线。如果采用第一接合导线作为第一互连器370，则第一接合导线可以将第一半导体芯片310的第一芯片焊盘315彼此电连接。另外，第一接合导线可以进一步延伸，以电连接到封装基板100的第一接合指113。
封装基板100的第一接合指113可以是包括在封装基板100中的电路互连结构(未示出)的部分。封装基板100可以是包括电路互连结构(例如，印刷电路板(PCB))的基板。封装基板100的第一接合指113可以被设置在与第一芯片层叠物300交叠的区域外部，以便连接到与第一互连器370对应的第一接合导线。
构成第二芯片层叠物400的第二半导体芯片410可以通过第二互连器470彼此电连接。第二互连器470可以延伸，以将第二芯片层叠物400电连接到支承块550。支承块550可以电连接到设置在其下方的中介层510。中介层510可以通过第三互连器570电连接到封装基板100。第二半导体芯片410可以通过第二互连器470、支承块550、中介层510和第三互连器570电连接到封装基板100。
第二互连器470可以包括第二接合导线。如果采用第二接合导线作为第二互连器470，则第二接合导线可以将第二半导体芯片410的第二芯片焊盘415彼此电连接，并且可以进一步延伸以电连接到支承块550。第二互连器470可以位于第二芯片层叠物400的与第一互连器370相反的一侧。第一互连器370可以位于第一芯片层叠物300的与支承块550相反的一侧。第三互连器570可以包括第三接合导线。如果采用第三接合导线作为第三互连器570，则第三接合导线可以被设置成将中介层510电连接到封装基板100的第二接合指115。
图2示出了说明图1的半导体封装件10中所包括的中介层510和支承块550的接合部的放大视图。
参照图2，穿通孔结构550V可以被设置成在竖直方向穿透支承块550。第二互连器470可以延伸以将第二芯片层叠物400的第二半导体芯片410电连接到穿通孔结构550V的上端。支承块550可以包括块主体550B。穿通孔结构550V可以被设置成在竖直方向穿透支承块550的块主体550B。穿通孔结构550V中的每一个可以被配置为包括彼此相对的第一通孔焊盘553和第二通孔焊盘556以及将第一通孔焊盘553连接到第二通孔焊盘556的垂直通孔部552。第一通孔焊盘553可以提供穿通孔结构550V中的每一个的上端，第二通孔焊盘556可以提供穿通孔结构550V中的每一个的下端。
块主体550B可以被配置为包括硅主体551、上电介质层554和下电介质层557。上电介质层554可以被设置在硅主体551的与下电介质层557相对的顶表面上，并且下电介质层557可以被设置在硅主体551的与上电介质层554相对的底表面上。硅主体551可以包含与各种半导体材料中的一种对应的硅材料，并且可以具有芯片形状或盒形状。上电介质层554可以被设置在硅主体551的顶表面上，以使穿通孔结构550V的第一通孔焊盘553暴露。上电介质层554可以包括电介质层或绝缘层。下电介质层557可以被设置在硅主体551的底表面上，以使穿通孔结构550V的第二通孔焊盘556暴露。下电介质层557可以包括电介质层或绝缘层。穿通孔结构550V的垂直通孔部552可以与在竖直方向穿透硅主体551的硅通孔(TSV)对应。因为第二互连器470的第一端连接到穿通孔结构550V的第一通孔焊盘553，所以第二互连器470可以将第二芯片层叠物400电连接到穿通孔结构550V的垂直通孔部552。
图3示出了说明图1中示出的半导体封装件10的中介层510的重分配层(RDL)图案513的平面图。
参照图2和图3，中介层510可以被设置在支承块550和封装基板100之间。中介层510可以被配置为包括中介主体(interposer body)510B和RDL图案513。中介主体510B可以具有芯片形状。中介主体510B可以被配置为包括：硅主体511，该硅主体511具有与各种半导体材料中的一种对应的硅材料；第一电介质层514，该第一电介质层514被设置在硅主体511的与封装基板100相反的顶表面上；以及第二电介质层515，该第二电介质层515与硅主体511相反地设置在第一电介质层514上。包括金属图案的RDL图案513可以被设置在第一电介质层514和第二电介质层515之间。第一电介质层514可以将RDL图案513与硅主体511电隔离，并且第二电介质层515可以将RDL图案513彼此电隔离。
RDL图案513中的每一个可以是包括第一连接部513L、第二连接部513P和延伸部513C的导电图案。在RDL图案513中的每一个中，第一连接部513L和第二连接部513P可以彼此间隔开，并且延伸部513C可以是将第一连接部513L连接到第二连接部513P的线形图案。第二电介质层515可以覆盖RDL图案513的延伸部513C(如虚线所指示的)以与其它元件隔离，并且可以被形成为使RDL图案513的第一连接部513L和第二连接部513P暴露。RDL图案513的第一连接部513L可以被设置成分别面对穿通孔结构550V的第二通孔焊盘556。
导电凸块565可以被设置在支承块550和中介层510之间。导电凸块565可以用作将支承块550电连接到中介层510的内部导体。导电凸块565可以将RDL图案513的第一连接部513L电连接到穿通孔结构550V的第二通孔焊盘556(与下端对应)。导电凸块565可以通过包围导电凸块565的侧表面的第二粘合层560彼此电绝缘，并且第二粘合层560可以将支承块550附接到中介层510。第二粘合层560可以是非导电膜(NCF)。
支承块550可以与中介层510的部分交叠，以使RDL图案513的第二连接部513P暴露。支承块550可以被设置成覆盖RDL图案513的第一连接部513L。RDL图案513可以包括从被支承块550覆盖的第一连接部513L延伸到被支承块550暴露的第二连接部513P的延伸部513C。第三连接器570可以将RDL图案513的第二连接部513P电连接到封装基板100的第二接合指115。用作第三互连器570的第三接合导线的第一端可以接合到RDL图案513的第二连接部513P，并且用作第三互连器570的第三接合导线的第二端可以接合到封装基板100的第二接合指115。封装基板100的第二接合指115可以构成包括在封装基板100中的电路互连结构(未示出)的部分。
封装基板100的第二接合指115可以被设置成与中介层510间隔开特定距离。第三粘合层569可以被设置在中介层510和封装基板100之间。第三粘合层569可以包含用于将中介层510附接到封装基板100的粘合材料。中介层510可以通过第三粘合层569附接到封装基板100，以使封装基板100的第二接合指115暴露。
封装基板100的第二接合指115可以位于中介层510被设置的位置与第一芯片层叠物300被层叠的位置之间。封装基板100的第二接合指115可以被设置成与第二芯片层叠物400在竖直方向交叠。当从平面图观察时，封装基板100的第二接合指115可以位于第二芯片层叠物400的交叠区域下方。如果第二接合指115位于第二芯片层叠物400和封装基板100的交叠区域的外部区域上，则可必须增大封装基板100的宽度。因此，因为第二接合指115被设置成与第二芯片层叠物400在竖直方向交叠，所以封装基板100的宽度可以相对减小。
图4示出了说明图1中示出的半导体封装件10的支承块550的立体图。图5是例示支承块550和被支承块550支承的第二芯片层叠物400的平面图。
参照图4，支承块550可以包括分成两部分的第一区域550M和第二区域550L。穿通孔结构550V可以被设置成在支承块550的第一区域550M中彼此横向地间隔开。穿通孔结构550V可以基本上穿透支承块550的第一区域550M中的块主体550B。穿通孔结构550V的第一通孔焊盘553可以在块主体550B的顶表面550S1处暴露，而穿通孔结构550V的第二通孔焊盘556可以在块主体550B的底表面550S2处暴露。对于一个实施方式，穿通孔结构550V不设置在块主体550B的与块主体550B的第一区域550M相邻的第二区域550L中。
再次参照图2，在第二芯片层叠物400被层叠在第一芯片层叠物300上的层叠结构中，第二芯片层叠物400的部分400E可以从第一芯片层叠物300的边缘部300E横向地突出。第二芯片层叠物400的突出部400E可以被定位成与支承块550的第二区域550L在竖直方向交叠。第二芯片层叠物400的突出部400E可以被支承块550的第二区域550L支承。第一粘合层430B可以被设置在第二芯片层叠物400的突出部400E和支承块550的第二区域550L之间。第一粘合层430B可以将第二芯片层叠物400的突出部400E附接到支承块550的第二区域550L。第一粘合层430B可以延伸到第一芯片层叠物300与第二芯片层叠物400之间的界面中，以将第二芯片层叠物400附接到第一芯片层叠物300。在这种情况下，支承块550可以被设置成与第一芯片层叠物300横向地间隔开特定距离D。
第一芯片层叠物300和支承块550可以被设置在封装基板100上，使得与第一芯片层叠物300的顶表面对应的第一顶表面300T和与支承块550的顶表面对应的第二顶表面550T位于基本上相同的高度。第二芯片层叠物400可以被设置在第一芯片层叠物300的第一顶表面300T和支承块550的第二顶表面550T二者上，以被第一芯片层叠物300和支承块550稳定地支承。
第二芯片层叠物400的突出部400E可以被支承块550的第二区域550L支承。第二芯片焊盘415的一些焊盘415B可以位于第二芯片层叠物400的突出部400E上，以与支承块550的第二区域550L在竖直方向交叠。如图5中例示的，构成第二芯片层叠物400的第二半导体芯片410当中的与最下层芯片对应的最下层第二半导体芯片410B可以包括第二芯片焊盘415B，并且第二芯片焊盘415B可以被设置为与支承块550的第二区域550L交叠。因此，最下层第二半导体芯片410B的第二芯片焊盘415B可以被支承块550的第二区域550L支承。因此，当将第二互连器470引线接合到第二芯片焊盘415B时，可以向支承块550的第二区域550L施加压力或冲击。支承块550可以耐受由接合工艺产生的压力或冲击，并且可以支承第二芯片层叠物400的突出部400E。因为支承块550支承包括第二芯片焊盘415B的突出部400E，所以支承块550能防止在执行接合工艺时第二芯片层叠物400的突出部400E卷曲或受损。
如果不存在支承块550，则包括第二芯片焊盘415B的突出部400E可能由于在接合工艺期间产生的压力或冲击而向下卷曲。如果包括第二芯片焊盘415B的突出部400E在接合工艺期间向下卷曲，则可能难以将第二互连器470准确地接合到第二芯片焊盘415B。也就是说，如果不存在支承块550，则可能发生接合失效。然而，根据本实施方式，因为存在支承包括第二芯片焊盘415B的突出部400E的支承块550，所以能够将第二互连器470准确地接合到第二芯片焊盘415B。
图6示出了说明比较例中的由引线接合工艺引起的接合失效现象的示意图。
参照图6，比较例可以对应于与图2的最下层第二半导体芯片410B对应的半导体芯片41R的挤出部(extruded portion)41E未被支承块(图2的550)支承的情况。引线接合器47H可以将引线47W引导并接合到位于半导体芯片41R的挤出部41E上的芯片焊盘45R。当将引线47W接合到芯片焊盘45R时，可向半导体芯片41R的挤出部41E施加压力和/或冲击。在这种情况下，因为没有任何东西支承半导体芯片41R的挤出部41E，所以半导体芯片41R的挤出部41E可向下卷曲。如果半导体芯片41R的挤出部41E向下卷曲，则芯片焊盘45R的位置和水平会改变。因此，可能难以将接合导线47R精确地接合到芯片焊盘45R。也就是说，接合导线47R不能精确地接合到芯片焊盘45R，从而造成接合失效。
然而，根据图2和图5中例示的本实施方式，第二互连器470可以在最下层第二半导体芯片410B的第二芯片焊盘415B被支承块550的第二区域550L稳定地支承的同时引线接合到第二芯片焊盘415B。因此，能够防止发生第二互连器470的接合失效现象。
再次参照图6，半导体芯片41R通过接合导线47R电连接到与图2的封装基板100对应的封装基板10R的接合指15R。在这种情况下，因为半导体芯片41R位于相对高的水平，所以接合导线47R的长度可以大于图2中例示的第二互连器470的长度。因此，在使用环氧模塑料(EMC)材料进行模制工艺期间，由于EMC材料的流动而引起的横向压力可以被施加到接合导线47R。
具有相对长的长度的接合导线47R可由于因EMC材料的流动所产生的横向压力而容易变形或受损。由于EMC材料的流动所产生的横向压力可以横向扫过接合导线47R，从而造成接合导线47R的横扫故障(sweeping failure)。在这种情况下，接合导线47R可变形或受损，以电连接到与接合导线47R相邻的另一接合导线或者造成接合导线47R的开路故障。
然而，根据图2和图5中例示的本实施方式，支承块550或者支承块550和中介层510的组合结构可以提供将第二芯片层叠物400电连接到封装基板100的连接路径。因为第二互连器470将第二芯片层叠物400电连接到支承块550，所以与图6中示出的比较例中所包括的接合导线47R的长度相比，第二互连器470的长度可减小。因此，即使在用于形成覆盖第一芯片层叠物300和第二芯片层叠物400以及第二互连器470的模制层600的模制工艺期间由于EMC材料的流动所产生的压力被施加到第二连接器470，但是因为第二互连器470具有减小的长度，所以可有效地抑制第二互连器470的横扫故障。
再次参照图1，半导体封装件10还可以包括设置在封装基板100和第一芯片层叠物300之间的提升电介质层250。提升电介质层250可以将第一芯片层叠物300提升，以使封装基板100与第一芯片层叠物300之间的距离增大。提升电介质层250可以用作将第一芯片层叠物300附接到封装基板100的粘合层。第三半导体芯片210可以被设置在第一芯片层叠物300与封装基板100之间或者提升电介质层250与封装基板100之间。第三半导体芯片210可以利用第四粘合层230附接到封装基板100。第三半导体芯片210可以包括控制第一半导体芯片310和第二半导体芯片410的操作的控制器芯片。
第三半导体芯片210可以通过第四互连器270电连接到封装基板100。第四互连器270可以使用第四接合导线来实现。第三半导体芯片210可以包括用于第三半导体芯片210的电连接的第三芯片焊盘211，并且封装基板100可以包括电连接到第三芯片焊盘211的第三接合指111。用作第四互连器270的第四接合导线可以将第三接合指111电连接到第三芯片焊盘211。第三接合指111可以是包括在封装基板100中的电路互连结构(未示出)的部分。提升电介质层250可以被设置成覆盖第三半导体芯片210和第四互连器270。在这种情况下，第三半导体芯片210和第四互连器270可以基本嵌入在提升电介质层250中。
图7示出了说明根据另一个实施方式的半导体封装件20的截面图。图8示出了说明图7的半导体封装件20中所包括的封装基板2100和支承块2550的接合部的放大视图。
参照图7和图8，半导体封装件20可以被配置为包括封装基板2100、第一芯片层叠物2300、第二芯片层叠物2400和支承块2550。模制层2600可以被设置在封装基板2100的表面上，以覆盖第一芯片层叠物2300、第二芯片层叠物2400和支承块2550。半导体封装件20可以被配置为使得第二芯片层叠物2400通过支承块2550电连接到封装基板2100。与图1中例示的半导体封装件10不同，支承块2550可直接连接到封装基板2100而无需诸如中介层(图1的510)这样的任何介入元件。第二芯片层叠物2400可以被设置在支承块2500和第一芯片层叠物2300二者上。也就是说，第二芯片层叠物2400可以被支承块2550和第一芯片层叠物2300支承。
如图8中例示的，第一芯片层叠物2300和支承块2550可以被设置在封装基板2100上，使得与第一芯片层叠物2300的顶表面对应的第一顶表面2300T和与支承块2550的顶表面对应的第二顶表面2550T位于基本相同的水平。第二芯片层叠物2400可以被设置在第一芯片层叠物2300的第一顶表面2300T和支承块2550的第二顶表面2550T二者上，以被第一芯片层叠物2300和支承块2550稳定地支承。
第一半导体芯片2310可以按照在第一偏移方向上偏移的方式层叠，以构成第一芯片层叠物2300。第一半导体芯片2310可以通过设置在其间的粘合层2330彼此附接。第二半导体芯片2410可以按照在与第一偏移方向基本相反的第二偏移方向上偏移的方式层叠，由此构成第二芯片层叠物2400。第二半导体芯片2410可以通过设置在其间的粘合层2430彼此附接。
第一芯片层叠物2300的第一半导体芯片2310可以通过第一互连器2370电连接到封装基板2100。用作第一互连器2370的第一接合导线可以将第一半导体芯片2310的第一芯片焊盘2315彼此电连接，并且可以延伸以连接到封装基板2100的第一接合指2113。
第二芯片层叠物2400的第二半导体芯片2410可以通过第二互连器2470彼此电连接，并且第二互连器2470可以延伸以将第二芯片层叠物2400电连接到支承块2550。用作第二互连器2470的第二接合导线可以将第二半导体芯片2410的第二芯片焊盘2415彼此电连接，并且可以延伸以连接到支承块2550。
第二互连器2470可以通过支承块2550电连接到封装基板2100的第二接合指2115。支承块2550可以被设置为与封装基板2100的第二接合指2115交叠，并且可以电连接到封装基板2100的第二接合指2115。
参照图8，穿通孔结构2550V可以被设置成在竖直方向穿透支承块2550。支承块2550可以被配置为包括块主体2550B和在竖直方向穿透块主体2550B的穿通孔结构2550V。穿通孔结构2550V中的每一个可以被配置为包括彼此相对的第一通孔焊盘2553和第二通孔焊盘2556以及将第一通孔焊盘2553连接到第二通孔焊盘2556的垂直通孔部2552。第一通孔焊盘2553可以提供穿通孔结构2550V中的每一个的上端，第二通孔焊盘2556可以提供穿通孔结构2550V中的每一个的下端。
块主体2550B可以被配置为包括硅主体2551、上电介质层2554和下电介质层2557。上电介质层2554可以被设置在硅主体2551的顶表面上，以使穿通孔结构2550V的第一通孔焊盘2553暴露，并且下电介质层557可以被设置在硅主体2551的底表面上，以使穿通孔结构2550V的第二通孔焊盘2556暴露。穿通孔结构2550V的垂直通孔部2552可以与在竖直方向穿透硅主体2551的硅通孔(TSV)对应。第二互连器2470的第一端可以接合到穿通孔结构2550V的第一通孔焊盘2553，使得第二互连器2470将第二芯片层叠物2400电连接到穿通孔结构2550V的垂直通孔部2552。
导电凸块2560可以被设置在支承块2550和封装基板2100之间，以用作将支承块2550电连接到封装基板2100的内部导体。导电凸块2560可以将穿通孔结构2550V的第二通孔焊盘2556(与下端对应)直接地电连接到封装基板2100的第二接合指2115。导电凸块2560可以通过包围导电凸块2560的侧表面的第二粘合层2565彼此电绝缘，并且第二粘合层2565可以将支承块2550附接到封装基板2100。第二粘合层2565可以是非导电膜(NCF)。封装基板2100的第二接合指2115可以被设置成分别与支承块2550的第二通孔焊盘2556在竖直方向交叠。封装基板2100的第二接合指2115可以被设置为与支承块2550的穿通孔结构2550V交叠。
再次参照图8，支承块2550可以包括分成两部分的第一区域2550M和第二区域2550L。穿通孔结构2550V可以被设置成基本上穿透支承块2550的第一区域2550M中的块主体2550B。对于一个实施方式，穿通孔结构2550V不设置在支承块2550的与第一区域2550M相邻的第二区域2550L中。
在第二芯片层叠物2400被层叠在第一芯片层叠物2300上的层叠结构中，第二芯片层叠物2400的部分2400E可以从第一芯片层叠物2300的边缘部2300E横向地突出。第二芯片层叠物2400的突出部2400E可以被支承块2550的第二区域2550L支承。第一粘合层2430B可以设置在第二芯片层叠物2400的突出部2400E和支承块2550的第二区域2550L之间。第一粘合层2430B可以延伸到第一芯片层叠物2300与第二芯片层叠物2400之间的界面中，以将第二芯片层叠物2400附接到第一芯片层叠物2300。
构成第二芯片层叠物2400的第二半导体芯片2410当中的与最下层芯片对应的最下层第二半导体芯片2410B可以包括第二芯片焊盘2415B，并且第二芯片焊盘2415B可以被设置为与支承块2550的第二区域2550L交叠。因此，最下层第二半导体芯片2410B的第二芯片焊盘2415B可以被支承块2550的第二区域2550L支承。因此，当第二互连器2470被引线接合到第二芯片焊盘2415B时，支承块2550能够防止第二互连器2470和第二芯片焊盘2415B之间的接合失效的发生。
再次参照图7，半导体封装件20还可以包括设置在封装基板2100和第一芯片层叠物2300之间的提升电介质层2250。第三半导体芯片2210可以被设置在第一芯片层叠物2300和封装基板2100之间或者提升电介质层2250和封装基板2100之间。第三半导体芯片2210可以利用第四粘合层2230附接到封装基板2100。第三半导体芯片2210可以包括控制第一半导体芯片2310和第二半导体芯片2410的操作的控制器芯片。第三半导体芯片2210的第三芯片焊盘2211可以通过用作第四互连器2270的第四接合导线电连接到封装基板2100的第三接合指2111。
根据实施方式，半导体封装件可以包括设置在封装基板上的上芯片层叠物、下芯片层叠物和支承块。上芯片层叠物可以被下芯片层叠物和支承块支承。支承块可以包括穿透支承块的块主体的穿通孔结构，并且穿通孔结构可以提供将上芯片层叠物电连接到封装基板的电路径。
图9示出了说明包括采用根据实施方式的半导体封装件中的至少一个的存储卡7800的电子***的框图。存储卡7800包括诸如非易失性存储器装置这样的存储器7810以及存储器控制器7820。存储器7810和存储器控制器7820可以存储数据或者读出所存储的数据。存储器7810和存储器控制器7820中的至少一个可以包括根据所描述实施方式的半导体封装件中的至少一个。
存储器7810可以包括应用了本公开的实施方式的技术的非易失性存储器装置。存储器控制器7820可以控制存储器7810，使得响应于来自主机7830的读/写请求，读出所存储的数据或者将数据进行存储。
图10示出了说明包括根据所描述实施方式的半导体封装件中的至少一个的电子***8710的框图。电子***8710可以包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可以通过总线8715相互联接，总线8715提供了供数据移动通过的路径。
在一个实施方式中，控制器8711可以包括一个或更多个微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同的功能的逻辑器件。控制器8711或存储器8713可以包括根据本公开的实施方式的半导体封装件中的一个或更多个。输入/输出装置8712可以包括从小键盘、键盘、显示装置、触摸屏等当中选择的至少一个。存储器8713是用于存储数据的装置。存储器8713可以存储将由控制器8711执行的数据和/或命令等。
存储器8713可以包括诸如DRAM这样的易失性存储器装置和/或诸如闪速存储器这样的非易失性存储器装置。例如，可以将闪速存储器安装到诸如移动终端和台式计算机这样的信息处理***。闪速存储器可以构成固态盘(SSD)。在这种情况下，电子***8710可以将大量数据稳定地存储在闪速存储器***中。
电子***8710还可包括接口8714，接口8714被配置为向通信网络发送数据和从通信网络接收数据。接口8714可以是有线或无线类型。例如，接口8714可包括天线或者有线或无线收发器。
电子***8710可被实现为移动***、个人计算机、工业用计算机或执行各种功能的逻辑***。例如，移动***可以是个人数字助理(PDA)、便携式计算机、平板电脑、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐***和信息发送/接收***中的任一个。
如果电子***8710表示能够执行无线通信的设备，则电子***8710可以被用在使用CDMA(码分多址)、GSM(全球移动通信***)、NADC(北美洲数字蜂窝)、E-TDMA(增强时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)技术的通信***中。
已经出于例示目的公开了本公开的实施方式。本领域的技术人员将领会的是，在不脱离本公开和所附权利要求书的范围和精神的情况下，能够进行各种修改、添加和替换。
相关申请的交叉引用
本申请要求于2018年10月18日提交的韩国专利申请No.10-2018-0124443的优先权，该韩国专利申请的全部内容以引用方式并入本文中。

Claims (20)

1.一种半导体封装件，该半导体封装件包括：
第一芯片层叠物，所述第一芯片层叠物包括在竖直方向层叠在封装基板上的第一半导体芯片，其中，所述第一半导体芯片在第一方向上偏移；
中介层，所述中介层包括重分配层图案，其中，所述中介层被设置在所述封装基板上并且与所述第一芯片层叠物横向地间隔开，并且其中，所述重分配层图案包括第一连接部、第二连接部和将所述第一连接部连接到所述第二连接部的延伸部；
支承块，所述支承块在竖直方向层叠在所述中介层上，其中，所述支承块包括穿通孔结构，所述穿通孔结构的下端电连接到所述中介层的所述第一连接部；
第二芯片层叠物，所述第二芯片层叠物包括在竖直方向层叠在所述第一芯片层叠物和所述支承块二者上的第二半导体芯片，其中，所述第二半导体芯片在第二方向上偏移；
第一互连器，所述第一互连器将所述第一半导体芯片电连接到所述封装基板；
第二互连器，所述第二互连器将所述第二半导体芯片电连接到所述穿通孔结构的上端；以及
第三互连器，所述第三互连器将所述重分配层图案的所述第二连接部电连接到所述封装基板。
2.根据权利要求1所述的半导体封装件，其中，所述第一互连器位于所述第一芯片层叠物的与所述支承块相反的一侧。
3.根据权利要求1所述的半导体封装件，
其中，所述第一互连器是第一接合导线，所述第一接合导线将所述第一半导体芯片彼此电连接并且延伸以接合到所述封装基板；
其中，所述第二互连器是第二接合导线，所述第二接合导线将所述第二半导体芯片彼此电连接并且延伸以接合到所述穿通孔结构；并且
其中，所述第三互连器是第三接合导线，所述第三接合导线的一端接合到所述第二连接部并且其另一端连接到所述封装基板。
4.根据权利要求1所述的半导体封装件，其中，所述支承块还包括：
块主体，所述块主体包括第一区域和第二区域，所述穿通孔结构位于所述第一区域中，所述第二芯片层叠物的边缘部与所述第二区域在竖直方向交叠；
第一通孔焊盘，所述第一通孔焊盘在所述块主体的顶表面处被暴露，以提供所述穿通孔结构的上端；
第二通孔焊盘，所述第二通孔焊盘在所述块主体的底表面处被暴露，以提供所述穿通孔结构的下端；以及
所述穿通孔结构的垂直通孔部，所述垂直通孔部将所述第一通孔焊盘连接到所述第二通孔焊盘。
5.根据权利要求4所述的半导体封装件，
其中，所述块主体包括硅主体；并且
其中，所述垂直通孔部包括穿透所述硅主体的硅通孔TSV。
6.根据权利要求4所述的半导体封装件，该半导体封装件还包括第一粘合层，所述第一粘合层被设置在所述块主体的所述第二区域与所述第二芯片层叠物之间。
7.根据权利要求6所述的半导体封装件，其中，所述第一粘合层延伸到所述第二芯片层叠物与所述第一芯片层叠物之间的界面中。
8.根据权利要求4所述的半导体封装件，
其中，所述第二芯片层叠物的所述第二半导体芯片当中的与最下层芯片对应的最下层第二半导体芯片包括与所述第二互连器连接的芯片焊盘；并且
其中，所述芯片焊盘被设置为与所述支承块的所述块主体的所述第二区域交叠。
9.根据权利要求1所述的半导体封装件，其中，所述支承块与所述第一芯片层叠物横向地间隔开。
10.根据权利要求1所述的半导体封装件，该半导体封装件还包括：
导电凸块，所述导电凸块被设置在所述中介层与所述支承块之间，以将所述中介层的所述第一连接部电连接到所述穿通孔结构的下端；以及
第二粘合层，所述第二粘合层包围所述导电凸块的侧表面并且将所述中介层附接到所述支承块。
11.根据权利要求10所述的半导体封装件，其中，所述第二粘合层包括非导电膜NCF。
12.根据权利要求1所述的半导体封装件，该半导体封装件还包括第三粘合层，所述第三粘合层被设置在所述中介层与所述封装基板之间，以将所述中介层附接到所述封装基板。
13.根据权利要求12所述的半导体封装件，
其中，所述封装基板包括连接到所述第三互连器的接合指；
其中，所述中介层使用所述第三粘合层附接到所述封装基板，以使所述封装基板的所述接合指暴露；并且
其中，所述接合指被设置为与所述第二芯片层叠物交叠。
14.根据权利要求1所述的半导体封装件，其中，所述支承块与所述中介层的一部分交叠，以使所述第二连接部暴露。
15.根据权利要求1所述的半导体封装件，其中，所述第二方向与所述第一方向相反。
16.根据权利要求1所述的半导体封装件，该半导体封装件还包括：
第三半导体芯片，所述第三半导体芯片被设置在所述第一芯片层叠物与所述封装基板之间；以及
提升电介质层，所述提升电介质层被设置成覆盖所述第三半导体芯片并且提升并支承所述第一芯片层叠物。
17.根据权利要求16所述的半导体封装件，其中，所述第三半导体芯片是控制所述第一半导体芯片和第二半导体芯片的操作的控制器芯片。
18.根据权利要求1所述的半导体封装件，
其中，所述第一芯片层叠物和所述支承块被设置在所述封装基板上，使得与所述第一芯片层叠物的顶表面对应的第一顶表面和与所述支承块的顶表面对应的第二顶表面位于基本相同的水平；并且
其中，所述第二芯片层叠物被设置在所述第一芯片层叠物的所述第一顶表面和所述支承块的所述第二顶表面二者上。
19.一种半导体封装件，该半导体封装件包括：
封装基板，所述封装基板包括接合指；
第一芯片层叠物，所述第一芯片层叠物以与所述接合指间隔开的方式设置在所述封装基板上，所述第一芯片层叠物包括被层叠成在第一方向上偏移的第一半导体芯片；
支承块，所述支承块以与所述第一芯片层叠物间隔开的方式设置在所述封装基板上，所述支承块包括穿通孔结构，所述穿通孔结构具有电连接到所述接合指的下端；
第二芯片层叠物，所述第二芯片层叠物包括在竖直方向层叠在所述第一芯片层叠物和所述支承块二者上的第二半导体芯片，其中，所述第二半导体芯片在第二方向上偏移；
第一互连器，所述第一互连器将所述第一半导体芯片电连接到所述封装基板；以及
第二互连器，所述第二互连器将所述第二半导体芯片电连接到所述穿通孔结构的上端。
20.根据权利要求19所述的半导体封装件，
其中，所述第一芯片层叠物和所述支承块被设置在所述封装基板上，使得与所述第一芯片层叠物的顶表面对应的第一顶表面和与所述支承块的顶表面对应的第二顶表面位于基本相同的水平；并且
其中，所述第二芯片层叠物被设置在所述第一芯片层叠物的所述第一顶表面和所述支承块的所述第二顶表面二者上。
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