CN111063668A - 布线结构、半导体装置结构及其制造方法 - Google Patents

布线结构、半导体装置结构及其制造方法 Download PDF

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CN111063668A
CN111063668A CN201910979322.8A CN201910979322A CN111063668A CN 111063668 A CN111063668 A CN 111063668A CN 201910979322 A CN201910979322 A CN 201910979322A CN 111063668 A CN111063668 A CN 111063668A
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layer
conductive
redistribution
electrical pad
semiconductor device
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竺明宪
王启宇
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明揭示一种布线结构，其包含重布层及电衬垫。所述重布层包含钝化层及金属层。所述金属层嵌入在所述钝化层中，且所述钝化层具有开口以暴露所述金属层的部分。所述电衬垫位在所述钝化层的所述开口中及所述金属层上。所述电衬垫包含晶种层、导电层、势垒层及抗氧化层。

Description

布线结构、半导体装置结构及其制造方法
技术领域
本发明涉及布线结构(wiring structure)，半导体装置结构及制造方法，且涉及用于扇出(fan-out)封装的布线结构及半导体装置结构，以及用于制造所述布线结构及半导体装置结构的方法。
背景技术
在半导体装置结构的制造过程中，半导体裸片(semiconductor die)可通过焊接接头(solder joint)连接到衬底(substrate)的电衬垫(electrical pad)。然后，可多次进行多个热处理(thermal processes)以在随后的制造步骤期间形成半导体装置结构的其它元件(例如，重布层(redistribution layer)或导电柱(conductive post))。然而，这些热处理可能不利地影响焊接接头的质量，导致可靠性(reliability)差。
发明内容
在一些实施例中，布线结构包含重布层及电衬垫。所述重布层包含钝化层(passivation)及金属层。所述金属层嵌入所述钝化层中，且所述钝化层具有开口以暴露所述金属层的一部分。所述电衬垫位在所述钝化层的所述开口中及所述金属层上。所述电衬垫包含晶种层(seed layer)、导电层、势垒层(barrier layer)及抗氧化层。
在一些实施例中，半导体装置结构包含第一重布层、电衬垫、半导体裸片、至少一个第一导电柱及封装体(encapsulant)。电衬垫位在第一重布层上。电衬垫包含导电层及势垒层。半导体裸片位在第一重布层上且电连接到电衬垫。第一导电柱位在第一重布层上且与半导体裸片相邻。封装体覆盖半导体裸片及第一导电柱。
在一些实施例中，用于制造半导体装置结构的方法包含：(a)形成第一重布层；(b)在第一重布层上形成电衬垫，其中电衬垫包含导电层、势垒层及抗氧化层；(c)在第一重布层上形成至少一个导电柱；(d)在第一重布层上安置半导体裸片；(e)形成封装体以覆盖半导体裸片及导电柱。
附图说明
当与附图一起阅读时，可从以下详述描述最佳理解本发明的一些实施例的方面。应注意，各种结构可能并未按比例绘制，且为论述的清晰性可任意增加或减小各种结构的尺寸。
图1说明根据本发明的一些实施例的布线结构的实例的截面图。
图2说明图1中所展示的区域“A”的放大视图。
图3说明根据本发明的一些实施例的布线结构的实例的截面图。
图4说明图3中所展示的区域“B”的放大视图。
图5说明根据本发明的一些实施例的半导体装置结构的实例的截面图。
图6说明图3中所展示的区域“C”的放大视图。
图7说明根据本发明的一些实施例的半导体装置结构的一部分的实例的截面图。
图8根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图9根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图10根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图11根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图12根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图13根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图14根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图15根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图16根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图17根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图18根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图19根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图20根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图21根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图22根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图23根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图24根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图25根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图26根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图27根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图28根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图29根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图30根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图31根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图32根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图33根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图34根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图35根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图36根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
图37根据本发明的一些实施例说明用于制造半导体装置结构的方法的实例的一或多个阶段。
具体实施方式
贯穿图式及详细描述使用共用参考编号来指示相同或类似组件。本发明的实施例从结合附图进行的以下详细描述将更容易理解。
以下揭露内容提供用于实施所提供标的物的不同特征的许多不同实施例或实例。下文描述组件及布置的特定实例以揭示本发明的某些方面。当然，这些仅为实例且并不意欲为限制性。举例来说，在随后描述中将第一特征形成于第二特征上方或其上可包含其中第一特征与第二特征以直接接触方式形成或安置的实施例，且还可包含其中可在第一特征与第二特征之间形成或安置额外特征使得第一特征与第二特征可不直接接触的实施例。另外，本发明可在各种实例中重复参考编号及/或字母。此重复是出于简约及清楚的目的且自身并不指示所论述的各种实施例及/或配置之间的关系。
在一些实施例中，半导体装置结构的制造工艺可包括以下步骤。首先，提供包含电衬垫的衬底。电衬垫可由铜制成。然后通过由锡或包含锡的合金制成的焊接接头将半导体裸片连接到电衬垫。然后，可在衬底上形成至少一个导电柱并与半导体裸片相邻，且可形成封装体以覆盖半导体裸片及导电柱。此外，导电柱的一端可从封装体暴露以用于外部连接。然后，可在封装体上形成包含至少一个钝化层的重布层以电连接导电柱。形成导电柱、封装体及重布层的步骤涉及热处理。在热处理期间，电衬垫的铜容易扩散到由锡或包含锡的合金制成的焊接接头中，因此在焊接接头与电衬垫的接合处形成大量的金属间化合物(intermetallic compound,IMC)，包含Cu6Sn5及/或Cu3Sn。大量的IMC可能降低焊接接头的机械强度，因此不利地影响半导体装置结构的可靠性。例如，焊接接头与电衬垫之间的边界(boundary)可能容易破裂。
本发明的至少一些实施例提供布线结构及/或半导体装置结构，其可减少在焊接接头中IMC的量及/或改善焊接接头中IMC的成分。在一些实施例中，布线结构包含电衬垫，且电衬垫包含晶种层、导电层、势垒层及抗氧化层。在一些实施例中，半导体装置结构包含电衬垫，且所述电衬垫包含导电层及势垒层。本发明的至少一些实施例进一步提供用于制造半导体装置结构的技术。
图1说明根据本发明的一些实施例的布线结构1的截面图。图2说明图1中所展示的区域“A”的放大视图。布线结构1包含第一重布层10(例如，包含钝化层18及金属层17)，以及电衬垫2。在一些实施例中，布线结构1可进一步包含多个电路层，例如第一电路层(例如，包含钝化层12及金属层11)，位在第一电路层上的第二电路层(例如，包含钝化层14及金属层13)，以及位在第二电路层上的第三电路层(例如，包含钝化层16及金属层15)。第一重布层10位在第三电路层上。布线结构1可为衬底或衬底的部分。
如图1中所展示，第一重布层10包含钝化层18及金属层17。钝化层18具有上表面181及与上表面181相对的下表面182。金属层17邻近于下表面182。例如，金属层17嵌入在钝化层18中并从钝化层18的下表面182暴露。金属层17可包含导电衬垫(conductive pad)173，导电通孔(conductive via)174及迹线(trace)(未展示)。导电通孔174电连接到第三电路层的金属层15。钝化层18具有延伸穿过钝化层18的开口180。开口180暴露金属层17的一部分，例如金属层17的导电衬垫173。钝化层18的材料可包含绝缘材料(insulatingmaterial)、介电材料(dielectric material)或阻焊材料(solder resist material)，例如基于苯并环丁烯(benzocyclobutene,BCB)的聚合物或聚酰亚胺(polyimide,PI)。在一些实施例中，钝化层18的材料可包含固化的可光成像电介质(photoimageable dielectric,PID)材料，例如环氧树脂或包含光引发剂(photoinitiators)的PI，或其它树脂材料。金属层17的材料可包含铜，另一导电金属或其合金。钝化层18的厚度可为约7μm，且金属层17的厚度可为约4μm。
电衬垫2位在钝化层18的开口180中及金属层17上。电衬垫2具有上表面201，与上表面201相对的下表面202，以及在上表面201与下表面202之间延伸的侧表面203。下表面202可接触第一重布层10的金属层17的导电衬垫173。电衬垫2包含晶种层21、导电层22、势垒层23及抗氧化层24。电衬垫2可适用于连接到半导体裸片。如图1及2中所展示，上表面201为抗氧化层24的表面，且下表面为晶种层21的表面。
晶种层21可位在开口180中且位在钝化层18的上表面181上。晶种层21可接触金属层17。晶种层21的材料可包含钛及/或铜。在一些实施例中，晶种层21包含依序位在钝化层18上的钛层及铜层。例如，钛层的厚度可为约0.1μm，且铜层的厚度可为约0.2μm到约1μm。
导电层22位在晶种层21上并与其接触。导电层22的材料可包含铜、另一导电金属或其合金。导电层22具有侧表面223，侧表面223为电衬垫2的侧表面203的一部分。导电层22的上部部分邻近势垒层23，其最大宽度可为约56μm。导电层22的下部部分邻近第一重布层10的金属层17，其最小宽度可为约30μm。导电层22的最大厚度(例如，在导电层22的中心轴处)可为约10μm，且导电层22的最小厚度(例如，在导电层22的周边处)可为约7μm。因此，导电层22可为“T”形。
势垒层23位在导电层22上并与其接触。势垒层23的材料可包含镍。势垒层23可防止或减少导电层22的材料(例如铜)扩散到抗氧化层24或形成在势垒层22上的内部连接器(internal connector)(例如，图5中所展示的内部连接器48)中。势垒层23具有上表面231及侧表面233，其为电衬垫2的侧表面203的一部分。势垒层22的最大宽度可为约60μm。导电层22的最大宽度可小于势垒层23的最大宽度，例如每侧少约1μm到约2μm。也就是说，导电层22的侧表面223可不与势垒层23的侧表面233共面(coplanar)。替代地，导电层22的侧表面223可从势垒层23的侧表面233凹进(recessed)以形成台阶结构(step structure)以形成间隙(gap)D，所述间隙D例如为约1μm到约2μm。另外，势垒层23的厚度可为约3μm。
抗氧化层24位在势垒层23(例如势垒层23的上表面231)上并与其接触。抗氧化层24的材料可包含焊料材料，例如锡、银或锡及/或银的合金。抗氧化层24覆盖势垒层23的上表面231，因此能够在随后热处理期间保护势垒层23的上表面231免受氧化。然而，值得注意的是，抗氧化层24本身可经氧化。抗氧化层24的最大宽度可为约60μm。抗氧化层24的最大宽度可基本上等于势垒层23的最大宽度。抗氧化层24的厚度可为约4μm。
电衬垫2进一步包含邻近侧表面203的氧化物层25。例如，氧化物层25可包含邻近导电层22的侧表面223的第一部分251，以及邻近势垒层23的侧表面233的第二部分252。氧化物层25的第一部分251可包含氧化铜(例如，CuOx，“x”大于0但不大于2)，且可通过氧化导电层22的***区域(peripheral region)来形成。氧化物层25的第二部分252可包含氧化镍(例如，NiOy，“y”大于0但不大于2)，且可通过氧化势垒层23的***区域来形成。导电层22及势垒层23的氧化可由于热处理而发生(例如，剥除光阻(stripping of photoresist)，固化封装化合物及/或钝化层(curing of molding compound and/or passivation layer)等)或蚀刻(etching)工艺。氧化物层25的第一部分251及第二部分252的厚度可分别为约0.7μm到约1.5μm。在一些实施例中，第一部分251的厚度可等于或不同于第二部分252的厚度。尽管图2中未展示，晶种层21及/或抗氧化层24还可包含氧化层或氧化区域。
第三电路层(例如，包含钝化层16及金属层15)位在第一重布层10的钝化层18的下表面182上或附接到第一重布层10的钝化层18的下表面182。第三电路层也可为重布层，其结构及材料可类似于上文所描述第一重布层10的结构及材料。钝化层16还可具有上表面161，及与上表面161相对的下表面162。金属层15邻近下表面162。例如，金属层15嵌入在钝化层16中且自钝化层16的下表面162暴露。金属层15还可包含导电衬垫153，导电通孔154及迹线(未展示)。例如，第一重布层10的金属层17的导电通孔174延伸穿过钝化层16，以接触并电连接第三电路层的金属层15的导电衬垫153。第三电路层的金属层15的导电通孔154电连接到第二电路层(例如，包含钝化层14及金属层13)。钝化层16的厚度可为约7μm，且金属层15的厚度可为约4μm。
第二电路层(例如，包含钝化层14及金属层13)及第一电路层(例如，包含钝化层12及金属层11)类似于第三电路层(例如，包含钝化层16及金属层15)及/或第一重布层10(例如，包含钝化层18及金属层17)，因此在下文中不再冗余重复。第二电路层的钝化层14的厚度可为约7μm，且第二电路层的金属层13的厚度可为约4μm。第一电路层的钝化层12的厚度可为约14μm，且第一电路层的金属层11的厚度可为约8.5μm。焊料球19位在第一电路层的金属层11的暴露部分上用于外部连接。在一些实施例中，布线结构1可包含多于或少于三个电路层。
由于电衬垫2包含势垒层23，因此可防止或至少减少导电层22的材料扩散穿过势垒层23。因此，可防止或减少形成在抗氧化层24或势垒层22上的内部连接器中的IMC(例如，包含Cu6Sn5及/或Cu3Sn)。避免电衬垫2与形成于其上的内部连接器(例如，图5中所展示的内部连接器48)之间的裂缝，因此改善布线结构1的可靠性。此外，抗氧化层24覆盖势垒层23的上表面231，因此能够保护势垒层23的上表面231免于在随后热处理期间氧化。在一些实施例中，势垒层23的氧化可能降低势垒层23的导电性。在随后用于熔化抗氧化层24的回焊(reflowing)过程期间，由于导电层22的最大宽度小于导电层23的最大宽度，且由于氧化物层25形成于邻近电衬垫2的侧表面203，因此可保持熔融的抗氧化层24在势垒层23上而不会向下流动以接触导电层22。
图3说明根据本发明的一些实施例的布线结构1a的实例的截面图。图4说明图3中所展示的区域“B”的放大视图。配线结构1a类似于图1及2中所展示的布线结构体1，除了电衬垫2a之外。
电衬垫2a也包含晶种层21、导电层22a、势垒层23及抗氧化层24。电衬垫2a的晶种层21、导电层22a、势垒层23及抗氧化层24分别类似于图1及2中所展示的布线结构1中的电衬垫2的晶种层21、导电层22、势垒层23及抗氧化层24。然而，如图3及4中所展示，导电层22a的最大宽度基本上等于势垒层23的最大宽度。导电层22a的侧表面223a与势垒层23的侧表面233a连续或共面。也就是说，导电层22a的侧表面223a与势垒层23的侧表面233a基本上共面。电衬垫2a也包含氧化物层25a，其类似于图1及2中所展示的布线结构体1的电衬垫2的氧化物层25。然而，由于导电层22a的侧表面223a与势垒层23的侧表面233a连续，所以第一部分251与第二部分252基本上对准。
图5说明根据本发明的一些实施例的半导体装置结构3的截面图。图6说明图5中所展示的区域“C”的放大视图。半导体装置结构3包含第一重布层10(例如，包含钝化层18及金属层17)、电衬垫2、第一电子组件34、半导体裸片4、内部连接器48、至少一个第一导电柱32、封装体33、第二重布层30(例如，包含下钝化层35、金属层36及上钝化层37)，外部连接器(external connector)38及第二电子组件5。半导体装置结构3可进一步包含多个电路层，例如第一电路层(例如，包含钝化层12及金属层11)、第二电路层(例如，包含钝化层14及金属层13)及第三电路层(例如，包含钝化层16及金属层15)。
半导体装置结构3的第一重布层10(例如，包含钝化层18及金属层17)、第一电路层(例如，包含钝化层12及金属层11)，第二电路层(例如，包含钝化层14及金属层13)，以及第三电路层(例如，包括钝化层16和金属层15)类似于图1及2中所展示的布线结构1的那些，因此在下文中不冗余重复。
半导体装置结构3的电衬垫2也类似于在图1及2中所展示的布线结构体1的电衬垫，除了半导体装置结构3的电衬垫2的抗氧化层24与半导体裸片4的预焊料(pre-solder)(例如，图21中所展示的预焊料49)熔合以形成内部连接器48。内部连接器48位在势垒层23的上表面231上并与其接触，而未接触导电层22。在其它实施例中，内部连接器48可进一步接触势垒层23的侧向表面233(如图7中所展示)
第一电子组件34位在布线结构1的最底部电路层，例如第一电路层(例如，包含钝化层12及金属层11)，上并连接到布线结构1的最底部电路层。在一些实施例中，第一电子组件34可为无源组件(passive component)。
半导体裸片4位在第一重布层10(例如，包含钝化层18及金属层17)上，且电连接到电衬垫2。半导体裸片4具有第一表面41，其可为有源表面(active surface)。如图5中所展示，半导体裸片4包含位在第一表面41上的至少一个第二导电柱45。半导体裸片4可进一步包含位在第二导电柱45上的预焊料(例如，图21中所展示的预焊料49)，且预焊料可与电衬垫2的抗氧化层24熔合以形成内部连接器48。第二导电柱45通过内部连接器48连接到电衬垫2。在一些实施例中，第二导体柱45的宽度可等于或小于势垒层22例如的最大宽度。例如，势垒层22的最大宽度可为第二导电柱45的宽度的约1.1倍。在一些实施例中，第二导电柱45包含导电区段46及势垒区段47。导电区段46连接到半导体裸片4的第一表面41，且势垒区段47连接到导电区段46。导电区段46的材料可包含铜、另一导电金属或其合金。势垒区段47的材料可包含镍。势垒区段47可防止或减少导电区段46的材料(例如铜)扩散到内部连接器48中。第二导电柱45具有侧表面453，且内部连接器48接触第二导电柱45的侧表面453。如图5及6中所展示，内部连接器48仅仅接触第二导电柱45的势垒区段47。然而，在其它实施例中，内部连接器48可接触第二导电柱45的势垒区段47及导电区段46的一小部分(如图7中所展示)。内部连接器48的材料可包含焊料材料，例如锡、银或锡及/或银的合金。在一些实施例中，内部连接器48的材料可进一步包含小量由(Cu,Ni)6Sn5制成的IMC。由包含镍的(Cu,Ni)6Sn5制成的IMC可提供大于由仅包含铜及锡的Cu6Sn5及/或Cu3Sn制成的IMC的机械强度。
第一导电柱32位在第一重布层10(例如，包含钝化层18及金属层17)上，且邻近半导体裸片4。在一个实施例中，半导体装置结构3包含围绕半导体裸片4的多个第一导电柱32。在一些实施例中，第一导电柱32位在第一重布层10的金属层17的另一导电衬垫173上并与其接触。第一导电柱32可包含晶种层325及导电区段326。晶种层325位在第一重布层10的金属层17及钝化层18上并与其接触，且导电区段326位在晶种层325上并与其接触。晶种层325的材料可包含钛及/或铜。在一些实施例中，晶种层325包含依序位在第一重布层10上的钛层及铜层。第一导电柱32的晶种层325可与电衬垫2的晶种层21同时形成。因此，第一导电柱32的晶种层325的厚度及组成可与电衬垫2的晶种层21的厚度及组成基本上相同。导电区段326的材料可包含铜、另一导电金属或其合金。
第一导电柱32可具有第一端321及与第一端321相对的第二端322。晶种层325邻近第一端321。第一端321连接第一重布层10的金属层17并与其接触。
封装体33位在第一重布层10上，例如在第一重布层10的钝化层18上，且覆盖半导体裸片4及第一导电柱32。封装体33的材料可为封装化合物或底部填料(underfill)，且可具有或不具有填料(filler)。在一些实施例中，封装体33可包封整个半导体裸片4，且可围绕第二导电柱45及电衬垫2。第一导电柱32的第二端322可从封装体33暴露。如图5中所展示，第一导电柱32的第二端322可与封装体33的上表面331基本上共面。
第二重布层30位在封装体上33且电连接到第一导体柱32。第二重分布层30可包含下钝化层35、金属层36及上钝化层37。如在图5中所展示，下钝化层35位在封装体33的上表面331上。下钝化层35具有上表面351及与上表面351相对的下表面352。下表面352接触封装体33的上表面331。下钝化层35具有延伸穿过下钝化层35的开口350。开口350暴露第一导电柱32的第二端322的至少一部分。
金属层36位在下钝化层35的上表面352及开口350中。例如，金属层36可包含接合衬垫(bonding pad)363、导电通孔364及迹线(未展示)。接合衬垫363及迹线(未展示)可位在下钝化层35的上表面351上。导电通孔364位在下钝化层35的开口350中且电连接到第一导电柱32的第二端322。
上钝化层37位在下钝化层35上及金属层36上。如图5中所展示，上钝化层37位在下钝化层35的上表面352上，且覆盖金属层36。上钝化层37可暴露金属层36的一部分(例如金属层36的接合衬垫363)用于外部连接。下钝化层35的厚度可为约18μm，金属层36的厚度可为约12μm，且上钝化层37的厚度可为约18μm。
在一些实施例中，外部连接器38位在第二重布层30的金属层36的接合衬垫363上。外部连接器38可进一步接触并连接到第二电子组件5。第二电子组件5可为随机存取存储器(random access memory,RAM)。第二电子组件5具有面向第二重布层30的下表面51，且可包含从下表面51暴露的导电衬垫53。外部连接器38连接在金属层36的接合衬垫363与第二电子组件5的导电衬垫53之间。
图7说明根据本发明的一些实施例的半导体装置结构的部分的实例的截面图。图7中所展示的半导体装置结构类似于图5及6中所展示的半导体装置结构3。然而，如图7中所展示，内部连接器48进一步接触势垒层23的侧表面233及第二导体柱45的导电区段46的一小部分。
图8到图37说明根据本发明一些实施例的制造半导体装置封装的方法。在一些实施例中，此方法用于制造图1及2中所展示的布线结构1，图3及4中所展示的布线结构1a，及/或图5及6中所展示的半导体装置结构3。
参考图8，提供第一载体(carrier)70，且形成或安置晶种层71在其上。然后，通过技术领域中已知的任何工艺依序形成第一电路层(例如，包含钝化层12及金属层11)、第二电路层(例如，包含钝化层14及金属层13)，以及第三电路层(例如，包含钝化层16及金属层15)在晶种层71上。例如，可通过在图案化光阻层(patterned photoresist layer)中电镀而形成第一电路层的金属层11在晶种层71上。金属层11的材料可包含铜，另一导电金属或其合金。在将图案化光阻层移除之后，形成第一电路层的钝化层12在晶种层71上以覆盖金属层11。钝化层12的材料可包含绝缘材料、介电材料或阻焊材料，例如基于苯并环丁烯(BCB)的聚合物或聚酰亚胺(PI)。钝化层12的材料可包含固化的可光成像电介质(PID)材料，例如环氧树脂或包含光引发剂的PI，或其它树脂材料。然后，可对钝化层12进行激光钻孔(laser drilling)工艺或图案化工艺以暴露金属层11的部分，因此形成第一电路层。
可通过类似工艺并使用与第一电路层类似的材料来形成第二电路层及第三电路层。例如，可形成第三电路层的金属层15在第二电路层上。金属层15可包含导电衬垫153、导电通孔154及迹线(未展示)。然后，可形成钝化层16在第二电路层上以覆盖金属层15。钝化层16可具有上表面161及与上表面161相对的下表面162。金属层15邻近下表面162。钝化层16暴露金属层15的部分，例如金属层15的导电衬垫153。
然后，形成第一重布层10(例如，包含钝化层18及金属层17)在第三电路层(例如第三电路层的钝化层16)上。也可通过类似的工艺并使用与第一电路层类似的材料来形成第一重布层10。例如，可形成金属层17在第三电路层的钝化层16上。金属层17可包含导电衬垫173、导电通孔174及迹线(未展示)。导电通孔174延伸穿过钝化层16以接触并连接到第三电路层的金属层15，例如金属层15的导电衬垫153。然后，可形成第一重布层10的钝化层18在第三电路层上以覆盖金属层17。钝化层18具有上表面181及与上表面181相对的下表面182。金属层17邻近于下表面182。钝化层18具有延伸穿过钝化层18的开口180。开口180暴露金属层17的一部分，例如金属层17的导电衬垫173。
参考图9，形成晶种层21a在第一重布层10上，例如形成在钝化层18的上表面181及开口180中。晶种层21a可接触并连接到第一重布层10的金属层17的导电衬垫173。晶种层21a的材料可包含钛及/或铜。在一些实施例中，晶种层21a包含依序位在钝化层18上的钛层及铜层。
参考图10，形成或安置第一光阻层72在第一重布层10(例如第一重布层10的钝化层18)上的晶种层21a上。第一光阻层72可为干膜(dry film)，其可直接安置在第一重布层10上，或可以液体形式施加。
参考图11，暴露第一光阻层72于强光图案。例如，安置光罩73邻近第一光阻层72，以覆盖第一光阻层72的部分。然后，将第一光阻层72暴露于辐射源74。
参考图12，通过显影剂来显影第一光阻层72。也就是说，图案化第一光阻层72以形成至少一个通孔720，所述至少一个通孔720暴露晶种层21a的至少一部分。例如，使位在第一重布层10的钝化层18的开口180中的晶种层21a的部分暴露。
参考图13，形成电衬垫2'在第一重布层10上及在第一光阻层72的通孔720中。例如，电衬垫2'包含依序地形成在第一光阻层72的通孔720中的晶种层21a的部分(例如，图1及2中所展示的晶种21)、导电层22a、势垒层23及抗氧化层24。
通过例如电镀形成导电层22a在晶种层21a上。导电层22a的材料可包含铜，另一导电金属或其任何合金。导电层22a具有侧表面223a，其接触第一光阻层72的通孔720。导电层22a的最大宽度可为约60μm。导电层22a的最小宽度可为约30μm。导电层22a的最大厚度可为约10μm，且导电层22a的最小厚度可为约7μm。
通过例如电镀形成势垒层23在导电层22a上。势垒层23的材料可包含镍。势垒层23具有侧表面233，其接触第一光阻层72的通孔720。势垒层23的最大宽度可为约60μm。导电层22a的侧表面223a可与势垒层23的侧表面233连续。势垒层23的厚度可为约3μm。势垒层23可防止或减少导电层22的材料(例如铜)扩散到抗氧化层24中。
通过例如电镀或焊膏印刷形成抗氧化层24在势垒层23的上表面231上。抗氧化层24的材料可包含焊料材料，例如锡、银或锡及/或银的合金。抗氧化层24覆盖势垒层23的上表面231。抗氧化层24的最大宽度可为约60μm。抗氧化层24的最大宽度可与势垒层23的最大宽度基本上相同。抗氧化层24的厚度可为约4μm。
参考图14，通过例如剥除来移除第一光阻层72。
参考图15，形成或安置第二光阻层75在第一重布层10(例如第一重布层10的钝化层18)上的晶种层21a上，且在电衬垫2’上。第二光阻层75可为干膜，其可直接安置在第一重布层10上。第二光阻层75可具有远大于第一光阻层72的厚度的厚度。
参考图16，暴露第二光阻层75于强光图案。例如，安置光罩76邻近第二光阻层75，以覆盖第二光阻层75的部分。然后，将第二光阻层75暴露于辐射源77。
参考图17，通过显影剂来显影第二光阻层75。也就是说，图案化第二光阻层75以形成至少一个通孔750，所述至少一个通孔750暴露晶种层21a的至少部分。例如，使位在第一重布层10的钝化层18的另一开口180中的晶种层21a的另一部分暴露。
参考图18，形成至少一个第一导电柱32在第一重布层10上及在第二光阻层75的通孔750中。例如，第一导电柱32包含晶种层21a的部分(例如，图5及6中所展示的晶种层325)及导电区段326。导电区段326的材料可包含铜，另一导电金属，或其合金。第一导电柱32可具有第一端321及与第一端321相对的第二端322。第一端321接触并连接到第一重布层10的金属层17。第二端322暴露在第二光阻层75的通孔750中。
参考图19，通过例如剥除来移除第二光阻层75。由于第二光阻层75的厚度大于第一光阻层72，因此第二光阻层75的剥除工艺可能需要更高温度及更长的处理时间，例如约73℃的温度约1小时。第二光阻层75的剥除过程可能导致导电层22a、势垒层23及/或抗氧化层24的氧化。例如，导电层22a及势垒层23的***区域容易被氧化。也就是说，去除第二光阻层75的步骤可包含形成氧化物层25a邻近电衬垫2a的侧表面203a。然而，势垒层23的上表面231可不被氧化，因为其被抗氧化层24覆盖。
参考图20，通过例如蚀刻移除晶种层21a的未被电衬垫2a的导电层22a或第一导电柱32的导电区段326覆盖的部分。在蚀刻工艺期间也可移除导电层22a的***区域(例如，具有约1μm到约2μm的厚度)，因此形成具有减小的最大宽度的导电层22(如图1及2或图5及6中所展示所示)。同时，电衬垫2a变成电衬垫2。因此，导电层22的最大宽度可小于势垒层23的最大宽度，例如每侧少约1μm到约2μm。也就是说，导电层22的侧表面223可位于势垒层23的侧表面233内。此外，在此蚀刻工艺期间，导电层22及势垒层23的***区域可能被进一步氧化，形成氧化物层25。氧化物层25可包含邻近导电层22的侧表面223的第一部分251，及邻近势垒层23的侧表面233的第二部分252。氧化物层25的第一部分251可包含氧化铜，且氧化物层25的第二部分252可包含氧化镍。在一些实施例中，晶种层21及/或抗氧化层24还可包含氧化层或氧化区域。在其它实施例中，在蚀刻工艺期间可不移除导电层22a的***区域，因此具有基本上等于势垒层23的最大宽度的最大宽度(如图3及4中所展示)。
参考图21，安置半导体裸片4在第一重布层10(例如，包含钝化层18及金属层17)上。半导体裸片4具有第一表面41，其可为有源表面。如图21中所展示，半导体裸片4包含位在第一表面41上的第二导电柱45。第二导电柱45包含导电区段46及势垒区段47。导电区段46连接到半导体裸片4的第一表面41，且势垒区段47连接到导电区段46。导电区段46的材料可包含铜，另一导电金属或其合金。势垒区段47的材料可包含镍。半导体裸片4可进一步包含位在第二导电柱45(例如第二导电柱45的势垒区段47)上的预焊料49。预焊料49的材料可包含焊料材料，例如锡、银或锡及/或银的合金。预焊料49接触电衬垫2的抗氧化层24。势垒区段47可防止或减少导电区段46的材料(例如铜)扩散到预焊料49中。
参考图22，半导体裸片4的预焊料49通过例如回焊工艺与电衬垫2的抗氧化层24熔合以形成内部连接器48。因此，半导体裸片4通过内部连接器48电连接到电衬垫2。在回焊工艺期间，由于导电层22的最大宽度小于势垒层23的最大宽度，且由于氧化物层25形成于邻近电衬垫2的侧表面203，因此可保持熔融的预焊料49及抗氧化层24在势垒层23上而不会向下流动以接触导电层22。然而，在其它实施例中，内部连接器48可进一步接触势垒层23的侧表面233(如图7中所展示)。第二导体柱45具有侧表面453，且内部连接器48可接触并沿着第二导体柱45的侧表面453向上流动。如图22中所展示，内部连接器48仅仅接触导电柱45d势垒区段47。然而，在其它实施例中，内部连接器48可接触势垒区段47及第二导电柱45的导电区段46(如图7中所展示)。
参考图23，形成封装体33以覆盖半导体裸片4及第一导电柱32。封装体33位在第一重布层10上，例如在第一重布层10的钝化层18上。封装体33的材料可为具有或不具有填料的封装化合物。在一些实施例中，封装体33可封装整个半导体裸片4，且可围绕第二导电柱45及电衬垫2。如图23中所展示，封装体33可覆盖第一导电柱32的第二端322。
封装体33的形成可涉及在约230℃下工艺过程中固化(in-process curing)约400秒，且在约150℃下封装后固化(post-mold curing)约1小时。这些热处理可能导致IMC(例如，包含Cu6Sn5及/或Cu3Sn)形成在锡(例如，内部连接器48)及铜(电衬垫2的导电层22或第二导电柱45的导电区段46)的结合处。然而，由于内部连接器48保持在势垒层23上而不接触导电层22，因此可以防止或至少减少内部连接器48及电衬垫2的接合处的IMC。此外，由于内部连接器48仅接触第二导电柱45的势垒区段47，因此也可防止或至少减少内部连接器48及第二导电柱45的接合处的IMC。在一些实施例中，在此热处理期间仍可能形成小量由(Cu,Ni)6Sn5制成的IMC。
参考图24，通过例如研磨(grinding)移除封装体33的部分以暴露第一导电柱32的第二端322。因此，第一导电柱32的第二端322可与封装体33的上表面331基本上共面。
参考图25，在封装体33上形成第二重布层30(例如，包含下钝化层35、金属层36及上钝化层37)，且固化第二重布层30(例如下钝化层35及上钝化层37)。可通过类似工艺并使用与第一重布层10类似的材料形成第二重布层30。例如，可形成或安置下钝化层35在封装体33的上表面331上，且可在约230℃下固化约6小时。下钝化层35具有上表面351及与上表面351相对的下表面352。下表面352接触封装体33的上表面331。下钝化层35具有延伸穿过下钝化层35的开口350以暴露第一导电柱32的第二端322的至少一部分。
然后，可形成或安置金属层36在下钝化层35的上表面352及开口350中。例如，金属层36可包含接合衬垫363、导电通孔364及迹线(未展示)。接合衬垫363及迹线(未展示)可位在下钝化层35的上表面351上。导电通孔364位在下钝化层35的开口350中且电连接到第一导电柱32的第二端322。
然后，可形成或安置上钝化层37在下钝化层35上及金属层36上，且可在约230℃下固化约6小时。上钝化层37位在下钝化层35的上表面352上，且覆盖金属层36。上钝化层37可暴露金属层36的部分(例如金属层36的接合衬垫363)用于外部连接。
在形成下钝化层35及上钝化层37期间的这些热处理可能导致IMC(例如，包含Cu6Sn5及/或Cu3Sn)形成在锡(例如，内部连接器48)及铜(电衬垫2的导电层22或第二导电柱45的导电区段46)的结合处。然而，由于内部连接器48保持在势垒层23上而不接触导电层22，因此可以防止或至少减少内部连接器48及电衬垫2的接合处的IMC。此外，由于内部连接器48仅接触第二导电柱45的势垒区段47，因此也可防止或至少减少内部连接器48及第二导电柱45的接合处的IMC。在一些实施例中，在此热处理期间仍可能形成小量由(Cu,Ni)6Sn5制成的IMC。
参考图26，形成或安置外部连接器38在第二重布层30的金属层36的接合衬垫363上。例如，外部连接器38可为通过焊膏印刷及回焊工艺形成的焊料球。
参考图27，提供第二载体80，其具有位在其上的粘合剂层81。附接第二重布层30到第二载体80，且嵌入外部连接器38在粘合剂层81中。
参考图28，移除第一载体70，使得晶种层71暴露。
参考图29，通过例如蚀刻来移除晶种层71。因此暴露第一电路层的金属层11的部分。
参考图30，通过例如焊膏印刷及回焊工艺形成或安置焊料球19在第一电路层的金属层11的暴露部分上。
参考图31，安置第一电子组件34在第一电路层上并连接到第一电路层，例如第一电路层的金属层11。在一些实施例中，第一电子组件34可为无源组件。
参考图32，附接胶带82到第一电路层，且焊料球19及第一电子组件34可嵌入胶带82中。
参考图33，附接框架(frame)83到胶带82。然后，移除第二载体80及粘合剂层81。
参考图34，通过另一胶带84附接第二重布层30到另一框架85。然后，移除框架83及胶带82。
参考图35，进行分割工艺(singulation process)以切穿第一电路层(例如，包含钝化层12及金属层11)、第二电路层(例如，包含钝化层14及金属层13)、第三电路层(例如，包含钝化层16及金属层15)、第一重布层10(例如，包含钝化层18及金属层17)、封装体33及第二重布层30(例如，包含下钝化层35、金属层36及上钝化层37)。
参考图36，移除载体85及胶带84。然后，安置第二电子组件5在第二重布层30上且与外部连接器38接触。第二电子组件5可为随机存取存储器(RAM)。第二电子组件5具有面向第二重布层30的下表面51，且可包含从下表面51暴露的导电衬垫53。外部连接器38接触导电衬垫53。
参考图37，进行回焊工艺以将第二电子组件5连接到第二重布层30，因此形成在图3及4中所展示的半导体装置结构3。外部连接器38连接在金属层36的接合衬垫363与第二电子组件5的导电衬垫53之间。
在一些实施例中，在图14中所展示的阶段之后，可移除未被导电层22a覆盖的晶种层21a的部分，且可在移除载体之后将焊料球19位在第一电路层的金属层11的暴露部分上，因此形成图1及2中所展示的布线结构1。例如，可通过蚀刻移除晶种层21a的部分，且还可蚀刻导电层22a的***区域(例如，具有大约1μm到大约2μm的厚度)，从而形成图1中所展示的导电层22。因此，导电层22的最大宽度可小于势垒层23的最大宽度，例如在每一侧减小约1μm到约2μm。也就是说，导电层22的侧表面223可位于势垒层23的侧表面233内。此外，在此蚀刻工艺期间，导电层22及势垒层23的***区域可经氧化，因而形成邻近电衬垫2的侧表面203的氧化物层25。氧化物层25可包含经安置邻近导电层22的侧表面223的第一部分251，及经安置邻近势垒层23的侧表面233的第二部分252。氧化物层25的第一部分251可包含氧化铜，且氧化物层25的第二部分252可包含氧化镍。尽管未在图1中展示，晶种层21及/或抗氧化层24还可包行氧化层或氧化区域。在其它实施例中，导电层22a的***区域不被蚀刻，因此形成在图3及4中所展示的布线结构1a。
除非另有规定，否则例如“在...上面”、“在...下面”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“较高”、“下部”、“上部”、“在...上方”、“在...下方”等等的空间描述是相对于图中所展示的定向指示。应理解，本文中所使用的空间描述仅出于说明的目的，且本文中所描述的结构的实际实施方案可以任一定向或方式进行空间布置，只要此布置不背离本发明的实施例的优点。
如本文中所使用，术语“大约”，“基本上”，“基本”和“约”用于描述及考虑小变化。在结合事件或情形使用时，所述术语可是指其中确切地发生事件或情形的例子以及其中近似地发生事件或情形的例子。举例来说，当结合数值使用时，所述术语可是指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么所述值可被认为基本上相同或相等。
如果两个表面之间的位移不大于5μm，不大于2μm，不大于1μm，或不大于0.5μm，那么两个表面可被认为共面或基本上共面。
如本文中所使用，除非上下文另有明确指示，否则单数术语“一(a)”、“一(an)”和“所述”可包含复数对象。
如本文中所使用，术语“导电”、“导电”及“导电率”是指传输电流的能力。导电材料通常指示展现对电流流动的极少或零对抗的那些材料。导电率的一个度量为西门子/米(S/m)。通常，导电材料为具有大于大约104S/m的导电性的材料，例如至少105S/m或至少106S/m。材料的导电性可有时随温度变化。除非另有规定，否则材料的导电性是在室温下进行测量。
另外，数量、比率及其它数值有时在本文中以范围格式呈现。应理解，此范围格式是出于便利及简洁起见而使用且应灵活地理解为包含明确规定为范围的限制的数值，而且还包含所述范围内囊括的所有个别数值或子范围，犹如每一数值及子范围是明确规定的。
虽然已参考本发明的特定实例描述并说明本发明，但这些描述及说明并非限制性。所属领域的技术人员应理解，在不背离如随附权利要求书所界定的本发明的真实精神及范围的情况下，可做出各种改变且可替代等效物。说明可不必按比例绘制。由于制造过程及容限，因此本发明中的精巧呈现与实际设备之间可存在差异。可存在本发明的未具体说明的其它实施例。说明书及图式应视为说明性而非限制性。可进行修改以使特定情况，材料，物质组合物，方法或过程适应本发明的目的，精神及范围。所有此些修改意欲属于随附的权利要求书的范围内。虽然已参考以特定次序执行的特定操作来描述本文中所揭示的方法，但应理解，可在不背离本发明的教示的情况下将这些操作组合、细分或重新排序以形成等效方法。因此，除非本文中特别指明，否则操作的次序及分组并非本发明的限制。

Claims (20)

1.一种布线结构，其包括：
重布层，其包括钝化层及金属层，其中所述金属层嵌入在所述钝化层中，且所述钝化层具有开口以暴露所述金属层的部分；及
电衬垫，其位在所述钝化层的所述开口中及在金属层上，其中所述电衬垫包括晶种层、导电层、势垒层及抗氧化层。
2.根据权利要求1所述的布线结构，其中所述电衬垫进一步包括氧化物层，其邻近所述电衬垫的侧表面。
3.根据权利要求1所述的布线结构，其中所述导电层包含铜，且所述势垒层包含镍。
4.根据权利要求3所述的布线结构，其中所述氧化物层包含第一部分，其邻近所述导电层的侧表面，且所述氧化物层的所述第一部分包含氧化铜。
5.根据权利要求3所述的布线结构，其中所述氧化物层包含第二部分，其邻近所述势垒层的侧表面，且所述氧化物层的所述第二部分包含氧化镍。
6.根据权利要求1所述的布线结构，其中所述导电层接触所述晶种层，且所述势垒层接触所述导电层。
7.根据权利要求1所述的布线结构，其中所述导电层的最大宽度小于所述势垒层的最大宽度。
8.一种半导体装置封装，其包括：
第一重布层；
电衬垫，其位在所述第一重布层上，其中所述电衬垫包括导电层及势垒层；
半导体裸片，其位在所述第一重布层上且电连接到所述电衬垫；
至少一个第一导电柱，其位在所述第一重布层上且邻近所述半导体裸片；及
封装体，其覆盖所述半导体裸片及所述第一导电柱。
9.根据权利要求8所述的半导体装置结构，其中所述电衬垫进一步包括氧化物层，其邻近所述电衬垫的侧表面。
10.根据权利要求8所述的半导体装置结构，其中所述电衬垫进一步包括晶种层，所述导电层接触所述晶种层，且所述势垒层接触所述导电层。
11.根据权利要求8所述的半导体装置结构，其中所述半导体裸片包含第二导电柱，所述第二导电柱通过内部连接器连接到所述电衬垫，且所述内部连接器接触所述第二导电柱的侧表面。
12.根据权利要求8所述的半导体装置结构，还包括第二重布层，所述第二重布层位在所述封装体上并且电连接到所述第一导电柱。
13.根据权利要求12所述的半导体装置结构，其中所述第二重布层包括结合衬垫。
14.一种用于制造半导体装置结构的方法，其包括：
(a)形成第一重布层；
(b)形成电衬垫在所述第一重布层上，其中所述电衬垫包括导电层、势垒层及抗氧化层；
(c)形成至少一个导电柱在所述第一重布层上；
(d)将半导体裸片安置在所述第一重布层上；以及
(e)形成封装体以覆盖所述半导体裸片及所述导电柱。
15.根据权利要求14所述的方法，其中在步骤(c)之前，所述方法进一步包括：
(c0)形成光阻层在所述电衬垫上，其具有至少一个通孔；及
其中在步骤(c)中，所述导电柱形成在所述光阻层的所述通孔中。
16.根据权利要求15所述的方法，其中所述光阻层为干膜。
17.根据权利要求15所述的方法，其中在步骤(c)之后，所述方法进一步包括：
(c1)移除所述光阻层。
18.根据权利要求17所述的方法，其中步骤(c1)进一步包括：
形成氧化物层，其邻近所述电衬垫的侧表面。
19.根据权利要求14所述的方法，其中在步骤(e)之后，所述方法进一步包括：
(e1)形成第二重布层在所述封装体上；及
(e2)固化所述第二重布层。
20.根据权利要求19所述的方法，其中在步骤(e2)中之后，所述方法进一步包括：
(e3)形成外部连接器在所述第二重布层上。
CN201910979322.8A 2018-10-16 2019-10-15 布线结构、半导体装置结构及其制造方法 Pending CN111063668A (zh)

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