CN110941510B - Online reloading circuit and method for FPGA - Google Patents
Online reloading circuit and method for FPGA Download PDFInfo
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- CN110941510B CN110941510B CN201911112286.1A CN201911112286A CN110941510B CN 110941510 B CN110941510 B CN 110941510B CN 201911112286 A CN201911112286 A CN 201911112286A CN 110941510 B CN110941510 B CN 110941510B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention belongs to the technical field of digital circuits, and provides an on-line reloading circuit and method of an FPGA. The method comprises the steps that whether the FPGA is successfully loaded is detected based on a heartbeat signal, when the failure of the FPGA in power-on loading is detected, the MCU starts an online reloading process, and a target file stored in an external FLASH is transmitted to the FPGA through a JTAG protocol realized by GPIO of the target file; the method and the device can detect whether the FPGA is successfully powered on and start an online reloading process when the powering on fails, realize the online reloading of the FPGA, avoid unsuccessful loading of the FPGA and obviously improve the reliability of products.
Description
Technical Field
The invention provides an FPGA online reloading circuit and method, belongs to the technical field of digital circuits, and is particularly suitable for the field of airborne computers with high reliability requirements.
Background
The FPGA of the SRAM technology belongs to a power-down volatile element, when a product is powered on, a target file stored in a PROM is required to be loaded into the FPGA, and after loading is completed, the FPGA can complete specified work according to design requirements. However, in practical application, the phenomenon that the loading of the FPGA is unsuccessful due to various reasons such as power supply jitter and PROM abnormality often occurs, so that the product functions fail and then malfunction occurs. The current common reloading strategy is to restart the process of loading from PROM by resetting the PROGRAM signal after the power-on loading fails, and belongs to the homomorphic reloading method, and the probability of successful reloading is smaller because the power-on loading process has failed. Aiming at the problems, the invention provides a heterogeneous reloading strategy, and after the power-on loading fails, the loading is carried out again through a JTAG interface, so that the probability of successful reloading of the FPGA is improved, and the reliability of the product is obviously improved.
Disclosure of Invention
The invention aims to:
the FPGA online reloading circuit and method can detect whether the power-on loading is successful or not and finish the online reloading of the FPGA when the power-on loading fails.
The technical scheme is as follows:
the invention provides an FPGA online reloading method, which comprises the steps that an MCU realizes JTAG protocol through GPIO, and a target file is called from FLASH to reload the FPGA.
Preferably, the FPGA online reloading method,
the method comprises the following steps:
step 1, MCU detects whether the loading of FPGA is successful, if the loading is unsuccessful, enter step 2;
step 2, the MCU configures the direction of the GPIO according to JTAG signal definition;
and 3, the MCU reads the target file from the FLASH, and transmits the target file to the FPGA through the GPIO defined in the step 2 to finish reloading.
Preferably, in the method for online reloading of an FPGA, the step 1 of detecting whether the power-on loading of the FPGA is successful specifically includes:
the MCU acquires an FPGA heartbeat signal after the FPGA is powered on and loaded, if the heartbeat signal is normal, the FPGA is powered on and loaded successfully, and if the heartbeat signal is abnormal, the FPGA is powered on and loaded failed.
Preferably, in the on-line reloading method of the FPGA, the 4 GPIO pins of the MCU are directly connected with the 4 signal lines of the JTAG connector, and the default state of the 4 GPIOs of the MCU is high-impedance;
in the step 2, the MCU configures the directions of 4 GPIOs respectively according to JTAG signal definition;
and (3) after the step (3) is finished, the MCU configures the states of the 4 GPIOs as high resistance.
Preferably, in the on-line reloading method of the FPGA, the FPGA is provided with a heartbeat signal driving circuit, and after the power-on loading is completed, if the power-on loading is successful, the heartbeat pin outputs a heartbeat signal, and the heartbeat signal is a square wave with specified frequency and duty ratio; if the power-on loading is unsuccessful, no heartbeat signal is generated.
The invention also provides an FPGA online reload circuit, which comprises an MCU and a FLASH, wherein the online reload object is the FPGA, the GPIO pin of the MCU is connected with the JTAG interface of the FPGA, the MCU is connected with the FPGA through a heartbeat signal line, and the MCU is connected with the FLASH.
Preferably, in the on-line reloading circuit for the FPGA, a JTAG interface of the FPGA is linked with a JTAG connector, 4 GPIO pins of the MCU are directly connected with 4 signal lines of the JTAG connector, and a default state of the 4 GPIOs of the MCU is high-impedance; when offline, loading is performed by using the simulator to connect with the JTAG connector;
preferably, in the on-line reloading circuit for the FPGA, the MCU detects whether the FPGA is loaded successfully through a heartbeat signal line, if no heartbeat signal is detected after the FPGA is powered on, the MCU configures the direction of the GPIO according to the JTAG signal definition, and invokes the target file from the FLASH, and transmits the target file to the FPGA through the GPIO, so as to complete reloading.
The beneficial effects are that:
the invention provides an FPGA online reloading circuit and method, which can detect whether the FPGA is successfully powered on and start an online reloading flow when the power on fails, so that the online reloading of the FPGA is realized, unsuccessful loading of the FPGA is avoided, and the reliability of products is obviously improved.
Drawings
The foregoing advantages of the invention, as well as a description of embodiments thereof, will be apparent and readily appreciated from the following drawings in which:
FIG. 1 is a circuit diagram of an FPGA on-line reload of the present invention;
FIG. 2 is a schematic representation of an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and detailed description.
FIG. 1 provides an FPGA online reload circuit, which comprises an MCU and a FLASH, wherein the online reload object is an FPGA;
optionally, the FLASH stores a target file;
optionally, offline loading using the emulator to connect the JTAG connector is also supported;
optionally, the 4 GPIO pins of the MCU are directly connected with the 4 signal lines of the JTAG connector, and the default state of the 4 GPIOs of the MCU is high-impedance;
optionally, the MCU is connected with the FPGA through a heartbeat signal line;
optionally, the FPGA is provided with a heartbeat signal driving circuit, and after the power-on loading is completed, the heartbeat pin outputs a heartbeat signal, wherein the heartbeat signal is a square wave with a specified frequency and duty cycle;
in order to apply the circuit shown in fig. 1, an FPGA online reloading method is provided, which includes:
detecting whether the FPGA is successfully powered on or not based on a heartbeat signal line;
when the power-on loading failure of the FPGA is detected, starting an FPGA reloading flow, configuring the directions of 4 GPIOs according to JTAG signal definition, reading a target file from an external FLASH, transmitting the target file to the FPGA through a JTAG interface realized by the GPIOs, and configuring the 4 GPIOs into high resistance;
optionally, the MCU acquires a heartbeat signal after the FPGA is powered on and loaded, if the heartbeat signal is normal, the FPGA is powered on and loaded successfully, and if the heartbeat signal is abnormal, the FPGA is powered on and loaded failed;
fig. 2 provides an embodiment of the present invention, as shown in fig. 2:
XC4VLX25 type FPGA is used as an online loading object. XC4VLX25 is an FPGA of SRAM technology, and belongs to a power-down volatile element, so PROM needs to be configured for the FPGA to store binary target files, where the model of the PROM is XCF32P, and the format of the target files is MCS; the FPGA and the PROM are connected with a maintenance JTAG connector through a JTAG chain, and four signal lines of the JTAG are simultaneously connected to four GPIOs of the MCU; the MCU is configured with an external FLASH, and the FLASH stores target codes in an XSVF format, wherein the target codes are obtained by converting target codes in a BIT format through an iMPACT tool. After the product is powered on, the XC4VLX25 type FPGA loads binary target codes from the PROM through a parallel bus [ D7D 0], and the following two conditions exist: (i) the heartbeat signal is normal. After the FPGA is powered on and loaded, a heartbeat pin of the FPGA outputs a heartbeat signal with a designated frequency and a duty ratio, and the MCU captures the heartbeat signal. The heartbeat signal normally indicates that the FPGA is successfully powered on and loaded, and the MCU does not need to execute an online reloading process; (ii) abnormal heartbeat signal. After the FPGA is powered on and loaded, a heartbeat pin of the FPGA outputs a heartbeat signal with a designated frequency and a duty ratio, and the MCU captures the heartbeat signal. The abnormal heartbeat signal indicates that the FPGA fails to be powered on and loaded, and the MCU needs to execute an online reload program: (1) configuring the directions of four GPIOs according to JTAG signal definition; (2) reading a target code from the FLASH; (3) transmitting the target file to the FPGA through JTAG protocol; (4) configuring the four GPIOs to be high-impedance.
When the FPGA finishes the power-on loading and detects that the heartbeat signal is abnormal, after the MCU executes the online loading program, the MCU captures the heartbeat signal again, and if the heartbeat signal is normal, the FPGA is successfully reloaded online; if the heartbeat signal is still abnormal, the FPGA is proved to fail to reload online, and the fault condition needs to be reported to the upper computer.
The conventional reloading strategy is that after the power-on loading fails, the process of loading from the PROM is restarted by resetting the PROGRAM signal, and the method belongs to an isomorphic reloading method, and because the power-on loading process fails, the probability of successful reloading is smaller; the method of the invention reloads through JTAG interface instead of parallel interface after the power-on loading fails, belongs to heterogeneous reloading method, and has higher probability of successful reloading.
Claims (3)
1. An FPGA online reloading method is characterized in that an MCU realizes JTAG protocol through GPIO, and a target file is called from FLASH to reload the FPGA;
the method comprises the following steps:
step 1, MCU detects whether the loading of FPGA is successful, if the loading is unsuccessful, enter step 2;
step 2, the MCU configures the direction of the GPIO according to JTAG signal definition;
step 3, the MCU reads the target file from the FLASH, and transmits the target file to the FPGA through the GPIO defined in the step 2 to finish reloading;
step 1, detecting whether the power-on loading of the FPGA is successful specifically comprises the following steps:
the MCU acquires an FPGA heartbeat signal after the FPGA is electrified and loaded, if the heartbeat signal is normal, the FPGA is electrified and loaded successfully, and if the heartbeat signal is abnormal, the FPGA is electrified and loaded failed;
the 4 GPIO pins of the MCU are directly connected with the 4 signal lines of the JTAG connector, and the default state of the 4 GPIO pins of the MCU is high-resistance;
in the step 2, the MCU configures the directions of 4 GPIOs respectively according to JTAG signal definition;
and (3) after the step (3) is finished, the MCU configures the states of the 4 GPIOs as high resistance.
2. The method for online reloading of the FPGA according to claim 1, wherein the FPGA is provided with a heartbeat signal driving circuit, and after the power-on loading is completed, if the power-on loading is successful, a heartbeat pin outputs a heartbeat signal, and the heartbeat signal is a square wave with specified frequency and duty ratio; if the power-on loading is unsuccessful, no heartbeat signal is generated.
3. The on-line reloading circuit for the FPGA is characterized by comprising an MCU and a FLASH, wherein the object of the on-line reloading is the FPGA, a GPIO pin of the MCU is connected with a JTAG interface of the FPGA, the MCU is connected with the FPGA through a heartbeat signal line, and the MCU is connected with the FLASH;
the JTAG interface of the FPGA is connected with the JTAG connector, 4 GPIO pins of the MCU are directly connected with 4 signal lines of the JTAG connector, and the default state of 4 GPIOs of the MCU is high resistance; when offline, loading is performed by using the simulator to connect with the JTAG connector;
and the MCU detects whether the FPGA is successfully loaded or not through a heartbeat signal line, if the heartbeat signal is not detected after the power-on, the MCU configures the direction of the GPIO according to the definition of JTAG signals, invokes a target file from the FLASH, and transmits the target file to the FPGA through the GPIO to finish reloading.
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| CN110221935A (en) * | 2019-06-11 | 2019-09-10 | 中国科学院长春光学精密机械与物理研究所 | FPGA based on LDO loads allocation problem inspection method |
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- 2019-11-14 CN CN201911112286.1A patent/CN110941510B/en active Active
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| US6044025A (en) * | 1999-02-04 | 2000-03-28 | Xilinx, Inc. | PROM with built-in JTAG capability for configuring FPGAs |
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