CN110941510A - FPGA (field programmable Gate array) online reloading circuit and method - Google Patents
FPGA (field programmable Gate array) online reloading circuit and method Download PDFInfo
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- CN110941510A CN110941510A CN201911112286.1A CN201911112286A CN110941510A CN 110941510 A CN110941510 A CN 110941510A CN 201911112286 A CN201911112286 A CN 201911112286A CN 110941510 A CN110941510 A CN 110941510A
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
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- G06F11/1415—Saving, restoring, recovering or retrying at system level
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Abstract
The invention belongs to the technical field of digital circuits, and provides an on-line reloading circuit and method of an FPGA. The method detects whether the FPGA is loaded successfully or not based on the heartbeat signal, when the FPGA is detected to be loaded unsuccessfully, the MCU starts an online reloading process and transmits a target file stored in an external FLASH thereof to the FPGA through a JTAG protocol realized by a GPIO (general purpose input/output) of the target file; the invention can detect whether the power-on loading of the FPGA is successful or not, and start the on-line reloading process when the power-on loading is failed, thereby realizing the on-line reloading of the FPGA, avoiding the unsuccessful loading of the FPGA and obviously improving the reliability of the product.
Description
Technical Field
The invention provides an FPGA (field programmable gate array) online reloading circuit and an FPGA online reloading method, belongs to the technical field of digital circuits, and is particularly suitable for the field of airborne computers with high reliability requirements.
Background
An FPGA of an SRAM (static random access memory) process belongs to a power-down volatile element, when a product is powered on, a target file stored in a PROM (programmable read-only memory) needs to be loaded into the FPGA, and after the loading is finished, the FPGA can finish specified work according to design requirements. However, in practical applications, the phenomenon of unsuccessful FPGA loading due to various reasons such as power supply jitter and PROM abnormality often occurs, which causes product function failure and further failure. The conventional reloading strategy is to restart the process of loading from the PROM by resetting a PROGRAM signal after the power-on loading fails, and belongs to a homogeneous reloading method. Aiming at the problems, the invention provides a heterogeneous reloading strategy, and after the power-on loading fails, the heterogeneous reloading strategy is reloaded through a JTAG interface, so that the probability of the successful reloading of the FPGA is improved, and the reliability of the product is obviously improved.
Disclosure of Invention
The purpose of the invention is as follows:
the FPGA online reloading circuit and the method can detect whether the power-on loading is successful or not and complete the online reloading of the FPGA when the power-on loading is failed.
The technical scheme is as follows:
the invention provides an FPGA (field programmable gate array) online reloading method.A target file is called from FLASH by an MCU (micro control unit) through a GPIO (general purpose input/output) to realize a JTAG protocol, so as to reload the FPGA.
Preferably, the FPGA online reloading method,
the method comprises the following steps:
step 1, the MCU detects whether the power-on loading of the FPGA is successful, and if the loading is unsuccessful, the MCU enters step 2;
step 2, the MCU configures the direction of GPIO according to JTAG signal definition;
and 3, reading the target file from the FLASH by the MCU, and transmitting the target file to the FPGA through the GPIO defined in the step 2 to finish reloading.
Preferably, in the method for reloading an FPGA online, the step 1 of detecting whether the FPGA power-on loading is successful specifically includes:
and the MCU acquires the heartbeat signal of the FPGA after the power-on loading of the FPGA is finished, if the heartbeat signal is normal, the power-on loading of the FPGA is successful, and if the heartbeat signal is abnormal, the power-on loading of the FPGA is failed.
Preferably, in the method for on-line reloading of the FPGA, 4 GPIO pins of the MCU are directly connected to 4 signal lines of the JTAG connector, and a default state of the 4 GPIO pins of the MCU is a high impedance;
in the step 2, the MCU configures the directions of 4 GPIOs according to JTAG signal definitions;
and after the step 3 is finished, the MCU configures the states of the 4 GPIOs into high impedance.
Preferably, in the method for on-line reloading of the FPGA, the FPGA resides in a heartbeat signal driving circuit, and after the power-on loading is completed, if the power-on loading is successful, a heartbeat signal is output by a heartbeat pin, wherein the heartbeat signal is a square wave with a specified frequency and a specified duty ratio; and if the power-on loading is not successful, generating no heartbeat signal.
The invention also provides an FPGA online reloading circuit, which comprises an MCU and a FLASH, wherein the online reloading object is the FPGA, GPIO pins of the MCU are connected with a JTAG interface of the FPGA, the MCU is connected with the FPGA through a heartbeat signal line, and the MCU is connected with the FLASH.
Preferably, in the FPGA online reloading circuit, a JTAG interface of the FPGA is linked with a JTAG connector, 4 GPIO pins of the MCU are directly connected with 4 signal lines of the JTAG connector, and a default state of the 4 GPIO pins of the MCU is a high impedance; when the device is off-line, the simulator is connected with the JTAG connector for loading;
preferably, in the FPGA online reloading circuit, the MCU detects whether the FPGA is successfully loaded through the heartbeat signal line, and if the FPGA is not successfully loaded through the heartbeat signal line, the MCU configures a GPIO direction according to the JTAG signal definition, calls the target file from the FLASH, and transmits the target file to the FPGA through the GPIO to complete the reloading.
Has the advantages that:
the invention provides an FPGA (field programmable gate array) online reloading circuit and an FPGA online reloading method, which can detect whether the FPGA is successfully loaded on power, and start an online reloading process when the power-on loading fails, so that the FPGA is reloaded on line, the FPGA is prevented from being unsuccessfully loaded, and the reliability of a product is obviously improved.
Drawings
The above advantages and description of embodiments of the invention will become apparent and readily appreciated when taken in conjunction with the following drawings, wherein:
FIG. 1 is a circuit diagram of an FPGA on-line reload of the present invention;
fig. 2 is a schematic diagram of an embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following detailed description and accompanying drawings.
FIG. 1 provides an FPGA online reloading circuit, which includes an MCU and a FLASH, and the object of online reloading is the FPGA;
optionally, a target file is stored in the FLASH;
optionally, offline loading is also supported by using a method of connecting the simulator with the JTAG connector;
optionally, 4 GPIO pins of the MCU are directly connected to 4 signal lines of the JTAG connector, and the default state of the 4 GPIO pins of the MCU is high impedance;
optionally, the MCU is connected with the FPGA through a heartbeat signal line;
optionally, a heartbeat signal driving circuit is reserved in the FPGA, and after power-on loading is completed, a heartbeat signal is output by a heartbeat pin, wherein the heartbeat signal is a square wave with a specified frequency and a specified duty ratio;
in order to apply the circuit shown in fig. 1, an FPGA online reloading method is provided, which includes:
detecting whether the FPGA is successfully electrified and loaded based on the heartbeat signal line;
when the FPGA is detected to be failed in power-on loading, starting an FPGA reloading process, configuring directions of 4 GPIOs according to JTAG signal definition, reading a target file from an external FLASH, transmitting the target file to the FPGA through a JTAG interface realized by the GPIOs, and configuring the 4 GPIOs into a high resistance;
optionally, the MCU acquires a heartbeat signal after the FPGA power-on loading is completed, if the heartbeat signal is normal, the FPGA power-on loading is successful, and if the heartbeat signal is abnormal, the FPGA power-on loading is failed;
fig. 2 provides a specific embodiment of the present invention, as shown in fig. 2:
XC4VLX25 FPGA is taken as an online loading object. XC4VLX25 is an FPGA of an SRAM process, belongs to a power-down volatile element, and therefore needs to be configured with a PROM for storing a binary target file, wherein the model of the PROM is XCF32P, and the format of the target file is MCS; the FPGA and the PROM are connected with a maintenance JTAG connector through a JTAG chain, and four signal lines of the JTAG are simultaneously connected with four GPIOs of the MCU; the MCU is configured with an external FLASH, and the FLASH is stored with an object code in an XSVF format, wherein the object code is obtained by converting the object code in the BIT format through an iMPACT tool. After the product is powered on, the XC4VLX25 FPGA loads a binary object code from the PROM through a parallel bus [ D7D 0], and the following two conditions exist: (i) the heartbeat signal is normal. After the FPGA is electrified and loaded, a heartbeat pin of the FPGA outputs a heartbeat signal with specified frequency and duty ratio, and the MCU captures the heartbeat signal. The heartbeat signal normally indicates that the FPGA is successfully electrified and loaded, and the MCU does not need to execute an online reloading process; (ii) the heartbeat signal is abnormal. After the FPGA is electrified and loaded, a heartbeat pin of the FPGA outputs a heartbeat signal with specified frequency and duty ratio, and the MCU captures the heartbeat signal. The heartbeat signal abnormity indicates that the FPGA fails to be electrified and loaded, and the MCU needs to execute an online reloading program: (1) configuring directions of four GPIOs according to JTAG signal definition; (2) reading a target code from FLASH; (3) sending the target file to the FPGA through a JTAG protocol; (4) the four GPIOs are configured to be high impedance.
When the FPGA finishes power-on loading and detects that the heartbeat signal is abnormal, after the MCU executes an online loading program, the MCU captures the heartbeat signal again, and if the heartbeat signal is normal, the FPGA succeeds in online reloading; if the heartbeat signal is still abnormal, the FPGA fails to be reloaded on line, and the fault condition needs to be reported to the upper computer at the moment.
The existing common reloading strategy is to restart the process of loading from the PROM by resetting a PROGRAM signal after the power-on loading fails, which belongs to an isomorphic reloading method, and because the power-on loading process fails, the probability of successful reloading is smaller; the method reloads through the JTAG interface instead of the parallel interface after the power-on loading fails, belongs to a heterogeneous reloading method, and has higher probability of successful reloading.
Claims (8)
1. An FPGA online reloading method is characterized in that an MCU realizes a JTAG protocol through GPIO, calls a target file from FLASH and reloads the FPGA.
2. The FPGA online reloading method as claimed in claim 1,
the method comprises the following steps:
step 1, the MCU detects whether the power-on loading of the FPGA is successful, and if the loading is unsuccessful, the MCU enters step 2;
step 2, the MCU configures the direction of GPIO according to JTAG signal definition;
and 3, reading the target file from the FLASH by the MCU, and transmitting the target file to the FPGA through the GPIO defined in the step 2 to finish reloading.
3. The method for on-line reloading of an FPGA according to claim 2, wherein said step 1, detecting whether the FPGA power-on loading is successful specifically comprises:
and the MCU acquires the heartbeat signal of the FPGA after the power-on loading of the FPGA is finished, if the heartbeat signal is normal, the power-on loading of the FPGA is successful, and if the heartbeat signal is abnormal, the power-on loading of the FPGA is failed.
4. The FPGA online reloading method as claimed in claim 2, wherein 4 GPIO pins of the MCU are directly connected with 4 signal lines of the JTAG connector, and the default state of the 4 GPIO pins of the MCU is high impedance;
in the step 2, the MCU configures the directions of 4 GPIOs according to JTAG signal definitions;
and after the step 3 is finished, the MCU configures the states of the 4 GPIOs into high impedance.
5. The FPGA online reloading method as claimed in claim 3, wherein a heartbeat signal driving circuit resides in the FPGA, and after the power-on loading is completed, if the power-on loading is successful, a heartbeat signal is output by a heartbeat pin, wherein the heartbeat signal is a square wave with a specified frequency and a specified duty ratio; and if the power-on loading is not successful, generating no heartbeat signal.
6. The FPGA online reloading circuit is characterized by comprising an MCU and a FLASH, wherein the FPGA is used as an online reloading object, GPIO pins of the MCU are connected with a JTAG interface of the FPGA, the MCU is connected with the FPGA through a heartbeat signal line, and the MCU is connected with the FLASH.
7. The FPGA online reloading circuit of claim 1, wherein a JTAG interface of the FPGA is linked with a JTAG connector, 4 GPIO pins of the MCU are directly connected with 4 signal lines of the JTAG connector, and the default state of the 4 GPIO of the MCU is high resistance; when off-line, the loading is performed by connecting the JTAG connector with the emulator.
8. The FPGA online reloading circuit of claim 6, wherein the MCU detects whether the FPGA is loaded successfully through a heartbeat signal line, if the FPGA is not loaded successfully after being powered on, the MCU configures the direction of the GPIO according to the JTAG signal definition, calls a target file from the FLASH and transmits the target file to the FPGA through the GPIO to complete the reloading.
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| CN107015880A (en) * | 2016-01-28 | 2017-08-04 | 京微雅格（北京）科技有限公司 | A kind of FPGA circuitry and its configuration file processing method |
| CN209265384U (en) * | 2018-09-29 | 2019-08-16 | 江苏金晓电子信息股份有限公司 | A kind of upgrading power-down protection circuit system for urban traffic guidance terminal |
| CN110221935A (en) * | 2019-06-11 | 2019-09-10 | 中国科学院长春光学精密机械与物理研究所 | FPGA based on LDO loads allocation problem inspection method |
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2019
- 2019-11-14 CN CN201911112286.1A patent/CN110941510B/en active Active
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| US6044025A (en) * | 1999-02-04 | 2000-03-28 | Xilinx, Inc. | PROM with built-in JTAG capability for configuring FPGAs |
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