CN110221935A - FPGA based on LDO loads allocation problem inspection method - Google Patents

FPGA based on LDO loads allocation problem inspection method Download PDF

Info

Publication number
CN110221935A
CN110221935A CN201910500327.8A CN201910500327A CN110221935A CN 110221935 A CN110221935 A CN 110221935A CN 201910500327 A CN201910500327 A CN 201910500327A CN 110221935 A CN110221935 A CN 110221935A
Authority
CN
China
Prior art keywords
fpga
ldo
power supply
flash
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910500327.8A
Other languages
Chinese (zh)
Other versions
CN110221935B (en
Inventor
余达
刘金国
韩诚山
姜肖楠
孔德柱
柴方茂
李嘉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changchun Institute of Optics Fine Mechanics and Physics of CAS
Original Assignee
Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changchun Institute of Optics Fine Mechanics and Physics of CAS filed Critical Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority to CN201910500327.8A priority Critical patent/CN110221935B/en
Publication of CN110221935A publication Critical patent/CN110221935A/en
Application granted granted Critical
Publication of CN110221935B publication Critical patent/CN110221935B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0733—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a data processing system embedded in an image processing device, e.g. printer, facsimile, scanner
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H04N17/002—Diagnosis, testing or measuring for television systems or their details for television cameras

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • General Health & Medical Sciences (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Power Sources (AREA)
  • Stored Programmes (AREA)

Abstract

FPGA based on LDO loads allocation problem inspection method, it is related to a kind of FPGA load allocation problem inspection method based on LDO, solve the problems, such as FPGA configuration load failure caused by the latent logical and DCDC output voltage ascent stage starting configuration in existing imaging applications, including the obstructed problem investigation of JTAG connection；Flash data program is unsuccessfully checked, flash loads unsuccessfully investigation and the power supply capacity inspection based on LDO power supply etc., the present invention is configuration load failure caused by the latent logical and DCDC output voltage ascent stage starting configuration avoided in imaging applications, it proposes first to power on the LDO power supply mode powered on after kernel using the IO of FPGA, and the selection of the power supply capacity of LDO is powered by loading current to FPGA and filter capacitor, guarantee that the rise time of FPGA kernel power supply meets configuration requirement；Aiming at the problem that different application mode is likely to occur, different inspection methods are devised.The method of the present invention can quick positioning question, reduce problem investigation cost；The mistake of design may be found in advance, reduce a possibility that doing over again.

Description

FPGA based on LDO loads allocation problem inspection method
Technical field
The present invention relates to a kind of, and the FPGA based on LDO loads allocation problem inspection method, and in particular to one kind is based on CMOS The FPGA of the LDO of imaging applications loads allocation problem inspection method.
Background technique
Imaging FPGA based on cmos image sensor is applied, and the configuration data inside FPGA can be by JTAG mouthfuls directly It downloads in FPGA.Due to by JTAG mouthfuls of burned configuration datas, having lower electric volatibility, can also by JTAG mouthfuls first under It is downloaded in the flash of non-lower electric volatibility and carries out powering on load configuration again；Or cd-rom recorder can be first passed through and be first burnt to prom It carries out powering on load configuration again in memory.In commonly used, imaging controller is first powered on, and is then controlled centered on FPGA Imaging unit power-up, and generate control signal.Since imaging controller is first powered on, controlling the latent logical of signal will lead to FPGA's I/O port voltage raising in the case where its LDO that powers is not exported is configuring if the latent pressure that is powered has reached configured threshold voltage There is the IO voltage of FPGA the risk of pit occur in the process；For the surge current for reducing DCDC module input bus, usual DCDC The voltage increase rate of output and the time of transient response are longer, if starting in the uphill process of DCDC module output voltage FPGA configuration then FPGA configuration may occurs and add since the pressure drop on transmitting conducting wire is excessive or the power supply capacity of DCDC is insufficient Carry failure.
Summary of the invention
Caused by the present invention is the latent logical and DCDC output voltage ascent stage starting configuration solved in existing imaging applications The problem of FPGA configuration load failure, provides a kind of FPGA load allocation problem inspection method based on LDO.
FPGA based on LDO loads allocation problem inspection method, and this method is realized by following steps: not including JTAG connection Logical problem investigation method, the investigation method of the burned journey failure of flash data and the investigation method of flash load failure；
When JTAG and flash can be connected, the burned procedure failure of flash data specifically checks method are as follows:
Step a, set minimum for the downloading rate of JTAG downloader, can judgement burned program success；If not, holding Row step b；If so, executing step f；
Step b, the burned successful downloader of program is replaced, judging whether can burned program success；If not, executing step C, if so, executing step f；
Step c, the minimum and highest of FPGA kernel power supply, FPGA IO power supply and FPGA accessory power supply is checked Within the specified scope whether voltage value；If not, executing step d；If so, executing step f；
Step d, disconnect CCLK clock or CS pin, judgement can the success of burned program, if not, execute step e, If so, executing step f；
Step e, the waveform and relative phase relation for measuring each signal of JTAG, judge whether topological structure is reasonable, if so, Replace flash chip；If not, carrying out the optimization of topological structure；
Step f, terminate detection；
When by the burned program of jtag interface energy into FPGA and flash, flash load failure loads flash and loses The investigation method lost are as follows:
Step A1, on checking whether the downloading mode setting of flash is corresponding with hardware setting, if so, executing B1；If It is no, execute step A2；
Step A2, it is downloaded the adjustment of mode, and judges whether to load successfully, if not, executing step B1；If It is to execute step G1；
Step B1, when multi-disc flash provides configuration data to a piece of FPGA, m sub- configuration datas of segmentation are checked Whether programming sequence is correct, if so, executing step C1；If not, executing step B2；
Step B2, programming sequence adjusts, and judges whether to load successfully, if not, step C1 is executed, if so, executing Step G1；
Step C1, CCLK clock frequency is set as minimum, judgement can configuration successful, if not, execute step D1, such as Fruit is to execute step G1；
Step D1, check whether the full link topology of FPGA configuration coherent signal is reasonable, if so, executing step E1, if not, executing step D2；
Step D2, topologies adjusting, and judge whether to load successfully, if not, executing step E1；If so, executing Step G1；
Step E1, based on the power supply capacity inspection of LDO power supply, if meet application requirement；If so, step F1 is executed, If not, executing step E2；
Step E2, LDO power supply capacity adjusts, and judges whether to load successfully, if not, step F1 is executed, if so, holding Row step G1；
Step F1, it tests each configuration signal waveform and whether phase relation meets the requirements, if not, design correcting, if It is to update configuration chip；
Step G1, terminate detection.
Beneficial effects of the present invention:
1, the FPGA load allocation problem inspection method of the present invention based on based on LDO can quick positioning question, subtract The cost of minor issue investigation；
2, a possibility that inspection method of the present invention can find the mistake of design in advance, and reduction is done over again.
3, inspection method of the present invention can guarantee that FPGA reliablely and stablely loads configuration.
Detailed description of the invention
Fig. 1 is FPGA imaging configuration loading system in the present invention；Wherein, Fig. 1 a is that configuration is imaged in the FPGA based on flash Loading system block diagram, Fig. 1 b are the FPGA imaging configuration loading system block diagram based on PROM；
Fig. 2 is the power supply the principle figure of FPGA imaging configuration loading system；
Fig. 3 is the generation process schematic of FPGA supply voltage；Fig. 3 a be each LDO in input power uphill process simultaneously The enabled schematic diagram exported, Fig. 3 b are that each LDO enables output principle figure simultaneously in input power uphill process under latent logical state, Fig. 3 c is each LDO in the enabled output principle figure of input power timesharing；
Fig. 4 is that the obstructed problem of JTAG connection checks sequential flowchart；
Fig. 5 is that flash data program unsuccessfully checks sequential flowchart；
Fig. 6 is that sequential flowchart is unsuccessfully checked in flash load；
Fig. 7 is the power supply capacity checks sequence flow chart based on LDO power supply；
Fig. 8 is the power supply capacity check process figure of LDO and LDO power supply；
Fig. 9 is the connection type schematic diagram of LDO delay.
Specific embodiment
Specific embodiment one illustrates present embodiment in conjunction with Fig. 1 to Fig. 9, the FPGA load allocation problem inspection based on LDO Checking method, including FPGA imaging configuration loading system, in conjunction with Fig. 1, including computer, JTAG downloader, FPGA plate, CMOS focal plane plate And imaging controller, comprise in addition prom plate or flash plate.On FPGA plate comprising FPGA and with prom flash plate phase FPGA connector 2 even.It comprising the FPGA connector 1 being connected with FPGA plate on prom plate, while including n prom；Flash plate The upper FPGA connector 1 comprising being connected with FPGA plate, while including n flash；Signal on the FPGA connector 1 of the two is simultaneous Hold.In conjunction with Fig. 1 a, the FPGA imaging configuration loading system based on flash can be downloaded by daisy chain structure through computer to JTAG The configuration data of FPGA is directly downloaded in FPGA by device to flash plate to FPGA plate, can also be downloaded in n flash； The upper configuration load of FPGA is carried out by reading configuration data from n flash.In conjunction with Fig. 1 b, based on the FPGA of prom at As configuration loading system, can by daisy chain structure through computer to JTAG downloader to prom plate to FPGA plate by the configuration of FPGA Data are directly downloaded in FPGA, and the configuration data in n prom needs burned using cd-rom recorder in advance；The upper configuration of FPGA Load is carried out by reading configuration data from n prom.
After FPGA configuration loads successfully, the related command of imaging controller is received, the CMOS on CMOS focal plane plate is schemed As sensor output control sequential signal, while receiving the image data of cmos image sensor output.
In conjunction with Fig. 2, the power supply mode of FPGA imaging configuration loading system, externally input imaging power supply is respectively through in FPGA Core power supply LDO, FPGAIO power supply LDO, FPGA accessory power supply power supply LDO gives FPGA to power, and CMOS focal plane plate powers LDO to CMOS Interlock circuit power supply on focal plane plate.
Embodiment is described with reference to Fig. 3, in present embodiment, in conjunction with Fig. 3 a, and in figure, Vcco_maxIt powers for the IO of FPGA The maximum value that voltage reaches, Vin_maxFor the maximum value of input voltage, VccintFor the kernel supply voltage of FPGA, Vccint_maxFor The maximum value that the kernel supply voltage of FPGA reaches, IccFor VinOperating current, when each LDO is in input power uphill process Reach threshold voltage V simultaneouslyin_th, output is enabled, biggish peak point current can be generated in input terminal, the IO power supply of FPGA at this time LDO output voltage VccoBy the power supply capacity of LDO itself, the supply voltage V of inputDCDC, LDO input power cable resistance value R and The pressure difference V of LDOLDO_diffModulation, all may cause falling for output voltage.
Vcco=VDCDC-ICC×R-VLDO_diff
In conjunction with Fig. 3 b, each LDO enabled output simultaneously in input power uphill process under latent logical state, when owning for FPGA When supply voltage has reached configured threshold level, the LDO that the IO of FPGA powers at this time is since pressure difference deficiency can't export electricity Pressure, and kernel supply voltage has reached threshold level value, then easily there is pit in the IO voltage of FPGA, leads to configuration failure.
In conjunction with Fig. 3 c, each LDO reaches maximum in input power in the enabled output of input power timesharing, the kernel power supply of FPGA Value Vin_maxAfterwards enable output, since the pressure difference of LDO becomes larger, the power consumption that may add up during to capacitor charging become larger and There is the current limliting Thermal protection of LDO, the rise time of output voltage is caused to lengthen.Temperature of the electric current i of LDO output by LDO itself tLDO, maximum output current Imax, the minimum output current of Thermal protection, Thermal protection export electric current Imin, load capacitance C, input power supply Power supply Vin, LDO thermal resistance Rθ, LDO the modulation such as current limiting factor k.It is indicated with following formula are as follows:
FPGA described in present embodiment based on LDO loads allocation problem inspection method, including JTAG connection is not corresponded Investigation method is inscribed, in conjunction with Fig. 4, detailed process are as follows:
(1) can setting minimum see for the downloading rate of JTAG successful connection；
(2) downloader that replacement can be connected on other wiring board sees whether can be connected to；
(3) the minimum and ceiling voltage of all power supplies (FPGA kernel, FPGAIO and FPGA accessory power supply) is checked Within the specified scope whether value；
(4) be directed to the application of flash plate, measure between JTAG downloader and flash_1 each JTAG signal (TDI, TCK, TMS and TDO) connection, see with the presence or absence of open circuit；
(5) flash plate is changed to prom plate, for prom plate application, sees whether JTAG downloader is connected to FPGA, if It cannot be connected to, measure the connection feelings of each JTAG signal (TDI, TCK, TMS and TDO) between JTAG downloader and FPGA pin Condition is seen with the presence or absence of open circuit, the removing of further progress link.It is breaking if it does not exist, then replace fpga chip；Break if it exists Road carries out breaking reparation.
Embodiment is described with reference to Fig.5, which works as JTAG and flash, to connect, the burned program of flash data (program) Failure, specific investigation are
(1) set minimum for the downloading rate of JTAG, can see program success；
(2) replacement on other wiring board the successful downloader of progarm see whether can program success；
(3) the minimum and ceiling voltage of all power supplies (FPGA kernel, FPGAIO and FPGA accessory power supply) is checked Within the specified scope whether value；
(4) disconnect CCLK's or CS pin then attempt can program success, it is right after FPGA is behaved to avoid The interference of jtag circuit；
(5) waveform and relative phase relation for measuring each signal of JTAG, carry out topological structure reasonableness check.Measurement TDI, The signal waveform and relative phase relation of TMS, TCK and TDO.From the downloading wire being connected with PC to FPGA and flash；In addition also Need to check whether the access point of downloading wire is correct, if can exist whether there is also what branch circuit on this JTAG link The reflection problems of signal；
Embodiment is described with reference to Fig.6, by the way that in JTAG mouthfuls of energy program to FPGA and flash, flash load is lost Lose problem investigation method specifically:
(1) on checking whether the downloading mode setting of flash is corresponding with hardware setting.Principal and subordinate and string and whether with M2-M0, Downloading mode (whether choosing parallel mode) in cs_b and RDWR_B correspondence, in flash downloading process.This problem can It can lead to data recording success, but load unsuccessful.
(2) it provides configuration data to a piece of FPGA for multi-disc flash, checks the m of segmentation (m is the positive integer greater than 0) Whether the programming sequence of sub- configuration data is correct.First sub- configuration data should correspond to 0 number device in programming link, finally Sub- configuration data should correspond to the m-1 number device in programming link.
(3) CCLK clock frequency is set as minimum, can see configuration successful.
(4) check whether the full link topology of FPGA configuration coherent signal is reasonable.From FPGA to flash, in addition also Need to check whether there is also what branch circuits on this configuration link, if there can be the reflection problems of signal；
(5) based on the power supply capacity inspection of LDO power supply, if meet application requirement.Rising of the supply voltage from 0-90% Monotonicity in time, uphill process.
(6) it tests each configuration signal waveform and whether phase relation meets the requirements.Check whether carried out impedance control with Matching, if carried out equal length treatment.
The detailed process for the power supply capacity inspection based on LDO power supply that embodiment is described with reference to Fig.7, are as follows:
(1) level change in the monotonicity and configuration process in supply voltage uphill process is checked.
It first checks in LDO output voltage uphill process being monotone increasing, if it is monotone increasing, then executes (2)；If going out Showed falling for voltage, then whether the maximum output current for first checking for LDO meets configuration phase maximum current, if not satisfied, Replacement output electric current is greater than the LDO of the maximum current of configuration phase；If satisfied, then checking the maximum power supply electricity of LDO input power Whether stream meets FPGA configuration phase maximum current when substep is powered on.If the maximum supply current of LDO input power is unsatisfactory for point FPGA configuration phase maximum current when step power-up, replacement supply current are greater than the maximum current of FPGA configuration phase when substep is powered on Input power；If satisfied, then checking that pressure drop is excessive on LDO input power cable, causes output voltage to fall.If LDO is defeated Entering feed cable causes output voltage to fall, then the small cable of resistance value is not fallen with the output voltage for guaranteeing LDO, otherwise It checks that the configuration of FPGA is enabled whether to occur before input power reaches maximum value.Occur inputting if the configuration of FPGA is enabled Before power supply reaches maximum value, then checks and check that latent admittance causes the IO of FPGA with the presence or absence of voltage.If the IO of FPGA there are voltage, Then start the enabled output of LDO after input supply voltage reaches maximum value, IO is first powered on, and then accessory power supply powers on (can also be with At first powered on IO mono-), core power finally powers on；If it does not exist, only start LDO after input supply voltage reaches maximum value Enabled output, each power supply substep power on.
(2) check whether the rise time of supply voltage from 0-90% are too long.
Supply voltage requires from the setup time that the rise time of 0-90% meets FPGA and (is no more than 50ms), then does not need Extra process；If not satisfied, then checking whether the load capacitance amount of LDO is excessive.If the load capacitance amount of LDO is excessive, dismantle Otherwise partition capacitance checks it is to start the enabled output of LDO after input supply voltage reaches maximum value to reduce capacitance, each to supply Power supply substep powers on.If powering on step by step, the bigger LDO of Thermal protection electric current is replaced, is otherwise reached in input supply voltage Start the enabled output of LDO after to maximum value, each power supply substep powers on.
In present embodiment that embodiment is described with reference to Fig.8, FPGA kernel power supply LDO, FPGAIO power supply LDO, Power supply capacity inspection combination Fig. 8 of FPGA accessory power supply power supply LDO and DCDC module (power supply of LDO), wherein equivalent electricity Capacitance is all capacitances of connection, and equivalent resistance is that output voltage is in peak load current acquisition.By relay k11 and K12 accesses the response of capacitor and ohmic load to simulate respectively.
In present embodiment that embodiment is described with reference to Fig.9, FPGA kernel power supply LDO, FPGAIO power supply LDO With the delayed startup of FPGA accessory power supply power supply LDO, using sealing in resistance between EN pin and input power pin, and in EN The indirect capacitor of pin and ground pin carries out the delay control of upper electricity output by the resistance value of adjusting resistance and the amount of capacity of capacitor System, while requiring the rise time of output voltage lower than 50ms.
In present embodiment, the FPGA uses the XC5VFX100T-FFG1136 of Xilinx company；Flash and prom points Not Cai Yong Xilinx company XCF16P and XQR17V16；Imaging controller uses the DSP TMS320 6701 of TI company；CMOS Imaging sensor uses the TDI cmos image sensor of Chang Guangchen core company；JTAG downloader uses the downloading of Xilinx company Device；Connector uses the high-speed high-density connector of airborn company.

Claims (5)

1. the FPGA based on LDO loads allocation problem inspection method, it is characterized in that: including that JTAG connects obstructed problem investigation side The investigation method of the burned journey failure of method, flash data and the investigation method of flash load failure；
When JTAG and flash can be connected, the burned procedure failure of flash data specifically checks method are as follows:
Step a, set minimum for the downloading rate of JTAG downloader, can judgement burned program success；If not, executing step Rapid b；If so, executing step f；
Step b, the burned successful downloader of program is replaced, judging whether can burned program success；If not, executing step c, such as Fruit is to execute step f；
Step c, the minimum and ceiling voltage of FPGA kernel power supply, FPGA IO power supply and FPGA accessory power supply is checked Within the specified scope whether value；If not, executing step d；If so, executing step f；
Step d, disconnect CCLK clock or CS pin, judgement can the success of burned program, if not, execute step e, if It is to execute step f；
Step e, the waveform and relative phase relation for measuring each signal of JTAG, judge whether topological structure is reasonable, if so, replacement Flash chip；If not, carrying out the optimization of topological structure；
Step f, terminate detection；
When by the burned program of jtag interface energy into FPGA and flash, flash load failure, to flash load failure Investigation method are as follows:
Step A1, on checking whether the downloading mode setting of flash is corresponding with hardware setting, if so, executing B1；If not, Execute step A2；
Step A2, it is downloaded the adjustment of mode, and judges whether to load successfully, if not, executing step B1；If so, holding Row step G1；
Step B1, when multi-disc flash provides configuration data to a piece of FPGA, the programming of m sub- configuration datas of segmentation is checked Whether sequence is correct, if so, executing step C1；If not, executing step B2；
Step B2, programming sequence adjusts, and judges whether to load successfully, if not, step C1 is executed, if so, executing step G1；
Step C1, CCLK clock frequency is set as minimum, judgement can configuration successful, if not, execute step D1, if It is to execute step G1；
Step D1, check whether the full link topology of FPGA configuration coherent signal is reasonable, if so, executing step E1, such as Fruit is no, executes step D2；
Step D2, topologies adjusting, and judge whether to load successfully, if not, executing step E1；If so, executing step G1；
Step E1, based on the power supply capacity inspection of LDO power supply, if meet application requirement；If so, step F1 is executed, if It is no, execute step E2；
Step E2, LDO power supply capacity adjusts, and judges whether to load successfully, if not, step F1 is executed, if so, executing step Rapid G1；
Step F1, it tests each configuration signal waveform and whether phase relation meets the requirements, if not, design correcting, if so, more New configuration chip；
Step G1, terminate detection.
2. the FPGA according to claim 1 based on LDO loads allocation problem inspection method, it is characterised in that: described JTAG connects obstructed investigation method, comprising the following steps:
Step A, when setting minimum for the downloading rate of JTAG downloader, judge whether successful connection, if not, executing step B, if so, executing step G；
Step B, using the JTAG downloader in the downloader replacement step A that can be connected on other wiring board, judge whether energy Connection；If not, step C is executed, if so, executing step G；
Step C, the minimum and ceiling voltage of FPGA kernel power supply, FPGA IO power supply and FPGA accessory power supply is checked Within the specified scope whether value；If not, step D is executed, if so, executing step G；
Step D, the connection of each JTAG signal between the flash_1 in JTAG downloader and flash plate is measured, judgement is It is no to there is open circuit；If not, executing step E；If so, executing step G；
Step E, flash plate is changed to prom plate, judges whether JTAG downloader can be connected to FPGA, if not, executing step Rapid F；If so, executing step G；
Step F, the connection of each JTAG signal between JTAG downloader and FPGA pin is measured with the presence or absence of open circuit, if so, Then replace fpga chip；If not, reducing connectivity reparation；
Step G, terminate detection.
3. the FPGA according to claim 1 based on LDO loads allocation problem inspection method, it is characterised in that: step E1 In, the power supply capacity inspection based on LDO power supply method particularly includes:
Step 1: check whether in LDO output voltage uphill process be monotone increasing, if it is not, then step 2 is executed, if It is to execute step 7；
Step 2: check whether the maximum output current of LDO meets the maximum current of configuration phase, if so, step 3 is executed, If not, replacement output electric current is greater than the LDO of the maximum current of configuration phase；
Step 3: checking whether the maximum supply current of LDO input power meets the maximum of FPGA configuration phase when substep is powered on Electric current；If so, executing step 4；If not, replacement supply current is greater than the maximum electricity of FPGA configuration phase when substep is powered on The input power of stream；
Step 4: judging whether to cause output voltage to fall since pressure drop is excessive on LDO input power cable, if it is, resistance It is worth small cable and is not fallen with the output voltage for guaranteeing LDO, if not, executes step 5；
Whether occur before input power reaches maximum value Step 5: checking that the configuration of FPGA is enabled, if so, executing step Six；If not, not needing extra process；
Step 6: checking that latent admittance causes the IO of FPGA to whether there is voltage, if so, after input supply voltage reaches maximum value Start the enabled output of IO power supply LDO, IO is first powered on, and then FPGA accessory power supply powers on, FPGA core power finally powers on；If It is no, start the enabled output of LDO after input supply voltage reaches maximum value, each power supply substep powers on；
Step 7: checking whether the rise time of LDO output voltage from 0-90% are too long, if so, executing step 8；If It is no, then it does not need to handle；
Step 8: check whether the load capacitance amount of LDO is excessive, if it is, disengaging section capacitor to be to reduce capacitance, if It is no, execute step 9；
Start the enabled output of LDO after input supply voltage reaches maximum value Step 9: then checking whether, each power supply substep It powers on；If it is, the LDO that replacement Thermal protection electric current is big；If not, starting LDO after input supply voltage reaches maximum value Enabled output, each power supply substep power on.
4. the FPGA according to claim 3 based on LDO loads allocation problem inspection method, it is characterised in that: step 7 In, the rise time of LDO output voltage from 0-90% is too long to refer to that the time is more than or equal to 50ms.
5. the FPGA according to claim 1 based on LDO loads allocation problem inspection method, it is characterised in that: described The delayed startup setting of FPGA kernel power supply LDO, FPGAIO power supply LDO and FPGA accessory power supply power supply LDO are as follows: using in EN pipe Resistance R is sealed between foot and input power pin, and in the indirect capacitor C of EN pin and ground pin, by the resistance for adjusting resistance R The capacity of value and capacitor C carry out the delays time to control of electricity output, and the rise time of output LDO supply voltage is required to be less than 50ms。
CN201910500327.8A 2019-06-11 2019-06-11 FPGA loading configuration problem checking method based on LDO Active CN110221935B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910500327.8A CN110221935B (en) 2019-06-11 2019-06-11 FPGA loading configuration problem checking method based on LDO

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910500327.8A CN110221935B (en) 2019-06-11 2019-06-11 FPGA loading configuration problem checking method based on LDO

Publications (2)

Publication Number Publication Date
CN110221935A true CN110221935A (en) 2019-09-10
CN110221935B CN110221935B (en) 2021-04-02

Family

ID=67816298

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910500327.8A Active CN110221935B (en) 2019-06-11 2019-06-11 FPGA loading configuration problem checking method based on LDO

Country Status (1)

Country Link
CN (1) CN110221935B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110941510A (en) * 2019-11-14 2020-03-31 中国航空工业集团公司西安航空计算技术研究所 FPGA (field programmable Gate array) online reloading circuit and method
CN111443652A (en) * 2020-03-24 2020-07-24 深圳市紫光同创电子有限公司 Power supply structure of CP L D logic unit array
CN111491161A (en) * 2020-04-27 2020-08-04 中国科学院长春光学精密机械与物理研究所 Debugging method of imaging system
CN112256115A (en) * 2020-09-21 2021-01-22 北京比特大陆科技有限公司 Power supply circuit, chip and electronic equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102521065A (en) * 2011-12-30 2012-06-27 四川九洲电器集团有限责任公司 Method for dynamic loading of configuration file through FPGA (field programmable gate array)
US8255754B2 (en) * 2007-05-15 2012-08-28 Texas Instruments Incorporated Range extension and noise mitigation for wireless communication links utilizing a CRC based single and multiple bit error correction mechanism
JP2014052781A (en) * 2012-09-06 2014-03-20 Fujitsu Telecom Networks Ltd Fpga monitoring control circuit
CN106292816A (en) * 2015-06-11 2017-01-04 京微雅格（北京）科技有限公司 A kind of LDO circuit and method of supplying power to, fpga chip
CN107967041A (en) * 2017-12-05 2018-04-27 中国科学院长春光学精密机械与物理研究所 A kind of power on configuration control method of more FPGA

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8255754B2 (en) * 2007-05-15 2012-08-28 Texas Instruments Incorporated Range extension and noise mitigation for wireless communication links utilizing a CRC based single and multiple bit error correction mechanism
CN102521065A (en) * 2011-12-30 2012-06-27 四川九洲电器集团有限责任公司 Method for dynamic loading of configuration file through FPGA (field programmable gate array)
JP2014052781A (en) * 2012-09-06 2014-03-20 Fujitsu Telecom Networks Ltd Fpga monitoring control circuit
CN106292816A (en) * 2015-06-11 2017-01-04 京微雅格（北京）科技有限公司 A kind of LDO circuit and method of supplying power to, fpga chip
CN107967041A (en) * 2017-12-05 2018-04-27 中国科学院长春光学精密机械与物理研究所 A kind of power on configuration control method of more FPGA

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
RUI JIA, FEI WANG, RUI CHEN, XIN-GANG WANG, HAI-GA: "《JTAG-Based Bitstream Compression for FPGA Configuration》", 《 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY》 *
候轶宸: "《关于FPGA 加载中的某种异常问题的解决方案》", 《航空计算技术》 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110941510A (en) * 2019-11-14 2020-03-31 中国航空工业集团公司西安航空计算技术研究所 FPGA (field programmable Gate array) online reloading circuit and method
CN110941510B (en) * 2019-11-14 2023-05-05 中国航空工业集团公司西安航空计算技术研究所 Online reloading circuit and method for FPGA
CN111443652A (en) * 2020-03-24 2020-07-24 深圳市紫光同创电子有限公司 Power supply structure of CP L D logic unit array
CN111443652B (en) * 2020-03-24 2021-06-18 深圳市紫光同创电子有限公司 Power supply structure of CPLD (complex programmable logic device) logic unit array
CN111491161A (en) * 2020-04-27 2020-08-04 中国科学院长春光学精密机械与物理研究所 Debugging method of imaging system
CN111491161B (en) * 2020-04-27 2021-03-16 中国科学院长春光学精密机械与物理研究所 Debugging method of imaging system
CN112256115A (en) * 2020-09-21 2021-01-22 北京比特大陆科技有限公司 Power supply circuit, chip and electronic equipment

Also Published As

Publication number Publication date
CN110221935B (en) 2021-04-02

Similar Documents

Publication Publication Date Title
CN110221935A (en) FPGA based on LDO loads allocation problem inspection method
CN101165354B (en) Fan rotation speed automatic control circuit
CN103149526B (en) PCBA board test macro and method
WO2001073929A2 (en) Apparatus for reducing power supply noise in an integrated circuit
CN106598639B (en) Logic chip upgrading method and upgrading system
WO2019113732A1 (en) Electronic device and charging control method
CN101604244B (en) Device and method for realizing that FPGA can be used when being electrified and remote upgrade of FPGA
US9123442B2 (en) Testing device
US20130181737A1 (en) Test system and test method for pcba
CN104881312B (en) The method and circuit of a kind of FPGA logical code iteration upgrading
CN106707143A (en) Chip internal logic verify system and method
CN112445739A (en) Circuit and method for supporting non-inductive upgrading of BIOS
CN101084444B (en) Pin electronics with high voltage functionality
JP2830786B2 (en) Hot-swap circuit
CN206601695U (en) A kind of burning device for detecting and indicating objective chip state
CN109933179A (en) A kind of server intelligence start-up control method, device and equipment
CN101930392B (en) Device for testing mobile hard disk
JP3699729B2 (en) I / O device for hot-swapping
CN113419982A (en) System and method for automatically matching downlink equipment by timer
CN110196781A (en) Allocation problem inspection method is loaded based on a FPGA for load
CN104871020A (en) An electronic load module and a method and a system therefor
KR101452959B1 (en) Mount-type test equipment and method thereof
US9158319B2 (en) Closed-loop adaptive voltage scaling for integrated circuits
CN111078476A (en) Network card drive firmware stability test method, system, terminal and storage medium
CN103969491A (en) Device and method for detecting voltage of processor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant