CN104572331B - The monitoring module enabled with power monitoring and delayed - Google Patents
The monitoring module enabled with power monitoring and delayed Download PDFInfo
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- CN104572331B CN104572331B CN201510009532.6A CN201510009532A CN104572331B CN 104572331 B CN104572331 B CN 104572331B CN 201510009532 A CN201510009532 A CN 201510009532A CN 104572331 B CN104572331 B CN 104572331B
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Abstract
It is a kind of that the monitoring module that there is power monitoring and delayed to enable in " feeding dog " cycle can be adjusted according to the startup time of operating system.It enables control circuit between module input and module output end provided with electric source monitoring circuit and delayed, wherein, electric source monitoring circuit is mainly power monitoring chip, and it is mainly programming device that delayed, which enables control circuit,.Module input is system power supply signal acquisition terminal；The end of module output end one is connected to programming device, and the other end is connected to CPU, network interface card or other system application modules Enable Pin respectively.The design of the present invention realizes the house dog with a variety of functions using power monitoring chip and programming device, can highly desirable reduce procedural problem and the problem of watchdog chip defect itself may be brought.And realize simple and full-featured.It is easy to apply in embedded hardware system.
Description
Technical field
The present invention relates to embedded system hardware design.Particularly a kind of house dog with power monitoring and delayed
Hardware design.
Background technology
Generally, in the microcomputer system being made up of single-chip microcomputer, due to single-chip microcomputer work usually can by from
The interference of external electromagnetic field, causes the race of program to fly, and is absorbed in endless loop, and the normal operation of program is interrupted, by single-chip microcomputer control
The system of system can not work on, and can cause the dead state that is absorbed in of whole system, occur unpredictable consequence, so for
The consideration monitored in real time to single-chip microcomputer running status, is just generated a kind of dedicated for monitoring SCM program running status
Chip, be commonly called as " house dog " (English claim watchdog).
House dog point hardware watchdog and software watchdog.Hardware watchdog is to utilize a timer circuit, its timing
Output is connected to the reset terminal of circuit, and program resets to timer in the range of certain time and (is commonly called as " feeding dog "), therefore program
During normal work, timer can not always overflow (it is " barking " that hereinafter referred to as timer, which overflows), cannot also produce reset signal.Such as
Fruit program is broken down, and house dog (being reset to timer) is resetted not in timing cycle, WatchDog Timer is allowed for and overflows
Go out to produce reset signal to lay equal stress on starting system.It is the same in software watchdog principle, simply the timer on hardware circuit is handled
The timer internal of device is replaced, and can so simplify hardware circuit design.
With the development of embedded hardware technology, the hardware of embedded system becomes increasingly complex.If the work electricity of system
Source voltage falls, and exception occur in the input and output or sequential that can make some digit chips, and then cause expiration operation very
To the generation of major accident.
In the prior art, embedded OS, which generally requires longer time, could complete the startup of whole system.It is main
If because the Bootloader (referring to the first paragraph code that embedded system is performed after power) of system is performed, Kernel
(referring to operating system nucleus) decompression is performed and File Sytem (referring to file system) loading is required for longer time to go completion.
Although watchdog chip special at present has voltage monitoring function, often " feeding dog " time interval of chip is short
And can not adjust, with conventional MAX706, (MAX706 is CMOS supervisory circuits, being capable of monitoring power voltage, battery failures and micro-
The working condition of processor) exemplified by, its " feeding dog " cycle is only 1.6s.If directly controlling host CPU to answer with the watchdog chip
Position, when the startup time of embedded OS being more than 1.6s, system has been reset in also never call " feeding dog " task,
So system will be unable to launch into mode of operation.
The content of the invention
It can be adjusted the technical problem to be solved in the present invention is to provide a kind of according to the startup time of operating system " feeding dog "
The monitoring module with power monitoring and delayed enable in cycle.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is：
The present invention's has the monitoring module that power monitoring and delayed are enabled, including module input and module output
End, control circuit is enabled between module input and module output end provided with electric source monitoring circuit and delayed, wherein,
Electric source monitoring circuit is made up of power monitoring chip, first resistor, second resistance and the first electric capacity, first resistor
One end connects with system power supply signal acquisition terminal, and its another voltage input end for being terminated at power monitoring chip simultaneously passes through the second electricity
Resistance connects with earth terminal；First electric capacity is connected in parallel with second resistance；
Delayed enables control circuit and is made up of programming device, 3rd resistor, the 4th resistance and the second electric capacity, the
Three resistance one end connect with operating voltage end, and another reset output terminal for being terminated at power monitoring chip is simultaneously connect by the 4th resistance
In the signal input part of programming device, the second electric capacity is connected across between the signal input part of programming device and earth terminal；
The module input is system power supply signal acquisition terminal；The end of module output end one is connected to programming device
Reset output terminal, the other end is connected to CPU, network interface card or other system application modules Enable Pin respectively.
The programming device is CPLD, field programmable gate array or single-chip microcomputer.
The programming device is made up of at least two timers and one with door, and the reset of the power monitoring chip is defeated
Go out to be terminated at first timer resets reset terminal and an input pin with door；Time of first timer, which overflows, is terminated at the
The start end of two timers, time of second timer overflows another input pin being terminated at door, second timer it is clear
The resetting of zero is terminated at a CPU I/O pin；Output end with door is described module output end.
The power monitoring chip be model be IMP809 chip.
Compared with prior art, the present invention realizes power supply by using the combination of power monitoring chip and programming device
Monitoring and electrification reset function, its input signal are the signal to be monitored extracted by system working power, power monitoring chip
Output signal the input of programming device is connected to for electrification reset or Voltage Drop reset signal, the signal is programmable
Multiple counters are set up in device and judge CL Compare Logic, completes that delayed is enabled, " barking " threshold is adjustable, house dog and answer
The functions such as digit pulse generation.
The design of the present invention realizes the house dog with a variety of functions using power monitoring chip and programming device, can
The problem of highly desirable reduction procedural problem and watchdog chip defect itself may be brought.And realize that simple and function is complete
Face.It is easy to apply in embedded hardware system.
Brief description of the drawings
Fig. 1 is the hardware elementary diagram of the present invention.
Fig. 2 is the hardware embodiment schematic diagram of the present invention
Reference is as follows：
Power monitoring chip U1, programming device U2, first timer Timer1, second timer Timer2, the first electricity
Hinder R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the first electric capacity C1, the second electric capacity C2.
Embodiment
The present invention is described in detail below in conjunction with the accompanying drawings.
The present invention obtains power monitoring signal by resistors match is used for input power monitoring chip U1, power monitoring chip
U1 signal outputs are connected by pull-up and build-out resistor with programming device U2.Programming device U2 is according to power monitoring chip U1
The reset signal of offer completes delayed, produces the watchdog functions such as reset signal.And completed by CPU to Programmable
Part U2 " feeding dog " operation.
As shown in figure 1, the present invention realizes power supply by power monitoring chip U1 (its model IMP809 monitoring chip)
Monitoring, to programming device U2, [programming device can for CPLD (English abbreviation CPLD), scene for it
Program gate array (English abbreviation FPGA) or single-chip microcomputer] reset signal is provided；By to electric on programming device U2 programming realizations
Be delayed, the function such as threshold of barking is adjustable, system reset pulses generation.
Described power monitoring chip U1 voltage monitorings input (also known as module input) connection is electricity to be monitored
Source voltage signal, the threshold voltage of power monitoring is realized by adjusting resistance first resistor R1 and second resistance R2 resistance.Institute
After the power monitoring chip U1 stated output end is pulled up by 3rd resistor R3, programming device U2 is connected to by the 4th resistance R4
Input.When the voltage of system electrification or voltage monitoring input is less than the threshold voltage set, power monitoring chip
U1 exports low level signal to programming device U2.
As shown in Fig. 2 the present invention completes electricity by setting up several timers or counter in programming device U2
Function that delay is enabled, house dog threshold is adjustable etc..
It is preferred that programming device U2 structure be：It is made up of two timers and one with door, the power monitoring
Chip U1 reset output terminal is connected to first timer Timer1 and resets reset terminal and an input pin with door；First timer
Timer1 time overflows the start end for being terminated at second timer Timer2, and second timer Timer2 time overflows termination
In another input pin with door, second timer Timer2 clearing resets an I/O end for being terminated at CPU；It is defeated with door
It is described module output end to enter end.
Power monitoring chip U1 reset output signal RST1 leads to programming device U2, and programming device U2 reset is defeated
Go out signal RST and lead to other devices such as CPU, network interface card.
Power monitoring chip U1 produces RST1 signals in upper electricity or Voltage Drop and programming device U2 progress logics is answered
Position.To CPU, network interface card etc., other devices carry out electrification reset to reset output signal RST.
First timer Timer1 in the RST1 signal enabling programming devices U2 that power monitoring chip U1 is produced.First
Timer Timer1 starts timing, and the signal for starting second timer Timer2 is produced after first timer Timer1 spillings.
Second timer Timer2 starts timing immediately, the output reset pulse RST2 after second timer Timer2 spillings.By adjusting
Whole first timer Timer1 and second timer Timer2 timing completes the threshold adjustable function of house dog.
Inside programming device U2, reseting pulse signal RST1 and RST2 by one two input with door, with door
The signal of output end (also known as module output end) output is the reset RST signal of system.
Second timer Timer2 reset signal by host CPU I/O foot control systems.Under normal circumstances, within a certain period of time,
CPU controls I/O pin low and high level change once, realizes and second timer Timer2 is reset, i.e., " feed dog " operates, and prevents the
Two timer Timer2, which overflow, starts output reset pulse RST2.
Claims (1)
1. a kind of monitoring module enabled with power monitoring and delayed, including module input and module output end, its
It is characterised by：Control circuit is enabled provided with electric source monitoring circuit and delayed between module input and module output end,
Wherein,
Electric source monitoring circuit is made up of power monitoring chip U1, first resistor R1, second resistance R2 and the first electric capacity C1, the first electricity
Resistance R1 one end connects with system power supply signal acquisition terminal, and its another voltage input end for being terminated at power monitoring chip U1 simultaneously leads to
Second resistance R2 is crossed with earth terminal to connect；First electric capacity C1 and second resistance R2 is connected in parallel；
Delayed enables control circuit and is made up of programming device U2,3rd resistor R3, the 4th resistance R4 and the second electric capacity C2,
3rd resistor R3 one end connects with operating voltage end, another reset output terminal for being terminated at power monitoring chip U1 and by the 4th
Resistance R4 is connected to programming device U2 signal input part, the second electric capacity C2 be connected across programming device U2 signal input part with
Between earth terminal；
The module input is system power supply signal acquisition terminal；The end of module output end one is connected to answering for programming device U2
Position output end, the other end is connected to CPU, network interface card or other system application modules Enable Pin respectively；
The programming device U2 is made up of at least two timers and one with door, and the reset of the power monitoring chip U1 is defeated
Go out to be terminated at first timer Timer1 resets reset terminal and an input pin with door；First timer Timer1 time
Overflow and be terminated at second timer Timer2 start end, second timer Timer2 time overflow be terminated at it is another with door
Individual input pin, second timer Timer2 clearing resets an I/O pin for being terminated at CPU；Output end with door is described
Module output end；
The power monitoring chip U1 be model be IMP809 chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510009532.6A CN104572331B (en) | 2015-01-08 | 2015-01-08 | The monitoring module enabled with power monitoring and delayed |
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| CN201510009532.6A CN104572331B (en) | 2015-01-08 | 2015-01-08 | The monitoring module enabled with power monitoring and delayed |
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| CN104572331A CN104572331A (en) | 2015-04-29 |
| CN104572331B true CN104572331B (en) | 2017-09-19 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106933319A (en) * | 2016-11-25 | 2017-07-07 | 科诺伟业风能设备（北京）有限公司 | A kind of current transformer DSP electrification reset control methods |
| CN106776096B (en) * | 2016-12-27 | 2019-12-06 | 兴唐通信科技有限公司 | reliable recovery method for embedded software error |
| CN107329847A (en) * | 2017-06-05 | 2017-11-07 | 深圳市有方科技股份有限公司 | The supervisory circuit of control system |
| CN112269347B (en) * | 2020-12-24 | 2021-03-16 | 深圳市鼎阳科技股份有限公司 | Power-on and power-off time sequence control device |
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| US5303390A (en) * | 1990-06-28 | 1994-04-12 | Dallas Semiconductor Corporation | Microprocessor auxiliary with combined pin for reset output and pushbutton input |
| CN1506825A (en) * | 2002-12-10 | 2004-06-23 | 深圳市中兴通讯股份有限公司 | Real-time adjustable reset method and device for watch dog |
| CN2681231Y (en) * | 2003-06-24 | 2005-02-23 | 华为技术有限公司 | A watchdog circuit |
| CN1908856A (en) * | 2005-08-05 | 2007-02-07 | 中兴通讯股份有限公司 | Position restoration circuit device |
| CN201163390Y (en) * | 2008-03-19 | 2008-12-10 | 长沙威胜信息技术有限公司 | Reset device used for electric load management and electrical energy data acquisition terminal |
| CN202737830U (en) * | 2012-06-17 | 2013-02-13 | 珠海中慧微电子有限公司 | Power supply monitoring circuit based on SW172x chip |
| CN103678780A (en) * | 2013-11-28 | 2014-03-26 | 中国船舶重工集团公司第七二二研究所 | Hardware fault tolerance circuit |
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2015
- 2015-01-08 CN CN201510009532.6A patent/CN104572331B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5303390A (en) * | 1990-06-28 | 1994-04-12 | Dallas Semiconductor Corporation | Microprocessor auxiliary with combined pin for reset output and pushbutton input |
| CN1506825A (en) * | 2002-12-10 | 2004-06-23 | 深圳市中兴通讯股份有限公司 | Real-time adjustable reset method and device for watch dog |
| CN2681231Y (en) * | 2003-06-24 | 2005-02-23 | 华为技术有限公司 | A watchdog circuit |
| CN1908856A (en) * | 2005-08-05 | 2007-02-07 | 中兴通讯股份有限公司 | Position restoration circuit device |
| CN201163390Y (en) * | 2008-03-19 | 2008-12-10 | 长沙威胜信息技术有限公司 | Reset device used for electric load management and electrical energy data acquisition terminal |
| CN202737830U (en) * | 2012-06-17 | 2013-02-13 | 珠海中慧微电子有限公司 | Power supply monitoring circuit based on SW172x chip |
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