CN110931568A - 薄膜晶体管及其制造方法 - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000002161 passivation Methods 0.000 claims abstract description 24
- 239000010949 copper Substances 0.000 claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052802 copper Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- VSSLEOGOUUKTNN-UHFFFAOYSA-N tantalum titanium Chemical compound [Ti].[Ta] VSSLEOGOUUKTNN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 22
- 229910001362 Ta alloys Inorganic materials 0.000 claims description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical group [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 abstract description 5
- 229910052719 titanium Inorganic materials 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000002738 chelating agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
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Abstract
本揭示提供了一种薄膜晶体管及其制造方法。所述薄膜晶体管包括：基板、闸极、闸极绝缘层、半导体层、源极和漏极、及钝化层。所述源极和所述漏极的结构皆为三层金属结构，且所述三层金属结构为钛钽/铜/钛钽结构，故在所述钝化层施加于所述源极和所述漏极上后，可有效改善所述钝化层的鼓包问题，且使所述薄膜晶体管具有较好的塑性而可用于柔性显示。
Description
【技术领域】
本揭示涉及晶体管的技术领域，特别涉及一种薄膜晶体管的结构及其制造方法。
【背景技术】
通常液晶显示器(LCD)使用的薄膜晶体管(Thin Film Transistor、TFT)中，源极和漏极的金属层使用的是两层钼/铜(Mo/Cu)结构，对于后通道蚀刻(Back ChannelEtched、BCE)结构中搭载镓锌氧化物(IGZO)的半导体层的薄膜晶体管器件而言，其钝化层(passivation layer、PV)通常为硅氧化物(SiOx)层，但由于硅氧化物和铜的应力不匹配，导致硅氧化物膜层在退火(anneal)阶段时容易发生鼓包。所以本发明旨在改善具有硅氧化物层的钝化层在与铜结合时的鼓包问题。
【发明内容】
为解决上述技术问题，本揭示的一目的在于提供一种薄膜晶体管，其能够有效改善钝化层与源极和漏极结合时的鼓包问题，且使所述薄膜晶体管具有较好的塑性而可用于柔性显示。
为达成上述目的，本揭示提供一种薄膜晶体管，其包括:基板、闸极、闸极绝缘层、半导体层、源极和漏极及钝化层。所述闸极设置于所述基板上。所述闸极绝缘层设置于所述闸极上并包覆所述闸极。所述半导体层设置于所述闸极绝缘层上并局部覆盖所述闸极绝缘层。所述源极和所述漏极形成于所述半导体层上，且所述源极和所述漏极间隔开。所述钝化层形成于所述源极、所述漏极、所述半导体层和所述闸极绝缘层上。其中，所述源极和所述漏极的结构皆为三层金属结构。
于本揭示的实施例中，所述三层金属结构的中间一层为铜(Cu)。
于本揭示的实施例中，所述三层金属结构的第一层金属结构为钛钽合金，第二层金属结构为铜，第三层金属结构为钛钽合金。
于本揭示的实施例中，所述钛元素和所述钽元素的原子比区间范围为25～35：65～75。
于本揭示的实施例中，所述半导体层为镓锌氧化物(IGZO)层或非晶硅(a-Si)层。
为达成上述目的，本揭示提供一种薄膜晶体管的制造方法，包含下列步骤：
提供基板；
于所述基板上形成闸极；
于所述闸极上形成闸极绝缘层；
于所述闸极绝缘层上形成半导体层；
于所述半导体层上形成源极和漏极；以及
于所述源极、所述漏极、所述半导体层和所述闸极绝缘层上形成钝化层；
其中，所述源极和所述漏极由同步蚀刻三层金属结构所获得。
于本揭示的实施例中，所述源极和所述漏极是利用铜酸蚀刻所述三层金属结构所获得。
于本揭示的实施例中，所述闸极可采用物理气相沉积方式制作膜层，并采用光刻工艺及湿法蚀刻方式图形化。
于本揭示的实施例中，所述半导体层可采用物理气相沉积或化学气相沉积方式制作膜层，并采用光刻工艺及蚀刻方式图形化。
为让本揭示的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
【附图说明】
图1显示具有本揭示的薄膜晶体管的示意图；
图2显示根据本揭示的薄膜晶体管移除钝化层后的示意图；以及
图3为本揭示的薄膜晶体管的制造方法步骤图。
【具体实施方式】
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
如图1-图2所示，本揭示的目的在于提供一种薄膜晶体管100。所述薄膜晶体管100包括：基板110、闸极120、闸极绝缘层130、半导体层140、源极150和漏极160、及钝化层1710。
其中，所述源极150和所述漏极160的结构皆为三层金属结构180，且所述三层金属结构180为钛钽/铜/钛钽(TaTi/Cu/TaTi)结构，故在所述钝化层170施加于所述源极150和所述漏极160上后，可有效改善所述钝化层170于退火阶段产生的鼓包问题，且使所述薄膜晶体管100具有较好的塑性而可用于柔性显示。
谨将本揭示的薄膜晶体管100所具有的结构详细说明如下：
如图1所示，所述闸极120设置于所述基板110上。所述闸极绝缘层130设置于所述闸极120上并包覆所述闸极120。所述半导体层140设置于所述闸极绝缘层130上并局部覆盖所述闸极绝缘层130。
所述源极150和所述漏极160形成于所述半导体层140上，且所述源极150和所述漏极160间隔开。所述钝化层170形成于所述源极150、所述漏极160、所述半导体层140和所述闸极绝缘层130上。因此，所述钝化层170用以自上而下地包覆所述源极150、所述漏极160、所述闸极绝缘层130及所述半导体层140。其中，所述源极150和所述漏极160的结构皆为三层金属结构180。
如图2所示，所述三层金属结构180是由二第一金属结构181分别自上侧及下侧夹设第二金属结构182所构成。所述第一金属结构181为钛钽(TiTa)合金，所述第二金属结构182为铜(Cu)，且所构成的所述三层金属结构180为钛钽/铜/钛钽(TiTa/Cu/TiTa)的结构。
此外，所述源极150和所述漏极160所用的铜酸需至少包含以下四种成分，过氧化氢(H2O2)、硝酸(HNO3)、氟化氢(HF)和其他添加剂(刻蚀抑制剂、螯合剂等)。
换言之，由于所述第一金属结构181的钛钽合金不仅可以和构成钝化层170的硅氧化物层(SiOx)的应力匹配，所述第一金属结构181的钛钽合金更具有优良的超塑性，可应用于柔性显示，并且可实现大曲率的弯折。
于本揭示中，所述闸极120为铜。所述半导体层140为镓锌氧化物(IGZO)层或非晶硅(a-Si)层。所述钝化层170为硅氧化物层(SiOx)。
如图3所示，本揭示的薄膜晶体管的制造方法包含下列步骤：
S1：提供基板110；
S2：于所述基板110上形成闸极120；
S3：于所述闸极120上形成闸极绝缘层130；
S4：于所述闸极绝缘层130上形成半导体层140；
S5：于所述半导体层140上形成源极150和漏极160；以及
S6：于所述源极150、所述漏极160、所述半导体层140和所述闸极绝缘层130上形成钝化层170；
其中，所述源极150和所述漏极160由同步蚀刻三层金属结构所获得。
以下将对各层的制作方式进行说明。
于本揭示中，所述闸极120可采用物理气相沉积方式制作膜层，并采用光刻工艺及湿法蚀刻方式图形化。所述半导体层140可采用物理气相沉积或化学气相沉积方式制作膜层，并采用光刻工艺及蚀刻方式图形化。所述第一金属结构181可采用物理气相沉积方式制作膜层，并采用光刻工艺及湿法蚀刻方式图形化。所述钝化层170可用化学气相沉积方式制作膜层，并采用光刻工艺和干法刻蚀图形化。
此外，于本揭示的较佳实施例中，所述钛(Ti)元素和所述钽(Ta)元素的原子比区间范围为25～35：65～75。透过上述原子比的比例，所述钛钽合金不仅可以和构成钝化层170的硅氧化物层的应力匹配，更可具有优良的超塑性，能够应用于柔性显示并且可实现大曲率的弯折。
综上所述，由于本揭示所提供的薄膜晶体管100能够藉由所述三层金属结构180的设置，让所述三层金属结构180所具有的所述第一金属结构181的钛钽合金可以和构成所述钝化层170的硅氧化物层的应力匹配，改善现有技术中钝化层会在铜表面鼓包的问题，且所述第一金属结构181的钛钽合金还具有优良的超塑性，可应用于柔性显示以实现大曲率的弯折，并因此可应用于液晶显示、主动式有机电发光二极管显示(AMOLED)及其他柔性显示。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示)，即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。
Claims (9)
1.一种薄膜晶体管，其特征在于，包括:
基板；
闸极，设置于所述基板上；
闸极绝缘层，设置于所述闸极上并包覆所述闸极；
半导体层，设置于所述闸极绝缘层上并局部覆盖所述闸极绝缘层；
源极和漏极，形成于所述半导体层上，且所述源极和所述漏极间隔开；以及
钝化层，形成于所述源极、所述漏极、所述半导体层和所述闸极绝缘层上；
其中，所述源极和所述漏极的结构皆为三层金属结构。
2.如权利要求1所述的薄膜晶体管，其特征在于，所述三层金属结构的中间一层为铜(Cu)。
3.如权利要求2所述的薄膜晶体管，其特征在于，所述三层金属结构的第一层金属结构为钛钽合金，第二层金属结构为铜，第三层金属结构为钛钽合金。
4.如权利要求3所述的薄膜晶体管，其特征在于，所述钛元素和所述钽元素的原子比区间范围为25～35：65～75。
5.如权利要求1所述的薄膜晶体管，其特征在于，所述半导体层为镓锌氧化物(IGZO)层或非晶硅(a-Si)层。
6.一种薄膜晶体管的制造方法，包含下列步骤：
提供基板；
于所述基板上形成闸极；
于所述闸极上形成闸极绝缘层；
于所述闸极绝缘层上形成半导体层；
于所述半导体层上形成源极和漏极；以及
于所述源极、所述漏极、所述半导体层和所述闸极绝缘层上形成钝化层；
其中，所述源极和所述漏极由同步蚀刻三层金属结构所获得。
7.如权利要求6所述的制造方法，其特征在于，所述源极和所述漏极是利用铜酸蚀刻所述三层金属结构所获得。
8.如权利要求6所述的制造方法，其特征在于，所述闸极可采用物理气相沉积方式制作膜层，并采用光刻工艺及湿法蚀刻方式图形化。
9.如权利要求6所述的制造方法，其特征在于，所述半导体层可采用物理气相沉积或化学气相沉积方式制作膜层，并采用光刻工艺及蚀刻方式图形化。
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| CN103022007A (zh) * | 2011-09-28 | 2013-04-03 | 中芯国际集成电路制造(上海)有限公司 | 用于铜互连的钛掺杂钽基阻挡层及其制造方法 |
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| CN113764282B (zh) * | 2021-09-03 | 2023-09-05 | 深圳市华星光电半导体显示技术有限公司 | 一种背沟道蚀刻型的薄膜电晶体及其制作方法 |
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