CN110797392A - 外延结构 - Google Patents

外延结构 Download PDF

Info

Publication number
CN110797392A
CN110797392A CN201910547464.7A CN201910547464A CN110797392A CN 110797392 A CN110797392 A CN 110797392A CN 201910547464 A CN201910547464 A CN 201910547464A CN 110797392 A CN110797392 A CN 110797392A
Authority
CN
China
Prior art keywords
value
regions
gradient
values
epitaxial structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910547464.7A
Other languages
English (en)
Other versions
CN110797392B (zh
Inventor
刘嘉哲
黄彦纶
施英汝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalWafers Co Ltd
Original Assignee
GlobalWafers Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalWafers Co Ltd filed Critical GlobalWafers Co Ltd
Publication of CN110797392A publication Critical patent/CN110797392A/zh
Application granted granted Critical
Publication of CN110797392B publication Critical patent/CN110797392B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • C30B25/183Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/40AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403AIII-nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02502Layer structure consisting of two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/0251Graded layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22Roughened surfaces, e.g. at the interface between epitaxial layers
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • C30B25/20Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明提供一种外延结构,包括:基板、成核层、缓冲层以及氮化物层。成核层设置于基板上,所述成核层于厚度方向上由多个区域组成,所述区域的化学组成为Al(1‑x)InxN,其中0≤x≤1。缓冲层设置于成核层上,成核层的厚度小于缓冲层的厚度。氮化物层则设置于缓冲层上,其中所述成核层与所述缓冲层接触的表面的粗糙度大于所述缓冲层与所述氮化物层接触的表面的粗糙度。

Description

外延结构
技术领域
本发明涉及一种半导体结构,尤其涉及一种外延结构。
背景技术
由于外延制程所形成的膜层具有纯度高、厚度控制性佳等优点,因此目前已经广泛应用于射频(RF)元件或功率元件的制造中。
一般的RF元件所采用的外延结构中会在硅基板上形成一层作为成核层的氮化铝(AlN)层,再接续外延制程。然而,在成核层和硅基板界面常有成核层材料本身所引发的自发极化;或者因成核层和基板晶格不匹配引发压电极化,导致寄生信道的存在,因而增加RF损失(RF loss)。此外,成核层中的铝原子还容易扩散至硅基板表面,导致高导电层的形成,产生泄漏电流,也会影响RF元件特性。
发明内容
本发明提供一种外延结构,可解决传统外延结构中的成核层中的金属原子扩散至基板,降低RF的损失,进而不影响RF元件特性。
本发明的一种外延结构包括,基板、成核层、缓冲层、以及氮化物层。成核层设置于所述基板上,成核层于厚度方向上由多个区域组成,所述区域的化学组成为Al(1-x)InxN,其中0≤x≤1。缓冲层设置于所述成核层上,以及氮化物层设置于所述缓冲层上。所述成核层的厚度小于所述缓冲层的厚度,且成核层与缓冲层接触的表面的粗糙度大于缓冲层与氮化物层接触的表面的粗糙度。
在本发明的一实施例中,上述多个区域中的x值的最大值皆相同、x值的最小值皆相同,且每个区域的渐变斜率的绝对值为0.1%/nm~50%/nm。
在本发明的一实施例中,上述多个区域中的x值的最大值沿着所述厚度方向减小,而上述多个区域中的x值的最小值皆相同,每个区域的渐变斜率的绝对值为0.1%/nm~50%/nm,且上述多个区域的步阶斜率为-0.1%/回路(loop)~-50%/回路。
在本发明的一实施例中,上述多个区域中的x值的最大值沿着所述厚度方向减小,而上述多个区域中的x值的最小值皆相同,每四个区域的化学组成中的x值是由四段变化所组成,所述四段变化包括:由最大值渐变至最小值的第一渐变区、由最小值渐变至最大值的第二渐变区、由最大值渐变至最小值的第三渐变区以及由最小值渐变至最大值的第四渐变区,所述第一、第二以及第三渐变区中的x值的最大值相同,所述第四渐变区的x值的最大值则是第一渐变区的x值的最大值以步阶斜率为-0.1%/回路(loop)~-50%/回路减少的值,且每个区域的渐变斜率的绝对值为0.1%/nm~50%/nm。
在本发明的一实施例中,上述每个区域的化学组成中的x值沿着厚度方向以周期渐变式增加或减少。
在本发明的一实施例中,上述每四个区域的化学组成中的x值是沿着所述厚度方向由四段变化所组成,所述四段变化包括:最大值的第一固定区、由所述最大值渐变至最小值的第一渐变区、所述最小值的第二固定区以及由所述最小值渐变至所述最大值的第二渐变区,其中所述第一渐变区与所述第二渐变区的渐变斜率的绝对值为0.1%/nm~50%/nm。
在本发明的一实施例中,上述多个区域的化学组成中的x值沿着所述厚度方向以步阶式减小,每个区域中x值沿着所述厚度方向不变,且所述多个区域的步阶斜率为-0.1%/回路~-50%/回路。
在本发明的一实施例中,上述每个区域的化学组成中的x值沿着所述厚度方向以步阶式渐变减少。
在本发明的一实施例中,上述多个区域中的x值的最大值沿着所述厚度方向减小,每两个区域的化学组成中的x值是由固定区与渐变区所组成,其中所述渐变区的渐变斜率为-0.1%/nm~-50%/nm,且所述多个区域中的固定区的步阶斜率为-0.1%/回路~-50%/回路。
在本发明的一实施例中,上述每两个区域的化学组成中的x值分别为两个定值并沿着所述厚度方向堆叠。
在本发明的一实施例中,上述的x值以线性方式沿着所述厚度方向减小,所述x值的渐变斜率为-0.1%/nm~-50%/nm
在本发明的一实施例中,上述x值沿着所述厚度方向保持不变,且所述x值不小于10%。
在本发明的一实施例中,上述成核层的x值的起始含量为10%~100%,结束含量为0%~90%,所述(1-x)值的起始含量为0%~90%,结束含量为10%~100%。
基于上述,本发明的外延结构由于成核层中具有多个区域,且每个区域的化学组成为Al(1-x)InxN,x值沿着厚度方向具有不同类型的变化,因此可以解决传统外延结构中的成核层与硅基板因有较大自发性极化与晶格不匹配所产生的压电极化,而造成寄生信道存在的问题,也能解决成核层原子扩散至硅基板而产生的界面电阻降低的问题,进一步地降低RF的损失,且不影响RF元件特性。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1是依照本发明的一实施例的一种外延结构的剖面示意图。
图2是上述实施例的一种外延结构中的成核层呈现固定式含量变化的示意图。
图3是上述实施例的一种外延结构中的成核层呈现渐变式含量变化的示意图。
图4是上述实施例的一种外延结构中的成核层呈现步阶式含量变化的示意图。
图5是上述实施例的一种外延结构中的成核层呈现步阶式渐变含量变化的示意图。
图6是上述实施例的一种外延结构中的成核层呈现周期式含量变化的示意图。
图7是上述实施例的一种外延结构中的成核层呈现周期渐变式含量变化的示意图。
图8是上述实施例的一种外延结构中的成核层呈现一种完全渐变式含量变化的示意图。
图9是上述实施例的一种外延结构中的成核层呈现另一种完全渐变式含量变化的示意图。
图10是上述实施例的一种外延结构中的成核层呈现再一种完全渐变式含量变化的示意图。
【符号说明】
100:基板
102:成核层
102a、104a:表面
104:缓冲层
106:氮化物层
108:阻障层
110、110a、110b、110c、110d:区域
具体实施方式
下文列举一些实施例并配合所附附图来进行详细地说明,但所提供的实施例并非用以限制本发明所涵盖的范围。此外,附图仅以说明为目的,并未依照原尺寸作图。为了方便理解,下述说明中相同的元件将以相同的符号标示来说明。
图1是依照本发明的一实施例的一种外延结构的剖面示意图。
请参照图1,本实施例的外延结构包括基板100、成核层102、缓冲层104、氮化物层106以及阻障层108。基板100的材料例如Si、Al2O3、SiC、GaAs或其他适合的材料。
成核层102设置于基板100上,其中成核层102的厚度小于缓冲层104的厚度,且成核层102与缓冲层104接触的表面102a的粗糙度大于缓冲层104与氮化物层106接触的表面104a的粗糙度。成核层102于厚度方向上由多个区域110组成,其中多个区域110的化学组成为Al(1-x)InxN,其中0≤x≤1。x值表示In(铟)含量,(1-x)值表示Al(铝)含量。此外,在本文中所叙述的一个“区域”的定义为x值的一种变化,但区域的数目不一定代表层数,因为制程的关系,单一层结构中可能包含x值的多种变化,因此单一层可以是单一或由多个区域110组成。在图1中虽然显示的是4个区域110,但本发明并不限于此;在其它实施例中,区域110的数目例如2~100;较佳为2~20,在此范围内能得到较佳的界面质量与二维电子气(2DEG)特性。成核层102与缓冲层104接触的表面102a的粗糙度(rms)通常在1nm~10nm之间;1nm~3nm较佳,在此范围内能得到较佳的界面质量与2DEG特性。成核层102的厚度例如1nm~500nm,较佳为1nm~200nm,在此范围内能得到较佳的界面质量与2DEG特性。本实施例中通过设置成核层102,可减少压电与自发性极化量,改善寄生信道所导致的高导电层,亦可减少外延结构的应力、调整外延生长后的外延结构的翘曲度,并可改善龟裂长度。
缓冲层104则设置于成核层102上,其材料例如氮化铝(AlN)等,且缓冲层104与氮化物层106的接触的表面104a的粗糙度(rms)例如0.2nm~3nm之间,小于成核层102的表面102a的粗糙度,将有助于后续氮化物层106外延成长。缓冲层104的厚度通常大于500nm。于本实施例的外延结构中设置缓冲层104,作为应力补偿调整,并调整外延生长后的外延结构的翘曲度,藉此可改善龟裂长度。氮化物层106设置于缓冲层104上,其材料例如氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、氮化铝镓铟(AlGnInN)等。另外,在一实施例中,外延结构还可于氮化物层106上设置阻障层(barrier layer)108,其材料例如氮化铝(AlN)、氮化铟(InN)、氮化铝镓铟(AlGnInN)、氮化铝铟(AlInN)。
图2至图10是上述实施例的一种外延结构中的成核层的各种含量变化的示意图,其中“含量”是指x值。
图2是成核层呈现固定式含量变化的示意图。请参照图2,所述的固定式含量变化是定义为多个区域110的化学组成Al(1-x)InxN中的x值,沿着成核层厚度方向维持不变,且x值不小于10%(即,铟含量比例不小于10%),较佳为不小于60%,在此范围内能得到较佳的界面质量与2DEG特性。成核层的厚度例如1nm~500nm,较佳为1nm~200nm;且成核层的表面粗糙度例如1nm~10nm,较佳为1nm~3nm。成核层的制程温度通常是500℃~850℃,较佳为500℃~700℃,在此范围内能得到较佳的界面质量与2DEG特性。
图3是成核层呈现渐变式含量变化的示意图。请参照图3,所述的渐变式含量变化是定义为多个区域110中的化学组成Al(1-x)InxN中的x值沿着厚度方向以线性方式减少,且渐变斜率例如-0.1%/nm~-50%/nm,较佳为-0.5%/nm~-10%/nm,在此范围内能得到较佳的界面质量与2DEG特性。而且,x值的起始含量例如10%~100%,较佳为50%~100%,在此范围内能得到较佳的界面质量与2DEG特性,结束含量例如0%~90%,较佳为0%~50%,在此范围内能得到较佳的界面质量与2DEG特性。(1-x)值的起始含量例如0%~90%,较佳为0~50%,结束含量例如10%~100%,较佳为50~100%。成核层厚度例如1nm~500nm,较佳为1nm~200nm,且成核层表面粗糙度为1nm~10nm,较佳为1nm~3nm。
于另一实施例中,x值起始含量为100%,结束含量为0%。(1-x)值的起始含量为0%,结束含量为100%。
图4是成核层呈现步阶式含量变化的示意图。请参照图4,所述的步阶式含量变化是定义为多个区域110中的化学组成Al(1-x)InxN中的x值沿着厚度方向以步阶式减小,每个区域110中x值沿着厚度方向不变,且多个区域110的步阶斜率为-0.1%/回路(loop)~-50%/回路,较佳为-0.1%/回路~-20%/回路,在此范围内能得到较佳的界面质量与2DEG特性。在本文中,用语“回路”代表的是具有两种不同高低含量,并且周期性的方式推叠。而且,x值的起始含量例如10%~100%,较佳为50%~100%,结束含量例如0~90%,较佳为0~50%。(1-x)值的起始含量例如0~90%,较佳为0~50%,且结束含量例如10%~100%,较佳为50%~100%。而成核层厚度例如1nm~500nm,较佳为1nm~50nm。成核层中的区域110的数目为2~100,较佳为2~20,在此范围内能得到较佳的界面质量与2DEG特性。成核层的表面粗糙度例如1nm~10nm,较佳为1nm~3nm。
图5是成核层呈现步阶式渐变含量变化的示意图。请参照图5,所述的步阶式渐变含量变化是定义为多个区域110中的化学组成Al(1-x)InxN中的x值的最大值沿着厚度方向减小的变化,且每两个区域110的化学组成中的x值是由固定区与渐变区所组成;也就是说,每两个区域110是由一个x值为定值的固定区与一个x值以线性减少的渐变区所组成。图5中,固定区以步阶式减少,其步阶斜率例如为-0.1%/回路~-50%/回路,较佳为-0.1%/回路~-20%/回路(loop),且渐变区的渐变斜率例如-0.1%/nm~-50%/nm,较佳为-0.5%/nm~-10%/nm。
在步阶式渐变中,x值的起始含量例如10%~100%,较佳为50%~100%,结束含量例如0~90%,较佳为0~50%。(1-x)值的起始含量例如0~90%,较佳为0~50%,且结束含量例如10%~100%,较佳为50%~100%。而成核层厚度例如1nm~500nm,较佳为1nm~50nm,且成核层的区域110的数目例如2~100,较佳为2~20。成核层的表面粗糙度例如1nm~10nm,较佳为1nm~3nm。
图6是成核层呈现周期式含量变化的示意图。请参照图6,每两个区域110的化学组成中的x值分别为两个定值并沿着所述厚度方向堆叠。其中,x值的起始含量例如10%~100%,较佳为50%~100%,结束含量例如0~90%,较佳为0~50%。在本文中所谓的“起始含量”是指成核层与基板接触端为起始处;而“结束含量”是指成核层与缓冲层接触端为结束处。(1-x)值的起始含量例如0~90%,较佳为0~50%,且结束含量例如10%~100%,较佳为50%~100%。而成核层厚度例如1nm~500nm,较佳为1nm~50nm,且成核层的区域110的数目例如2~100,较佳为2~20。成核层的表面粗糙度例如1nm~10nm,较佳为1nm~3nm。
图7是成核层呈现周期渐变式含量变化的示意图。请参照图7,所述的周期渐变式含量变化是定义为x值沿着厚度方向以周期渐变式增加或减少,例如成核层中每四个区域110的化学组成Al(1-x)InxN中的x值是沿着厚度方向由四段变化所组成,其中所述四段变化包括:最大值为一定值的第一固定区、由最大值渐变至最小值的第一渐变区、最小值为另一定值的第二固定区以及由所述最小值渐变至所述最大值的第二渐变区。其中第一渐变区与第二渐变区的渐变斜率的绝对值例如0.1%/nm~50%/nm,较佳为0.5%/nm~10%/nm。
在周期渐变式变化中,x值的起始含量例如10%~100%,较佳为50%~100%,结束含量例如0~90%,较佳为0~50%。(1-x)值的起始含量例如0~90%,较佳为0~50%,且结束含量例如10%~100%,较佳为50%~100%。而成核层的厚度例如1nm~500nm,较佳为1nm~50nm,且成核层的区域110的数目例如4~100,较佳为4~20。成核层的表面粗糙度例如1nm~10nm,较佳为1nm~3nm。
图8、图9与图10是成核层呈现出来的三种完全渐变式含量变化的示意图。
所述的完全渐变式含量变化是定义为每个区域110的化学组成中的x值沿着厚度方向以完全渐变式增加或减少。
请先参照图8,区域110中x值的最大值皆相同、x值的最小值皆相同,且每个区域110的渐变斜率的绝对值例如0.1%/nm~50%/nm,较佳为0.5%/nm~10%/nm。其中,x值的起始含量例如10%~100%,较佳为50%~100%,结束含量例如0~90%,较佳为0~50%。(1-x)值的起始含量例如0~90%,较佳为0~50%,且结束含量例如10%~100%,较佳为50%~100%。而成核层厚度例如1nm~500nm,较佳为1nm~50nm。且成核层的区域110的数目例如2~100,较佳为2~20。成核层的表面粗糙度例如1nm~10nm,较佳为1nm~3nm。
在图9中,多个区域110中的x值的最大值沿着厚度方向减小、x值的最小值则都相同,其中每个区域110的渐变斜率的绝对值例如0.1%/nm~50%/nm,较佳为0.5%/nm~10%/nm,且区域110的步阶斜率的绝对值例如0.1%/回路(loop)~50%/回路,较佳为0.5%/回路~10%/回路。x值的起始含量例如10%~100%,较佳为50%~100%,结束含量例如0~90%,较佳为0~50%。(1-x)值的起始含量例如0~90%,较佳为0~50%,且结束含量例如10%~100%,较佳为50%~100%。成核层厚度则例如1nm~500nm,较佳为1nm~50nm,且成核层的区域110的数目例如2~100,较佳为2~20。成核层的表面粗糙度例如1nm~10nm,较佳为1nm~3nm。
在图10中,多个区域110a-110d中的x值的最大值沿着厚度方向减小,而x值的最小值皆相同,且每四个区域110a-110d的化学组成中的x值是由四段变化所组成。所述四段变化包括:由最大值渐变至最小值的第一渐变区110a、由最小值渐变至最大值的第二渐变区110b、由最大值渐变至最小值的第三渐变区110c以及由最小值渐变至最大值的第四渐变区110d,第一渐变区110a、第二渐变区110b以及第三渐变区110c中的x值的最大值相同,而第四渐变区110d中的x值的最大值为第一渐变区110a(第二渐变区110b以及第三渐变区110c)的x值的最大值以步阶斜率-0.1%/回路~-50%/回路减少的值,所述步阶斜率较佳为-0.5%/回路~-10%/回路,且区域110a-110d中的每一个的渐变斜率的绝对值例如0.1%/nm~50%/nm,较佳为0.5%/nm~10%/nm。
在图10中,x值的起始含量例如10%~100%,较佳为50%~100%,结束含量例如0~90%,较佳为0~50%。(1-x)值的起始含量例如0~90%,较佳为0~50%,且结束含量例如10%~100%,较佳为50%~100%。而成核层厚度例如1nm~500nm,较佳为1nm~50nm。成核层的区域110a-110d的数目例如4~100,较佳为4~20,在此范围内能得到较佳的界面质量与2DEG特性。成核层的表面粗糙度例如1nm~10nm,较佳为1nm~3nm。
以解决RF的损失的观点来看,优选为图8~图10的实施方式,这是因为成核层与缓冲层的界面为连续性变化,因此能降低界面的缺陷密度,可改善外延材料质量与界面平整度,此外,由于界面为连续性变化,所产生的界面应力较小,因而极化量相对较低,可有效改善寄生信道所造成的高导电层,因此可降低RF损失(RF loss)。
综上所述,根据本发明的外延结构,通过Al(1-x)InxN的成核层中不同含量(x值)变化,能改善传统成核层(AlN)的问题。下表一显示的是传统成核层与本发明成核层应用于外延结构的预期RF特性。
表一
Figure BDA0002104414970000091
根据表一可知,本发明的成核层由于与硅基板具有较好的晶格匹配度与较低的自发性极化和较低压电极化效应,且可降低硅基板中铝的扩散,因此能降低RF损失并确保RF特性。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中的技术人员,在不脱离本发明的精神和范围内,当可作些许的更改与润饰,故本发明的保护范围当视权利要求所界定的为准。

Claims (11)

1.一种外延结构,其特征在于包括:
基板;
成核层,设置于所述基板上,所述成核层于厚度方向上由多个区域组成,所述多个区域的化学组成为Al(1-x)InxN,其中0≤x≤1;
缓冲层,设置于所述成核层上,其中所述成核层的厚度小于所述缓冲层的厚度;以及
氮化物层,设置于所述缓冲层上,其中所述成核层与所述缓冲层接触的表面的粗糙度大于所述缓冲层与所述氮化物层接触的表面的粗糙度。
2.根据权利要求1所述的外延结构,其中所述多个区域中的所述x值的最大值皆相同,所述多个区域中的所述x值的最小值皆相同,且每个所述区域的渐变斜率的绝对值为0.1%/nm~50%/nm。
3.根据权利要求1所述的外延结构,其中所述多个区域中的所述x值的最大值沿着所述厚度方向减小,所述多个区域中的所述x值的最小值皆相同,每个所述区域的渐变斜率的绝对值为0.1%/nm~50%/nm,且所述多个区域的步阶斜率为-0.1%/回路~-50%/回路。
4.根据权利要求1所述的外延结构,其中所述多个区域中的所述x值的最大值沿着所述厚度方向减小,所述多个区域中的所述x值的最小值皆相同,每四个所述区域的化学组成中的所述x值是由四段变化所组成,所述四段变化包括:由最大值渐变至最小值的第一渐变区、由最小值渐变至最大值的第二渐变区、由最大值渐变至最小值的第三渐变区以及由最小值渐变至最大值的第四渐变区,所述第一渐变区、所述第二渐变区以及所述第三渐变区中的所述x值的最大值相同,所述的第四渐变区的所述x值的最大值为所述第一渐变区的所述x值的最大值以步阶斜率为-0.1%/回路~-50%/回路减少的值,且每个所述区域的渐变斜率的绝对值为0.1~50%/nm。
5.根据权利要求1所述的外延结构,其中每四个所述区域的化学组成中的所述x值是沿着所述厚度方向由四段变化所组成,所述四段变化包括:最大值的第一固定区、由所述最大值渐变至最小值的第一渐变区、所述最小值的第二固定区以及由所述最小值渐变至所述最大值的第二渐变区,其中所述第一渐变区与所述第二渐变区的渐变斜率的绝对值为0.1%/nm~50%/nm。
6.根据权利要求1所述的外延结构,其中所述多个区域的化学组成中的所述x值沿着所述厚度方向以步阶式减小,每个所述区域中所述x值沿着所述厚度方向不变,且所述多个区域的步阶斜率为-0.1%/回路~-50%/回路。
7.根据权利要求1所述的外延结构,其中所述多个区域中的所述x值的最大值沿着所述厚度方向减小,每两个所述区域的化学组成中的所述x值是由固定区与渐变区所组成,其中所述渐变区的渐变斜率为-0.1%/nm~-50%/nm,且所述多个区域中的所述固定区的步阶斜率为-0.1%/回路~-50%/回路。
8.根据权利要求1所述的外延结构,其中每两个所述区域的化学组成中的所述x值分别为两个定值并沿着所述厚度方向堆叠。
9.根据权利要求1所述的外延结构,其中所述x值以线性方式沿着所述厚度方向减小,所述x值的渐变斜率为-0.1%/nm~-50%/nm。
10.根据权利要求1所述的外延结构,其中所述x值沿着所述厚度方向保持不变,且所述x值不小于10%。
11.根据权利要求1~9中任一项所述的外延结构,其中所述成核层的所述x值的起始含量为10%~100%,结束含量为0%~90%,所述(1-x)值的起始含量为0%~90%,结束含量为10%~100%。
CN201910547464.7A 2018-08-01 2019-06-24 外延结构 Active CN110797392B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW107126691 2018-08-01
TW107126691A TWI671801B (zh) 2018-08-01 2018-08-01 磊晶結構

Publications (2)

Publication Number Publication Date
CN110797392A true CN110797392A (zh) 2020-02-14
CN110797392B CN110797392B (zh) 2023-04-18

Family

ID=68618993

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910547464.7A Active CN110797392B (zh) 2018-08-01 2019-06-24 外延结构

Country Status (3)

Country Link
US (4) US11316007B2 (zh)
CN (1) CN110797392B (zh)
TW (1) TWI671801B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022232717A2 (en) * 2021-02-17 2022-11-03 Cornell University Integrated quantum computing with epitaxial materials

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW398084B (en) * 1998-06-05 2000-07-11 Hewlett Packard Co Multilayered indium-containing nitride buffer layer for nitride epitaxy
US20080237640A1 (en) * 2007-03-29 2008-10-02 The Regents Of The University Of California N-face high electron mobility transistors with low buffer leakage and low parasitic resistance
US20130207078A1 (en) * 2012-01-18 2013-08-15 Kopin Corporation InGaN-Based Double Heterostructure Field Effect Transistor and Method of Forming the Same
US20150187876A1 (en) * 2013-12-31 2015-07-02 Industrial Technology Research Institute Nitride semiconductor structure
CN106711252A (zh) * 2016-11-25 2017-05-24 中国科学院半导体研究所 一种包含缓冲层的外延结构及其制备方法
CN108026638A (zh) * 2015-10-21 2018-05-11 爱沃特株式会社 具备SiC层的化合物半导体基板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649287B2 (en) 2000-12-14 2003-11-18 Nitronex Corporation Gallium nitride materials and methods
JP6015053B2 (ja) * 2012-03-26 2016-10-26 富士通株式会社 半導体装置の製造方法及び窒化物半導体結晶の製造方法
KR20130141290A (ko) 2012-06-15 2013-12-26 삼성전자주식회사 초격자 구조체 및 이를 포함한 반도체 소자
KR102098250B1 (ko) * 2013-10-21 2020-04-08 삼성전자 주식회사 반도체 버퍼 구조체, 이를 포함하는 반도체 소자 및 반도체 버퍼 구조체를 이용한 반도체 소자 제조방법
KR20150085724A (ko) * 2014-01-16 2015-07-24 엘지전자 주식회사 질화물 반도체 소자 및 그 제조 방법
US10622447B2 (en) * 2017-03-29 2020-04-14 Raytheon Company Group III-nitride structure having successively reduced crystallographic dislocation density regions
US11444172B2 (en) * 2017-12-01 2022-09-13 Mitsubishi Electric Corporation Method for producing semiconductor device and semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW398084B (en) * 1998-06-05 2000-07-11 Hewlett Packard Co Multilayered indium-containing nitride buffer layer for nitride epitaxy
US20080237640A1 (en) * 2007-03-29 2008-10-02 The Regents Of The University Of California N-face high electron mobility transistors with low buffer leakage and low parasitic resistance
US20130207078A1 (en) * 2012-01-18 2013-08-15 Kopin Corporation InGaN-Based Double Heterostructure Field Effect Transistor and Method of Forming the Same
US20150187876A1 (en) * 2013-12-31 2015-07-02 Industrial Technology Research Institute Nitride semiconductor structure
CN108026638A (zh) * 2015-10-21 2018-05-11 爱沃特株式会社 具备SiC层的化合物半导体基板
CN106711252A (zh) * 2016-11-25 2017-05-24 中国科学院半导体研究所 一种包含缓冲层的外延结构及其制备方法

Also Published As

Publication number Publication date
US20220199761A1 (en) 2022-06-23
US20200044015A1 (en) 2020-02-06
TWI671801B (zh) 2019-09-11
US11588014B2 (en) 2023-02-21
TW202008427A (zh) 2020-02-16
US20220199762A1 (en) 2022-06-23
US11316007B2 (en) 2022-04-26
US11588015B2 (en) 2023-02-21
US20220199763A1 (en) 2022-06-23
CN110797392B (zh) 2023-04-18
US11532700B2 (en) 2022-12-20

Similar Documents

Publication Publication Date Title
US10026814B2 (en) P-doping of group-III-nitride buffer layer structure on a heterosubstrate
US10615273B2 (en) Semiconductor devices having a plurality of unit cell transistors that have smoothed turn-on behavior and improved linearity
US20050133816A1 (en) III-nitride quantum-well field effect transistors
US20210193825A1 (en) Semiconductor devices having a plurality of unit cell transistors that have smoothed turn-on behavior and improved linearity
US8357571B2 (en) Methods of forming semiconductor contacts
EP1889297A1 (en) Group iii nitride epitaxial layers on silicon carbide substrates
US8785942B2 (en) Nitride semiconductor substrate and method of manufacturing the same
CN109817698A (zh) 形成用于氮化镓沟道器件的半导体结构的方法
JP2009260296A (ja) 窒化物半導体エピタキシャルウエハ及び窒化物半導体素子
US20210050422A1 (en) Epitaxial structure
CN110797392B (zh) 外延结构
US10943998B2 (en) Digital alloy based back barrier for P-channel nitride transistors
CN100501951C (zh) 场效应晶体管、半导体器件、其制造方法和半导体晶体生长方法
Higashiwaki et al. High-performance short-gate InAlN/GaN heterostructure field-effect transistors
US6818928B2 (en) Quaternary-ternary semiconductor devices
US20180342649A1 (en) Heterostructure with Stress Controlling Layer
US11923454B2 (en) Epitaxial structure having super-lattice laminates
Prystawko et al. AlGaN HEMTs on patterned resistive/conductive SiC templates
TW202105740A (zh) 增強型金屬絕緣半導體之高電子移動率電晶體
US20230045328A1 (en) Semiconductor structure
CN111033750B (zh) 用于p沟道氮化物晶体管的基于数字合金的背势垒
CN218602436U (zh) 半导体外延结构和半导体器件
Basceri et al. 100 V to 1800 V high performance p-GaN hemt epitaxial layers and e-mode power devices on 8-inch commercial QST® substrates
US20200098907A1 (en) Iii-nitride epitaxial structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant