CN110749763A - Triggering method based on I2S signal and oscilloscope - Google Patents
Triggering method based on I2S signal and oscilloscope Download PDFInfo
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Abstract
A triggering method and an oscilloscope based on an I2S signal are provided, wherein the triggering method comprises the following steps: performing time sequence alignment on various types of data in an I2S signal to obtain an aligned signal, wherein the I2S signal comprises frame synchronization data, clock data and audio data; extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal; and forming trigger data according to the data segments, and generating a trigger signal by using the trigger data to trigger. According to the method and the device, the trigger signal is generated according to the I2S signal, so that the trigger event occurs after external triggering, the application limitation that the conventional oscilloscope cannot utilize the I2S signal for real-time triggering is overcome, the trigger function of the oscilloscope is expanded, and an engineer can be helped to analyze the problem quickly and in multiple angles.
Description
Technical Field
The invention relates to the technical field of oscilloscopes, in particular to a triggering method based on an I2S signal and an oscilloscope.
Background
The rapid development and wide application of large-scale integrated circuits greatly increase the complexity of digital systems, which leads to more and more complex design, development, detection and fault diagnosis, and in practical application, people usually want to perform visual analysis on the signal quantity on a line through the trigger function of an oscilloscope, but the traditional limited trigger measurement method can not meet the requirements of users.
The oscilloscope can stably display repeated periodic signals and can display signals with specific characteristics, and the trigger sensitivity directly determines the capturing and displaying capacity of the oscilloscope on weak signals. Most of the existing trigger systems of digital oscilloscopes are analog trigger systems, and the comparator responsible for detecting the signal level uses an analog comparator for processing the original measurement signal. On one hand, the stable triggering of the noise signal requires a triggering system to realize a certain delay around a triggering threshold, so that the analog comparator must adopt a feedback technology to compensate to obtain a stably displayed waveform; on the other hand, the larger hysteresis of the small-amplitude signal limits the sensitivity of the trigger system, so that the small-amplitude signal cannot stably trigger the display.
The current generation oscilloscopes not only need to ensure the sensitivity of the trigger system, but also have requirements on the richness of the trigger function. The application trend of audio interface digitization is more and more applied in electronic products, I2S is a common digital audio interface at present, and is more common in audio decoders, audio DACs and bluetooth chips, and products designed by using the three types of chips are even more numerous, however, there is no extended application situation in oscilloscope trigger measurement by using I2S signals at present. The product needs to undergo complex debugging and testing in the period from design to volume production, the speed of using a testing instrument to locate problems directly influences the development progress of the product, and an oscilloscope serving as a general testing instrument must provide a flexible and good-use testing scheme to serve a wide range of engineers.
Disclosure of Invention
The invention mainly solves the technical problem of how to overcome the application limitation that the conventional oscilloscope cannot utilize an I2S signal for real-time triggering. In order to solve the technical problem, the application discloses a triggering method based on an I2S signal and an oscilloscope.
According to a first aspect, an embodiment provides a triggering method based on an I2S signal, the I2S signal including frame synchronization data, clock data, and audio data, the triggering method comprising the steps of: carrying out time sequence alignment on various types of data in the I2S signal to obtain an alignment signal; extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal; and forming trigger data according to a plurality of data fragments, and generating a trigger signal by using the trigger data to trigger.
The performing time sequence alignment on various types of data in the I2S signal to obtain an aligned signal includes: performing analog-to-digital conversion and filter shaping on the I2S signal to obtain frame synchronization data, clock data and audio data in the I2S signal; performing hysteresis processing on the data that is ahead of the frame synchronization data, the clock data, and the audio data to cause an edge formed by the frame synchronization data to align with a falling edge formed by the clock data in each period of the frame synchronization data; determining valid data bits in the audio data, aligning the audio data with the frame synchronization data using the most significant bits or the least significant bits; and forming a corresponding alignment signal according to the frame synchronization data, the clock data and the audio data after alignment.
The aligning the audio data with the frame synchronization data using the most significant bits or the least significant bits includes: under a preset left alignment mode, shifting the most significant bit in the audio data to the edge of the frame synchronization data, and beginning to align with a second clock period formed by the clock data and positioned after the edge; or, in a preset right alignment mode, the least significant bit in the audio data is shifted to the edge of the frame synchronization data, and the first clock period formed by the audio data and the clock data before the edge is aligned.
The extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal includes: acquiring left and right channel options, a valid bit start type, a sampling start bit, a sampling edge type and a sampling length required by extracting a data segment from preset frame configuration information; determining the effective level of frame synchronization data in the alignment signal according to the left and right channel options, and controlling the extraction of audio data in the alignment signal under the condition that the effective level is high level and/or low level; determining a start significant bit of the audio data in the alignment signal according to the start type of the significant bit, and controlling the extraction direction of the audio data in the alignment signal under the condition that the start significant bit is the most significant bit or the least significant bit; determining the start bit of the audio data in the alignment signal according to the sampling start bit, and controlling the audio data in the alignment signal to be extracted from the start bit; determining sampling edges of clock data in the alignment signals according to the types of the sampling edges, and accumulatively extracting the number of bits of audio data in the alignment signals when the sampling edges are rising edges or falling edges; controlling the data length for extracting the audio data in the alignment signal according to the sampling length; and receiving the audio data in the alignment signal by bit, thereby respectively acquiring the data segments of the audio data in the alignment signal in each period of the frame synchronization data in the alignment signal.
The forming of trigger data according to a plurality of the data segments, generating a trigger signal to trigger by using the trigger data, includes: framing the acquired one or more data segments to form trigger data; and generating a trigger signal when the trigger data meet a preset trigger condition, wherein the trigger signal is used for triggering an external trigger and then generating a trigger event.
The trigger condition is one of data trigger, mute trigger, glitch trigger, rising edge trigger, and falling edge trigger.
In a second aspect, in one embodiment, there is provided an oscilloscope, comprising: the device comprises a preprocessing unit, a signal processing unit and a signal processing unit, wherein the preprocessing unit is used for carrying out time sequence alignment on various types of data in an I2S signal and obtaining an aligned signal, and the I2S signal comprises frame synchronization data, clock data and audio data; the buffer unit is connected with the preprocessing unit and used for extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal and forming trigger data according to the plurality of data segments; the setting unit is connected with the preprocessing unit and the cache unit and is used for presetting alignment modes of various types of data in the I2S signal and presetting frame configuration information of the alignment signal; the trigger unit is connected with the cache unit and used for generating a trigger signal by utilizing the trigger data; and the output unit is connected with the trigger unit and used for outputting a trigger signal to trigger a trigger event after external triggering.
The preprocessing unit comprises an analog-to-digital converter, a comparator and a signal alignment module; the analog-to-digital converter and the comparator are respectively used for performing analog-to-digital conversion and filter shaping on the I2S signal and outputting frame synchronization data, clock data and audio data in the I2S signal; the signal alignment module is connected with the comparator and used for performing hysteresis processing on the data which is ahead of the frame synchronization data, the clock data and the audio data so as to align the edge formed by the frame synchronization data with the falling edge formed by the clock data in each period of the frame synchronization data; and for determining valid data bits in the audio data, the audio data being aligned with the frame synchronization data using either the most significant bits or the least significant bits; and the alignment device is used for forming a corresponding alignment signal according to the frame synchronization data, the clock data and the audio data after alignment.
The alignment mode preset by the setting unit comprises a left alignment mode and a right alignment mode, and the frame configuration information preset by the setting unit comprises left and right channel options, a valid bit start type, a sampling start bit, a sampling edge type and a sampling length; the signal alignment module shifts the most significant bit in the audio data to the edge of the frame synchronization data in a left alignment mode and starts to align with a second clock period formed on the clock data after the edge; the signal alignment module shifts the least significant bit in the audio data to an edge of the frame synchronization data in a right alignment mode and starts to align with a first clock period formed on the clock data after the edge.
The buffer unit is used for determining the effective level of frame synchronization data in the alignment signal according to the left and right channel options when extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal, and controlling the extraction of the audio data in the alignment signal under the condition that the effective level is high level and/or low level; the alignment circuit is used for determining the initial valid bit of the audio data in the alignment signal according to the valid bit initial type, and controlling the extraction direction of the audio data in the alignment signal under the condition that the initial valid bit is the most valid bit or the least valid bit; the audio data alignment circuit is used for determining a start bit of the audio data in the alignment signal according to the sampling start bit and controlling the audio data in the alignment signal to be extracted from the start bit; the sampling edge is used for determining the sampling edge of the clock data in the alignment signal according to the type of the sampling edge, and the number of bits of the audio data in the alignment signal is extracted in an accumulated mode when the sampling edge is a rising edge or a falling edge; the data length used for extracting the audio data in the alignment signal is controlled according to the sampling length; and receiving the audio data in the alignment signal by bit, thereby respectively acquiring the data segments of the audio data in the alignment signal in each period of the frame synchronization data in the alignment signal.
According to a third aspect, an embodiment provides a computer-readable storage medium comprising a program executable by a processor to implement the triggering method described in the first aspect above.
The beneficial effect of this application is:
according to the triggering method and the oscilloscope based on the I2S signal, the triggering method comprises the following steps: performing time sequence alignment on various types of data in an I2S signal to obtain an aligned signal, wherein the I2S signal comprises frame synchronization data, clock data and audio data; extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal; and forming trigger data according to the data segments, and generating a trigger signal by using the trigger data to trigger. On the first hand, the trigger signal is generated according to the I2S signal, so that the trigger event occurs after external triggering, the application limitation that the conventional oscilloscope cannot utilize the I2S signal for real-time triggering is overcome, the trigger function of the oscilloscope is expanded, and an engineer can be helped to analyze the problem quickly and in multiple angles; in the second aspect, by extracting the alignment signal through the preset frame configuration information, the data segment of interest to the user in the I2S signal can be extracted to form the trigger data, so as to generate the trigger signal through the trigger output; in the third aspect, the I2S signal is subjected to timing alignment processing before the I2S signal is extracted, so that the signal skew situation can be avoided, and the data segment extraction processing is favorably carried out on the aligned signal according to the sampling edge of the aligned signal, so that a more ideal data segment in the audio data is obtained; in the fourth aspect, when the data segments of the alignment signals are extracted, an extra baud rate sampling circuit is not needed to sample the audio data, and only the clock edge needs to be detected, so that the extraction operation is simpler and more efficient, the hardware resources of the oscilloscope are saved, and the application cost can be reduced; in a fifth aspect, the oscilloscope in the application comprises a preprocessing unit, a buffer unit, a setting unit, a triggering unit and an output unit, wherein the setting unit is used for guiding the preprocessing unit to execute time sequence alignment processing, and guiding the buffer unit to perform bit receiving and data fragment framing processing, so that the triggering function of the oscilloscope is enriched, the compact and reasonable layout on the structure is also brought, and the oscilloscope has higher practical value.
Drawings
FIG. 1 is a flow chart of a triggering method based on the I2S signal in the present application;
FIG. 2 is a flow chart of obtaining an alignment signal by timing alignment;
FIG. 3 is a flow chart of extracting a plurality of data segments associated with audio data;
FIG. 4 is a flow chart for forming trigger data from data segments;
FIG. 5 is a schematic diagram of the timing alignment of various types of data in the I2S signal;
FIG. 6 is a schematic diagram of the data segment extraction of audio data in an alignment signal;
fig. 7 is a schematic structural diagram of an oscilloscope in the present application.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
For clear understanding of the technical contents of the present application, some technical terms will be described herein.
The I2S signal (Inter-IC Sound signal) is a bus standard established by philips for audio data transmission between digital audio devices (e.g., CD players, digital Sound processors, digital television Sound systems). The method avoids distortion induced by time difference by a design mode of separating a data signal and a clock signal. The standard bus cable for transmitting the I2S signal is composed of 3 serial conductors: 1 is a time division multiplexing data line, and 1 is a word selection line; the 1 root is the clock line. Then, the I2S signal mainly includes a frame clock signal (LRCK), a serial clock signal (BCK or SCLK), and a serial DATA signal (DATA or SDATA); the LRCK is used for switching data of left and right channels, wherein the high level (namely '1') represents transmission of right channel data, the low level (namely '0') represents transmission of left channel data, and the frequency of the LRCK is equal to the sampling frequency; wherein each pulse of the BCK corresponds to each bit of data of the digital audio, and the frequency =2 × sampling frequency × sampling bit depth of the BCK; DATA is audio DATA represented by two's complement, and is usually transmitted from the most significant bit MSB to the least significant bit LSB in sequence.
The Most Significant Bit (Most Significant Bit, abbreviated MSB) is the highest weighted Bit in the binary number, similar to the leftmost Bit in the decimal number; the Least Significant Bit (LSB) is the position in the binary number representing the minimum value. Typically, the MSB is located at the leftmost side of the binary number and the LSB is located at the rightmost side of the binary number. For example, a binary number 0' b1100, which represents a decimal number 12 if the 1 st bit after the letter b is the MSB; if the 1 st bit after the letter b is the LSB, the binary number represents the decimal number 3.
The technical solution of the present application will be described in detail with reference to the following examples.
The first embodiment,
Referring to fig. 1, the present application discloses a triggering method based on I2S signal, which mainly includes steps S100-S300, which are described below.
And step S100, carrying out time sequence alignment on various types of data in the I2S signal to obtain an alignment signal. The I2S signal here includes frame synchronization DATA, clock DATA and audio DATA, wherein the frame synchronization DATA is corresponding to LRCK after the I2S signal is digitized, the clock DATA is corresponding to BCK after the I2S signal is digitized, and the audio DATA is corresponding to DATA after the I2S signal is digitized.
It should be noted that, when an analog audio I2S signal is input into an oscilloscope, the attenuation of the signal will be different due to different lengths of signal paths, and finally, three signals cannot be aligned in time sequence, which may cause signal skew. Therefore, after converting the analog audio into a digitized form of the I2S signal, it is necessary to perform an alignment operation on the frame synchronization data, the clock data, and the audio data in the I2S signal, to ensure consistency of signal edges, and to ensure consistency with standard timing.
Step S200, extracting the alignment signal according to the preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal.
It should be noted that the audio data in the alignment signal is digitized audio data obtained at a certain sampling frequency, and includes a large amount of audio information, but not all audio data are suitable for performing the triggering operation, so that here, a part of data in the audio data is extracted based on the audio information that a user is interested in, and the extracted data segment is used for the subsequent triggering operation. For example, a data segment of the audio data in the alignment signal may be acquired in each period of the frame synchronization data in the alignment signal, and each data segment is composed of a number of values in bits (bits).
It should be noted that the frame configuration information is used to limit the data segment extraction operation, and the data segment of interest to the user can be extracted by selecting parameters such as left and right channels, start type of significant bits (MSB or LSB), sample edge type, system bit width, start bit, sample data length, and the like.
Step S300, forming trigger data according to the plurality of data segments, and generating a trigger signal by using the trigger data to trigger.
It should be noted that, since a plurality of data segments are all in the form of bit streams, one or more data segments may be framed to construct trigger data in the form of frame data, a trigger signal is generated when the trigger data meets a specified trigger requirement, and the generated trigger signal may be used to trigger generation of a trigger event, such as a trigger event for data storage, start scanning, waveform detection, exception marking, and the like.
In this embodiment, referring to fig. 2, the step S100 mentioned above relates to various processing procedures for data timing alignment, and may specifically include steps S110 to S140, which are respectively described as follows.
Step S110, perform analog-to-digital conversion and filter shaping on the I2S signal to obtain frame synchronization data, clock data, and audio data in the I2S signal.
For an I2S signal in an analog audio form, which is transmitted by three signals (LRCK, BCK, and DATA) together, ADC conversion and filter shaping are required to be performed on each signal, and interference signals and abnormal DATA are filtered out, so that a digital form of the I2S signal is obtained, that is, frame synchronization DATA, clock DATA, and audio DATA in the I2S signal are obtained.
In step S120, the leading data among the frame synchronization data, the clock data, and the audio data is subjected to hysteresis processing to align an edge formed by the frame synchronization data with a falling edge formed by the clock data in each period of the frame synchronization data.
Since the path lengths of the three signals are different when the I2S signal passes through the analog-to-digital conversion circuit and the filter shaping circuit, the data that should be output at the same time has the data output by one path that leads the data output by the other path, and at this time, the data output in the leading path needs to be delayed, the output timing of the data is reduced, and the output timing is synchronized with the output timing of the data of the other path.
For example, the I2S signal illustrated in fig. 5, LRCK, BCK, and DATA correspond to frame synchronization DATA, clock DATA, and audio DATA, respectively, the low state of LRCK representing the left channel L and the high state representing the right channel R, and for the sake of understanding, the various types of DATA are represented using digital waveforms. In the case of normal alignment, the edges (falling edge and rising edge) of the frame synchronization data are kept aligned with the falling edge of the clock data, and the respective bits in the audio data are aligned one-to-one with the respective clock cycles in the clock data. If the frame synchronization data is advanced, the edge of the frame synchronization data will exceed the falling edge of the clock data, possibly by more than a time within one clock cycle, and at this time, the output timing of the frame synchronization data needs to be reduced, and the edge of the frame synchronization data is pulled back to be aligned with the falling edge of the clock cycle.
In step S130, valid data bits in the audio data are determined, and the audio data and the frame synchronization data are aligned using the most significant bits or the least significant bits.
It should be noted that the length of the audio data word is often relatively constant in each half period of the frame synchronization data, such as 24 bits as illustrated by bit 1 to bit 24 in the audio data in fig. 5. The leftmost bit 1 represents the most significant bit MSB and the rightmost bit 24 represents the least significant bit LSB.
In a specific embodiment, the alignment operation of the audio data and the frame synchronization data may be performed in a preset left alignment mode or a preset right alignment mode. The alignment mode may be preset by a user, for example, the alignment mode is selected on a display interface or an interactive window UI of the oscilloscope, so that a parameter value of the mode configuration is written into a register, and a parameter value is read from the register to obtain one of the left alignment mode and the right alignment mode, for example, the configuration item Variant in table 1 below.
If in the left alignment mode, the Most Significant Bit (MSB) of the audio data may be shifted to the edge of the frame synchronization data, and the alignment begins with the second clock cycle after the edge formed by the clock data, resulting in the alignment effect of the LRCK and BCK in fig. 5.
If in the right alignment mode, the Least Significant Bit (LSB) of the audio DATA may be shifted to the edge of the frame sync DATA and aligned with the beginning of the first clock cycle formed by the clock DATA before the edge, i.e., DATA is shifted to the right in fig. 5 so that the LSB is aligned with the rising edge of LRCK.
In step S140, a corresponding alignment signal is formed according to the frame synchronization data, the clock data, and the audio data after alignment.
It should be noted that after the frame synchronization data, the clock data and the audio data are aligned, the edge of the frame synchronization data is consistent with the falling edge of the clock data, and each bit of the audio data is consistent with each clock period of the clock data; and, the most significant bit of the audio data is aligned to the left with respect to the second clock period after the frame sync data edge, or the least significant bit of the audio data is aligned to the right with respect to the first clock period before the frame sync data edge.
In the present embodiment, referring to fig. 3, the above step S200 mainly relates to the operation of extracting data segments from the alignment signals, and may include steps S210 to S270, which are respectively described as follows.
Step S210, obtaining left and right channel options, valid bit start types, sampling start bits, sampling edge types, and sampling lengths required by extracting data segments from the preset frame configuration information.
It should be noted that the frame configuration information may be preset by a user, for example, each parameter in the frame configuration information is selected or set on a display interface or an interactive window UI of an oscilloscope, so that a value of each parameter is written into a register, and the frame configuration information can be obtained by reading the parameter from the register. For example, the specific contents of the frame configuration information may refer to table 1 below.
TABLE 1 list of configuration items and their meanings
Step S220, determining the effective level of the frame synchronization data in the alignment signal according to the left and right channel options, and controlling the audio data in the alignment signal to be extracted when the effective level is a high level and/or a low level.
It should be noted that, because each period of the frame synchronization data is composed of a high level and a low level, if the low level represents the left channel and the high level represents the right channel, the low level of the left channel is active, or the high level of the right channel is active, or both the high and low levels of the left and right channels are active at the same time, which can be determined by the left and right channel options. Only when the active level is determined, the audio data corresponding to the active level can be extracted.
Step S230, determining a start significant bit of the audio data in the alignment signal according to the start type of the significant bit, and controlling an extraction direction of the audio data in the alignment signal when the start significant bit is a most significant bit or a least significant bit.
It should be noted that, for example, in the audio data illustrated in fig. 6, in the case of different start significant bits (MSB or LSB), the reading direction of the bits is different, and thus the read values are also different. Taking the MSB as an example of the starting significant bit, the bits from left to right are bit 1 to bit 32, so that the data segment is extracted in the left-to-right extraction direction to perform the value reading operation on the bits.
Step S240, determining a start bit of the audio data in the alignment signal according to the sampling start bit, and controlling to extract the audio data in the alignment signal from the start bit. For example, bit 5 in fig. 6 may be determined as the start bit.
And step S250, determining the sampling edge of the clock data in the alignment signal according to the type of the sampling edge, and accumulating and extracting the number of bits of the audio data in the alignment signal when the sampling edge is a rising edge or a falling edge.
It should be noted that, since each bit of the audio data corresponds to each period of the clock data, the number of bits of the audio data in the alignment signal can be obtained by counting once when the rising edge (or the falling edge) of the clock data arrives, so as to count the number of bits extracted. The purpose of accumulating the number of extracted bits is to ensure that the extracted bits can accurately meet the requirement of the sampling length. The method of accumulating the count may be to generate a bit counter from an edge of the clock data, and to perform a loop count by resetting the bit counter every time the left and right channels change.
Step S260, controlling the data length for extracting the audio data in the alignment signal according to the sampling length. For example, in fig. 6, if the sampling length is set to 23 bits, the values of 23 bits can be extracted from the bit 5 corresponding to the start bit until being cut off at the bit 27 corresponding to the end bit.
Step S270, receiving the audio data in the alignment signal by bit, so as to obtain the data segments of the audio data in the alignment signal in each period of the frame synchronization data in the alignment signal.
It should be noted that, a group of audio data is correspondingly formed in each half cycle of the frame synchronization data, the number of bits in the group of audio data is equivalent to the system bit width (Total data bit), and is determined by the ADC conversion process of the analog audio, for example, 32 bits in fig. 6. The bit width of the system can also be preset by a user and then realized in the ADC conversion process of analog audio. Normally, the sampling length cannot exceed the system bit width, otherwise, normal data fragment extraction operation cannot be performed.
It should be noted that, in each period of the frame synchronization data in the alignment signal, a data segment can be correspondingly extracted from the audio data, and each data segment is received with bits. Because each data segment comprises numerical values on a plurality of continuous bits in the audio data, the numerical values in the data segment can be received one by one according to the order of the bits, and the implementation effect of bit receiving is formed, thereby ensuring the accuracy of the data receiving process and providing convenience for the subsequent framing operation.
In the present embodiment, referring to fig. 4, the step S300 may include steps S310 to S320, which are described as follows.
Step S310, framing the acquired one or more data segments to form trigger data.
It should be noted that after receiving bits of each data segment that arrives successively, a bit stream is formed, and in order to meet the requirement of data triggering, the bit stream is further formed into a data frame, and then data triggering is performed. In order to enable the subsequent trigger unit to correctly receive and check the transmitted frame, the sender must encapsulate the bit stream delivered by the network layer into frames according to a certain rule to implement the operation process of framing, the trigger data can be formed after framing, and the head and tail of the trigger data have framing marks, so that the trigger unit can identify the start and end of the frame after receiving the trigger data.
In one embodiment, each data segment may be grouped into a frame, and the trigger data formed thereby reaches the trigger unit one by one, so that the trigger unit can recognize the frame and receive the trigger data smoothly.
In step S320, a trigger signal is generated when the trigger data meets a preset trigger condition, and the trigger signal is used for triggering an external trigger and then generating a trigger event.
The trigger condition in this embodiment is one of data trigger, mute trigger, glitch trigger, rising edge trigger, and falling edge trigger. Wherein, the data trigger (data trigger) is that the oscilloscope searches a piece of data input by a user from a received I2S signal and triggers when a condition is met; mute trigger (mute trigger) is that a user configures a mute threshold and a frame number, and when data continuously received by the oscilloscope is less than the threshold and the frame number is more than or equal to the frame number, the mute trigger is triggered at a position where a condition is met; the sound breaking trigger (clip trigger) is that a user configures a sound breaking threshold and a frame number, and is triggered at a position meeting a condition when data continuously received by the oscilloscope is greater than the threshold and the frame number is greater than or equal to the frame number; the glitch trigger (glitch trigger) is that a user configures a glitch threshold, and when the difference between two continuous data is larger than the threshold, the glitch trigger is triggered at a position meeting a condition; the rising edge trigger (rising trigger) is triggered when the oscilloscope searches that the data waveform is at the rising edge and meets a configured rising edge threshold value and meets the condition position; a falling edge trigger (falling trigger) is a trigger at the point where the oscilloscope searches for a data waveform to be on a falling edge and meets the configured falling edge threshold.
Those skilled in the art will appreciate that the triggering method based on the I2S signal disclosed in the present embodiment may achieve the following technical advantages during the application process: (1) the trigger signal is generated according to the I2S signal, so that a trigger event occurs after external triggering, the application limitation that the conventional oscilloscope cannot utilize the I2S signal for real-time triggering is overcome, the trigger function of the oscilloscope is expanded, and an engineer can be helped to analyze the problem quickly and in multiple angles; (2) extracting the alignment signal through preset frame configuration information, and extracting a data segment which is interested in a user in the I2S signal to form trigger data so as to generate a trigger signal through a trigger output; (3) the I2S signal is subjected to time sequence alignment processing before the I2S signal is extracted, so that the signal skew situation can be avoided, and the data segment extraction processing is favorably carried out on the aligned signal according to the sampling edge of the aligned signal, so that a more ideal data segment in the audio data is obtained.
Example II,
Referring to fig. 7, the present application discloses an oscilloscope, which mainly includes a preprocessing unit 11, a buffer unit 12, a setting unit 13, a triggering unit 14, and an output unit 15, which are described below.
The preprocessing unit 11 is configured to perform timing alignment on various types of data in the I2S signal and obtain an alignment signal; the I2S signal here includes frame synchronization data, clock data, and audio data. The preprocessing unit 11 can perform a timing alignment operation on various types of data in the I2S signal by using a preset left alignment mode or a preset right alignment mode.
The buffer unit 12 is connected to the preprocessing unit 11, and is configured to extract the alignment signal according to preset frame configuration information, obtain a plurality of data segments related to the audio data in the alignment signal, and form trigger data according to the plurality of data segments. Since the plurality of data segments are all in the form of bit streams, the buffer unit 12 may perform framing on one or more data segments, so as to construct trigger data in the form of frame data, which facilitates the trigger unit 14 to receive the trigger data.
It should be noted that the buffer unit 12 may respectively obtain data segments of the audio data in the alignment signal in each period of the frame synchronization data in the alignment signal, where each data segment is composed of a plurality of values in units of bits (bits). In addition, the frame configuration information is used to limit the data segment extraction operation, and the data segment of interest to the user can be extracted by selecting parameters such as left and right channels, start type of significant bit (MSB or LSB), sample edge type, system bit width, start bit, length of sample data, and the like.
The setting unit 13 is connected to the preprocessing unit 11 and the buffer unit 12, and is configured to preset alignment modes of various types of data in the I2S signal and preset frame configuration information of the alignment signal. The alignment mode may include a left alignment mode and a right alignment mode, and the frame configuration information may include left and right channel options, a valid bit start type, a sampling start bit, a sampling edge type, and a sampling length, which will be described in detail below.
The trigger unit 14 is connected to the buffer unit 12 for generating a trigger signal using the trigger data. The trigger unit 14 may compare the trigger data with a preset trigger condition, so as to generate a trigger signal when the trigger condition is satisfied. The trigger condition here is one of a data trigger, a mute trigger, a glitch trigger, a rising edge trigger, and a falling edge trigger.
The output unit 15 is connected to the trigger unit 14, and is configured to output a trigger signal to trigger an external trigger and then generate a trigger event. The output unit 15 may output the trigger signal to a hardware device such as a memory, a processor, a detection circuit, a counting circuit, etc., so that the generated trigger signal may be used to trigger generation of a trigger event, such as a trigger event for data storage, start scanning, waveform detection, exception marking, etc.
In the present embodiment, referring to fig. 7, the preprocessing unit 11 may include an analog-to-digital converter 111, a comparator 112, and a signal alignment module 113.
The analog-to-digital converter 111 and the comparator 112 are respectively configured to perform analog-to-digital conversion and filter shaping on the I2S signal in analog audio form, and output frame synchronization data, clock data, and audio data in the I2S signal in digitized form.
The signal alignment module 113 is connected to the comparator 112, and configured to perform hysteresis processing on the preceding data among the frame synchronization data, the clock data, and the audio data, so as to align an edge formed by the frame synchronization data with a falling edge formed by the clock data in each period of the frame synchronization data; the signal alignment module 113 is further configured to determine valid data bits in the audio data, and align the audio data with the frame synchronization data using the most significant bits or the least significant bits; and a signal alignment module 113 for forming a corresponding alignment signal according to the frame synchronization data, the clock data and the audio data after alignment.
In this embodiment, referring to fig. 7, the buffer unit 12 may include a receiving module 121 and a framing module 122.
The receiving module 121 is configured to receive bits of the audio data in the alignment signal, so as to obtain data segments of the audio data in the alignment signal in each period of the frame synchronization data in the alignment signal. The framing module 122 is configured to frame the acquired one or more data segments to form trigger data.
In this embodiment, the alignment modes preset by the setting unit 13 include a left alignment mode and a right alignment mode, and the frame configuration information preset by the setting unit 13 includes left and right channel options, a valid bit start type, a sampling start bit, a sampling edge type, and a sampling length. Then, the preprocessing unit 11 may acquire the alignment mode information from the setting unit 13 to perform the corresponding timing alignment processing, and the buffer unit 12 may acquire the frame configuration information from the setting unit 13 to perform the corresponding data segment extraction processing.
In one embodiment, referring to fig. 7, the signal alignment module 113 in the pre-processing unit 11 shifts the most significant bit in the audio data to the edge of the frame synchronization data in the left alignment mode and starts to align with the second clock period formed on the clock data after the edge. In addition, the signal alignment module 113 may shift the least significant bit in the audio data to the edge of the frame synchronization data in the right alignment mode, and align with the first clock cycle formed on the clock data after the edge. As for the functions of the signal alignment module 113, reference may be made to steps S120 to S140 in the first embodiment, which are not described herein again.
In an embodiment, the receiving module 121 in the buffer unit 12 extracts the alignment signal according to the preset frame configuration information, so as to obtain a plurality of data segments related to the audio data in the alignment signal. The method specifically comprises the following steps: the receiving module 121 determines the effective level of the frame synchronization data in the alignment signal according to the left and right channel options, and controls to extract the audio data in the alignment signal when the effective level is a high level and/or a low level; the receiving module 121 determines a start significant bit of the audio data in the alignment signal according to the start type of the significant bit, and controls the extraction direction of the audio data in the alignment signal when the start significant bit is the most significant bit or the least significant bit; the receiving module 121 determines a start bit of the audio data in the alignment signal according to the sampling start bit, and controls to extract the audio data in the alignment signal from the start bit; the receiving module 121 determines a sampling edge of the clock data in the alignment signal according to the type of the sampling edge, and accumulates and extracts the number of bits of the audio data in the alignment signal when the sampling edge is a rising edge or a falling edge; the receiving module 121 controls the data length for extracting the audio data in the alignment signal according to the sampling length; after the above processing procedure, the receiving module 121 may perform bit reception on the audio data in the alignment signal, so as to obtain the data segment of the audio data in the alignment signal in each period of the frame synchronization data in the alignment signal. As for the functions of the buffer unit 12, reference may be made to steps S210 to S270 in the first embodiment, which are not described herein again.
In addition, in this embodiment, the oscilloscope further includes a processor 16 and a display 17, where the processor 16 may be a digital processing device such as a CPU, an MCU, etc., and is in communication with the setting unit 13, the triggering unit 14, and the output unit 15, and is configured to monitor the alignment mode and the frame configuration information configured in the setting unit 13, monitor the triggering condition in the triggering unit 14, and monitor the output process of the triggering signal of the output unit 15. The display 17 communicates with the processor 16 for forming an interactive configuration window (UI) and a real-time monitoring window. Then, the user can flexibly configure the corresponding alignment mode parameter and frame configuration information parameter for the setting unit 13 through the interactive configuration window on the display 17, and can also timely know the states of the I2S signal, the alignment signal, the trigger data and the trigger signal through the real-time monitoring window, so as to help the user timely know the operating condition of the oscilloscope in the trigger mode based on the I2S signal.
Those skilled in the art will appreciate that the oscilloscope disclosed in the present embodiment has the following technical advantages when in use: (1) when the data segments of the alignment signals are extracted, an extra baud rate sampling circuit is not needed to sample the audio data, and only the clock edge needs to be detected, so that the extraction operation is simpler and more efficient, the hardware resources of the oscilloscope are saved, and the application cost can be reduced; (2) the oscilloscope guides the preprocessing unit to execute time sequence alignment processing by using the setting unit, and guides the cache unit to receive bits and perform framing processing of data fragments, thereby enriching the trigger function of the oscilloscope, bringing compact and reasonable layout on the structure and having higher practical value.
Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by computer programs. When all or part of the functions of the above embodiments are implemented by a computer program, the program may be stored in a computer-readable storage medium, and the storage medium may include: a read only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to realize the above functions. For example, the program may be stored in a memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above may be implemented. In addition, when all or part of the functions in the above embodiments are implemented by a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and may be downloaded or copied to a memory of a local device, or may be version-updated in a system of the local device, and when the program in the memory is executed by a processor, all or part of the functions in the above embodiments may be implemented.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A triggering method based on an I2S signal, the I2S signal including frame synchronization data, clock data, and audio data, the triggering method comprising the steps of:
carrying out time sequence alignment on various types of data in the I2S signal to obtain an alignment signal;
extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal;
and forming trigger data according to a plurality of data fragments, and generating a trigger signal by using the trigger data to trigger.
2. The method of claim 1, wherein the performing timing alignment on the types of data in the I2S signal to obtain an aligned signal comprises:
performing analog-to-digital conversion and filter shaping on the I2S signal to obtain frame synchronization data, clock data and audio data in the I2S signal;
performing hysteresis processing on the data that is ahead of the frame synchronization data, the clock data, and the audio data to cause an edge formed by the frame synchronization data to align with a falling edge formed by the clock data in each period of the frame synchronization data;
determining valid data bits in the audio data, aligning the audio data with the frame synchronization data using the most significant bits or the least significant bits;
and forming a corresponding alignment signal according to the frame synchronization data, the clock data and the audio data after alignment.
3. The triggering method of claim 2, wherein said aligning the audio data with the frame synchronization data using the most significant bits or the least significant bits comprises:
under a preset left alignment mode, shifting the most significant bit in the audio data to the edge of the frame synchronization data, and beginning to align with a second clock period formed by the clock data and positioned after the edge;
or, in a preset right alignment mode, the least significant bit in the audio data is shifted to the edge of the frame synchronization data, and the first clock period formed by the audio data and the clock data before the edge is aligned.
4. The method of claim 2, wherein the extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal comprises:
acquiring left and right channel options, a valid bit start type, a sampling start bit, a sampling edge type and a sampling length required by extracting a data segment from preset frame configuration information;
determining the effective level of frame synchronization data in the alignment signal according to the left and right channel options, and controlling the extraction of audio data in the alignment signal under the condition that the effective level is high level and/or low level;
determining a start significant bit of the audio data in the alignment signal according to the start type of the significant bit, and controlling the extraction direction of the audio data in the alignment signal under the condition that the start significant bit is the most significant bit or the least significant bit;
determining the start bit of the audio data in the alignment signal according to the sampling start bit, and controlling the audio data in the alignment signal to be extracted from the start bit;
determining sampling edges of clock data in the alignment signals according to the types of the sampling edges, and accumulatively extracting the number of bits of audio data in the alignment signals when the sampling edges are rising edges or falling edges;
controlling the data length for extracting the audio data in the alignment signal according to the sampling length;
and receiving the audio data in the alignment signal by bit, thereby respectively acquiring the data segments of the audio data in the alignment signal in each period of the frame synchronization data in the alignment signal.
5. The triggering method of claim 4, wherein said forming triggering data from a plurality of said data segments, utilizing said triggering data to generate a triggering signal to trigger comprises:
framing the acquired one or more data segments to form trigger data;
and generating a trigger signal when the trigger data meet a preset trigger condition, wherein the trigger signal is used for triggering an external trigger and then generating a trigger event.
6. The triggering method of claim 5, wherein the triggering condition is one of a data trigger, a mute trigger, a glitch trigger, a rising edge trigger, and a falling edge trigger.
7. An oscilloscope, comprising:
the device comprises a preprocessing unit, a signal processing unit and a signal processing unit, wherein the preprocessing unit is used for carrying out time sequence alignment on various types of data in an I2S signal and obtaining an aligned signal, and the I2S signal comprises frame synchronization data, clock data and audio data;
the buffer unit is connected with the preprocessing unit and used for extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal and forming trigger data according to the plurality of data segments;
the setting unit is connected with the preprocessing unit and the cache unit and is used for presetting alignment modes of various types of data in the I2S signal and presetting frame configuration information of the alignment signal;
the trigger unit is connected with the cache unit and used for generating a trigger signal by utilizing the trigger data;
and the output unit is connected with the trigger unit and used for outputting a trigger signal to trigger a trigger event after external triggering.
8. The oscilloscope of claim 7, wherein the preprocessing unit comprises an analog-to-digital converter, a comparator, and a signal alignment module;
the analog-to-digital converter and the comparator are respectively used for performing analog-to-digital conversion and filter shaping on the I2S signal and outputting frame synchronization data, clock data and audio data in the I2S signal;
the signal alignment module is connected with the comparator and used for performing hysteresis processing on the data which is ahead of the frame synchronization data, the clock data and the audio data so as to align the edge formed by the frame synchronization data with the falling edge formed by the clock data in each period of the frame synchronization data; and for determining valid data bits in the audio data, the audio data being aligned with the frame synchronization data using either the most significant bits or the least significant bits; and the alignment device is used for forming a corresponding alignment signal according to the frame synchronization data, the clock data and the audio data after alignment.
9. The oscilloscope of claim 8, wherein the preset alignment modes of the setting unit comprise a left alignment mode and a right alignment mode, and the preset frame configuration information of the setting unit comprises left and right channel options, a valid bit start type, a sampling start bit, a sampling edge type and a sampling length;
the signal alignment module shifts the most significant bit in the audio data to the edge of the frame synchronization data in a left alignment mode and starts to align with a second clock period formed on the clock data after the edge; the signal alignment module shifts the least significant bit in the audio data to the edge of the frame synchronization data in a right alignment mode, and is aligned with the first clock period formed on the clock data after the edge;
the buffer unit is used for determining the effective level of frame synchronization data in the alignment signal according to the left and right channel options when extracting the alignment signal according to preset frame configuration information to obtain a plurality of data segments related to the audio data in the alignment signal, and controlling the extraction of the audio data in the alignment signal under the condition that the effective level is high level and/or low level; the alignment circuit is used for determining the initial valid bit of the audio data in the alignment signal according to the valid bit initial type, and controlling the extraction direction of the audio data in the alignment signal under the condition that the initial valid bit is the most valid bit or the least valid bit; the audio data alignment circuit is used for determining a start bit of the audio data in the alignment signal according to the sampling start bit and controlling the audio data in the alignment signal to be extracted from the start bit; the sampling edge is used for determining the sampling edge of the clock data in the alignment signal according to the type of the sampling edge, and the number of bits of the audio data in the alignment signal is extracted in an accumulated mode when the sampling edge is a rising edge or a falling edge; the data length used for extracting the audio data in the alignment signal is controlled according to the sampling length; and receiving the audio data in the alignment signal by bit, thereby respectively acquiring the data segments of the audio data in the alignment signal in each period of the frame synchronization data in the alignment signal.
10. A computer-readable storage medium, characterized by comprising a program executable by a processor to implement the triggering method of any one of claims 1-6.
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