CN209486159U - Simple and Easy Logic Tester based on oscillograph X-Y mode - Google Patents
Simple and Easy Logic Tester based on oscillograph X-Y mode Download PDFInfo
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- CN209486159U CN209486159U CN201822068105.7U CN201822068105U CN209486159U CN 209486159 U CN209486159 U CN 209486159U CN 201822068105 U CN201822068105 U CN 201822068105U CN 209486159 U CN209486159 U CN 209486159U
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Abstract
The utility model discloses a kind of Simple and Easy Logic Testers based on oscillograph X-Y mode, including control processing unit, display unit, signal scanning drive module and oscillograph, control processing unit and signal scanning drive module synchronizing clock signals, the display signal output end of control processing unit is connect with display unit, the control signal and sequential logic signal output end for controlling processing unit are connect with the signal input part of signal scanning drive module, and the signal output end of signal scanning drive module is connect with oscillograph.The channel that can be shown for oscillograph is few, it is difficult to which the problem of analyzing logical sequence completes the Simple and Easy Logic Tester based on oscillograph X-Y mode.Design mainly includes control unit, three display unit, scan driver module parts.By the communication and cooperation of intermodule, system can show simultaneously the 8 road logical sequence waveforms based on common synchronous signal in oscillograph, and realize the logic analyses functions such as triggering setting, status word reading.
Description
Technical field
The utility model relates to a kind of logic analyser more particularly to a kind of simple logics based on oscillograph X-Y mode
Analyzer.
Background technique
The X-Y mode of oscillograph is dynamic point-scan mode, and the channel X, Y respectively corresponds the X-axis and Y-axis of display, in display
Appearance is determined by the voltage that the channel X, Y is accessed.The logic analyser of design has access to oscillograph, utilizes the X-Y mode of oscillograph
The 8 road logical sequence signal of outside based on common synchronous is shown simultaneously.In order to indicate that conveniently, oscillograph can show one
Vertical line, for positioning and showing each logic state (status word).System can carry out triggering setting, status word to logical sequence
The operation such as reading.Control unit reads in the logical sequence of 8 road signals, and the scanning signal that export that treated and control signal are to sweeping
Retouch drive module.The signal that scan driver module is responsible for receive send oscilloscope display.Oscillograph cannot show, be difficult to show
Content (such as status word) by logic analyser liquid crystal display.
Utility model content
The purpose of this utility model is that solve the above-mentioned problems and provides a kind of letter based on oscillograph X-Y mode
Easy logic analyser.
The utility model achieves the above object through the following technical schemes:
The utility model includes control processing unit, display unit, signal scanning drive module and oscillograph, the control
Processing unit and the signal scanning drive module synchronizing clock signals, it is described control processing unit display signal output end with
The display unit connection, the control signal and sequential logic signal output end of the control processing unit and the signal scanning
The signal input part of drive module connects, and the signal output end of the signal scanning drive module is connect with the oscillograph.
Further, the signal scanning drive module passes through X passage scanning and control circuit and Y Channel scan and control electricity
Road is connect with the oscillograph.
The utility model has the beneficial effects that:
The utility model is a kind of Simple and Easy Logic Tester based on oscillograph X-Y mode, compared with prior art, this reality
Screen is set to show the logical sequence waveform of multichannel using existing oscillograph X-Y mode with novel logic analyser.
Logic analyser can complete the functions such as trigger word setting, trigger point selection, logic state reading.It is demonstrated experimentally that system is defeated
Enter operational excellence in the case where the easily-testing logical sequence waveform of 8 channels, 100kHz.The system can use oscillograph realization
The basic function of logic analyser is to complete sequential logic analysis in the case where no logic analyser and consideration low cost
Feasible solution.
Detailed description of the invention
Fig. 1 is the overall system diagram of the utility model；
Fig. 2 is the sawtooth wave generating circuit of the utility model；
Fig. 3 is the X passage signal selecting circuit of the utility model；
Fig. 4 is the Y channel signal selection circuit of the utility model；
Fig. 5 is the trigger point setting procedure of the utility model；
Fig. 6 is that the X-axis of the utility model shows length Auto-matching process；
Fig. 7 is the single-chip microcontroller two machine communication framework of the utility model；
Fig. 8 is the communication data frame structure of the utility model.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawing:
The utility model includes control processing unit, display unit, signal scanning drive module and oscillograph, the control
Processing unit and the signal scanning drive module synchronizing clock signals, it is described control processing unit display signal output end with
The display unit connection, the control signal and sequential logic signal output end of the control processing unit and the signal scanning
The signal input part of drive module connects, and the signal output end of the signal scanning drive module is connect with the oscillograph.
Further, the signal scanning drive module passes through X passage scanning and control circuit and Y Channel scan and control electricity
Road is connect with the oscillograph.
The X-Y mode of oscillograph is dynamic point-scan mode, and the channel X, Y respectively corresponds the X-axis and Y-axis of display, in display
Appearance is determined by the voltage that the channel X, Y is accessed.The logic analyser of design has access to oscillograph, utilizes the X-Y mode of oscillograph
The 8 road logical sequence signal of outside based on common synchronous is shown simultaneously.In order to indicate that conveniently, oscillograph can show one
Vertical line, for positioning and showing each logic state (status word).System can carry out triggering setting, status word to logical sequence
The operation such as reading.Control unit reads in the logical sequence of 8 road signals, and the scanning signal that export that treated and control signal are to sweeping
Retouch drive module.The signal that scan driver module is responsible for receive send oscilloscope display.Oscillograph cannot show, be difficult to show
Content by logic analyser liquid crystal display, including clock frequency, triggering state, trigger word, status word etc..Provide liquid crystal
Behind interface, the display content of entire product is not only enriched, user's man-machine interaction experience is also improved.
Logic analyser is mainly made of control processing unit, display unit and signal scanning drive module.Due to logic
The waveform of analyzer shows that content is more, and existing resource can be integrated and be made full use of to the scheme of oscilloscope display, avoid using price
Expensive large-scale TFT display screen.Therefore, system is using oscillograph as basic display unit (see Fig. 1).Synchronizing clock signals clock
As working standard, need to be introduced into main control unit and oscilloscope signal scan driver module.Control processing unit
What is be all made of with display unit is macrocrystalline science and technology STC8 single-chip microcontroller.More, the applicable occasion of the series model function is wide [4], can
Meet system requirements.Control processing unit includes that key is read, sequential logic input and output and turntable driving control, and and is shown
Show unit communication.Display unit mainly includes liquid crystal display circuit, key circuit and LED indicating circuit.
The triggering of scanning signal and generation circuit:
X passage needs to generate an oblique ascension sawtooth wave, the scan channel signal as oscillograph.The signal oblique ascension curve is wanted
Straight, trailing edge edge wants precipitous.In this way, the figure that scope sweep goes out can be uniform accurate.Meanwhile sweeping the phase of screen signal
Position needs strictly with clock clock phase alignment screen signal can just stablized.Therefore, system devises one and has phase
Circuit occurs for the sawtooth signal of synchronous triggering, as shown in Figure 2.
Circuit utilizes the charge and discharge to capacitor C1 to generate sawtooth wave.D1, R1, Q1 constitute constant-current charging circuit, improve whole
The linearity of body sawtooth wave.Voltage U due to passing through the clamping action (pressure stabilizing tube voltage Uz) of voltage-stabiliser tube D1, on R1R1=UZ-
0.7.Therefore it is similar to by the electric current IR1 of R1 to the electric current i of capacitor charging.As long as voltage-stabiliser tube UZ is fixed, resistance R1 is fixed, fill
Electric current is just fixed, and guarantees the linearity of charging curve.
The differential circuit for passing through C2, R2 composition from the fractional frequency signal of clock synchronised clock, edge signal is shaped to
Sharp pulse signal.Due to only utilizing positive pulse (positive edge) using circuit, so the period of pulse signal and synchronous clock frequency dividing
The period of signal is consistent.Sharp pulse further pass through U1 compare, shaping so that need terminate charging when, signal can be touched reliably
Turn-on transistor Q2 is sent out, capacitor is allowed to discharge.The fall of the width of electric discharge, that is, sharp pulse span and sawtooth wave.Due to micro-
The sharp pulse width of sub-signal is narrow, therefore is capable of forming sharp sawtooth wave failing edge jump.
X passage scanning signal control circuit:
In general the signal of X passage is sawtooth wave screen scanning signal.But when showing vertical line, the signal of X passage
It does not need to scan, but determines a d. c. voltage signal for vertical line position (signal is provided by single-chip microcontroller).System is not according to
Gate unlike signal to X passage with situation (see Fig. 3).
In Fig. 3, single-chip microcontroller generates pwm signal, and passes through RC filter shape, can by adjusting the duty ratio of PWM waveform
To adjust required d. c. voltage signal size.The signal for recently entering X passage determines by alternative analog switch, and by scanning
Channel counter control.When scanning conventional channel, the road A sawtooth wave is accessed；When showing vertical line, the access road B PWM voltage is adjusted
Signal.
Y Channel scan signal control circuit:
Logical sequence signal is shown in Y-axis.It is different according to the channel of the logical sequence of display, in order to keep each waveform not mutual
Mutually conflict, interference, the display position of each channel, amplitude are had nothing in common with each other.By taking 8 channels as an example, when each channel switches
Primitive logic clock signal and original levels signal are superimposed using adder.Such as Fig. 4.In figure, U2 is responsible for the meter of multichannel switching
Number distribution, U3 is multiway analog switch, switches each channel original levels and vertical line signal according to distribution signal is counted.Work as counting
When being switched to vertical line channel, vertical line scanning signal is accessed.Here vertical line scanning signal is introduced by fractional frequency signal.Single-chip microcontroller is every
A channel provides original levels, which gives after being filtered by pwm signal RC.The processed logical sequence of single-chip microcontroller passes through
It is superimposed with the output of U3 by adder U6 after R14 and R15 compression decaying, final signal is sent into the channel Y and is shown.
The control function of single-chip microcontroller:
Logic analyser needs to handle the logical sequence of high speed, it is therefore desirable to the processing chip of high speed, such as STM32, FPGA
Deng [5] [6], the single-chip microcontroller that this system is applied to is STC ultrahigh speed 1T single-chip microcontroller, and price is low, performance is high, can satisfy and simply patrols
Collect the demand of analyzer.
The control of X-axis screen scanning clock
The X-Y mode of oscillograph is different from Y-T mode, does not have T time axis.Therefore, if the logic real training analyzer of design
Using X-axis as the time shaft of logical sequence, X-axis screen scanning clock has to have corresponding consistent pass with synchronizing clock signals
System.The X-axis screen scanning clock signal of system is obtained by the frequency dividing of synchronised clock, and the logical sequence waveform that such screen is shown is just
It can stablize.Meanwhile screen scanning clock signal is also channel switching, vertical line scanning provides benchmark.Therefore, screen scanning clock is believed
Number change while can also change the relevant informations such as the display cycle number of logical sequence waveform.
The reading and processing of logical sequence
Sequential logic signal is stored and interacted using display buffer.When single-chip microcontroller is responsible for reading the logic of multichannel
The logic state in each synchronised clock period is stored into display buffer, and real-time update by sequence.The depth of display buffer according to
Depending on the manifest cycle length of user setting, channel number.For example, if 1 complete sequential logic period is 8 clock weeks
Phase, and system will show the logical signal of 8 channel, 2 timing cycles, then the display buffer of 16 bytes will be opened up.Display
Buffer area is the memory space of a ring structure.When logic state storage depth alreadys exceed buffer length, automatically from
1st byte of buffer area stores.
The setting of trigger word and the selection of trigger point
System can configure logical triggering word.When logical AND trigger word when channel is consistent, all channels are intercepted and captured and shown
Logical sequence.Meanwhile the triggering word state can choose " starting to trigger ", " midpoint triggering ", " end triggering " Three models.
Three kinds of triggering modes refer respectively to left side, intermediate or right side of the trigger word status display captured in screen.
The content and oscilloscope display content of display buffer correspond, but transmission and the screen scanning letter of logical sequence
Number not necessarily it is aligned initial phase.Therefore, scanning sawtooth signal is shaped as impulse wave and introduces singlechip interruption (such as Fig. 5),
The initial phase for obtaining screen scanning, starts counting synchronised clock from initial phase, makes phase alignment.System finds satisfaction triggering
The synchronised clock count value of the logic state of word deviates the trigger word logic state in the position of display buffer according to count value
It sets, the display position of triggering word state can be adjusted.
Fixed X-axis shows length
The supply voltage of system is 5V, and in general, matching oscillograph X-axis is set as 500mV/div, observation effect
Fruit is relatively good.The display length of X-axis is determined by the capacitor charging voltage of " generation circuit of scanning signals ".According to fig. 2, capacitor fills
Piezoelectric voltage
Wherein i is charging current, and t is the charging time, and C is charging capacitor capacity.In the case where the charging time is fixed, adjust
Whole variable resistance R1, so that it may adjust sawtooth wave amplitude.It, can also be with the display of Auto-matching (fixation) X-axis in addition to manually adjusting
Length.No matter how synchronised clock changes, the crest voltage for scanning sawtooth signal requires to be a fixed value, such ability
The length for showing that X-axis in oscillograph screen is fixed.In conjunction with formula (1) and formula (2), have:
Wherein capacitor charging time t is the synchronised clock period, can just make the logical sequence waveform of scan process complete.It is single
Piece machine can individually adjust Uc to adjust X-axis and show length, or in order to observe conveniently, allow Uc to fix, that is, the X-axis shown is shown
Length is fixed.According to formula (3), charging resistor R1 is changed according to synchronised clock period t, keeps final Uc constant, specific software
Design control flow is detailed in Fig. 6.
The communication and display of single-chip microcontroller
The frame structure of two machine communication
Since each synchronised clock period will read in logical sequence signal and handle, so single-chip microcontroller wants processing core
Control function (analysis input logic signal timing, user key-press processing, the output of oscilloscope display signal etc.), is responsible for interface again
It shows (liquid crystal display, LED indication etc.).When logic analyser frequency to be treated is higher, the processing speed of single-chip microcontroller is just
Seem inadequate.Interface display and core control function are handled (see Fig. 7) by 2 single-chip microcontrollers respectively by system, alleviate single-chip microcontroller
Operation burden, improve complete machine rate.By UART communication come intercorrelation information between two single-chip microcontrollers.
Communication protocol
Synchronised clock frequency (i.e. logical sequence signal) is faster, and the operation burden of single-chip microcontroller is higher.Therefore, two single-chip microcontrollers
Between communication protocol cannot be excessively complicated, such as the common data frame format of household Internet of Things [7].Article devises one for this
The communication by simple means agreement of system, it is more simpler better with enough for degree, it can effectively promote communication efficiency.Agreement is master-slave mode, often
A data frame only 3 bytes, an including start byte, a command byte, one data word section (see Fig. 8).
Frame banner word system is set to 0x5a.System needs to receive two bytes again after receiving frame banner word.Command byte
The attribute and meaning for indicating data, the primary commands word definition specifically used are as shown in table 1.
1 command word meaning table of table
The advantages of basic principles and main features and the utility model of the utility model have been shown and described above.Current row
The technical staff of industry is described in above embodiments and description it should be appreciated that the present utility model is not limited to the above embodiments
Only illustrate the principles of the present invention, on the premise of not departing from the spirit and scope of the utility model, the utility model is also
It will have various changes and improvements, these various changes and improvements fall within the scope of the claimed invention.The utility model
Claimed range is defined by the appending claims and its equivalent thereof.
Claims (2)
1. a kind of Simple and Easy Logic Tester based on oscillograph X-Y mode, including oscillograph, it is characterised in that: further include control
Processing unit, display unit and signal scanning drive module, the control processing unit and the signal scanning drive module are same
The display signal output end of step clock signal, the control processing unit is connect with the display unit, and the control processing is single
The control signal and sequential logic signal output end of member are connect with the signal input part of the signal scanning drive module, the letter
The signal output end of number scan driver module is connect with the oscillograph.
2. the Simple and Easy Logic Tester according to claim 1 based on oscillograph X-Y mode, it is characterised in that: the letter
Number scan driver module is scanned by X passage and is connect with control circuit and Y Channel scan with control circuit with the oscillograph.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110749763A (en) * | 2019-12-24 | 2020-02-04 | 深圳市鼎阳科技股份有限公司 | Triggering method based on I2S signal and oscilloscope |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110749763A (en) * | 2019-12-24 | 2020-02-04 | 深圳市鼎阳科技股份有限公司 | Triggering method based on I2S signal and oscilloscope |
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Effective date of registration: 20210316 Address after: 362000 Shugang Road, Quanzhou City, Fujian Province / Zhongshan North Road (old school site) Patentee after: LIMING VOCATIONAL University Address before: 350000 36 Zhupai Houxiang, Taijiang District, Fuzhou City, Fujian Province Patentee before: Lin Longsen |