CN110728099A - Charge control memory capacitor simulator circuit - Google Patents
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Abstract
The invention discloses a charge control memcapacitor simulator circuit which comprises a capacitor network, a sampling charge circuit, an inverse integrator, an inverse proportioner and a multiplier, wherein the capacitor network is configured and used for converting an input signal in the circuit into a charge signal; the sampling charge circuit is configured and used for sampling a charge signal output by the capacitor network; configuring an inverse integrator for realizing integral operation of an input voltage signal, wherein the output and the input are in inverse phase; configuring an inverting proportioner for realizing that the output voltage and the input voltage are in proportional operation relation and are in inverting; the multiplier is configured to perform a multiplication operation of signals from the two input terminals. The invention provides a memcapacitor simulator circuit which is used for simulating voltage and charge characteristics of a memcapacitor and replacing an actual memcapacitor to carry out experiments, application and research.
Description
Technical Field
The invention belongs to the technical field of circuit design, relates to a charge control memcapacitor simulator circuit, and particularly relates to an analog circuit for realizing the relation between voltage and charge of a charge control memcapacitor.
Background
Chua proposed the concept of memristors in 1971. With the physical realization of memristors, Ventra et al have further widened the range of memory elements, proposing two new memory element concepts: memcapacitor and memory inductor. The three memory elements are considered to have great application prospects in nonvolatile storage, artificial neural networks, large-scale integrated circuits and chaos theory research due to the unique properties of the three memory elements. The memcapacitor is influenced by the historical state of current or charge in the circuit, so the memcapacitor has the function of 'memorizing'. The memory container is used as a novel circuit element with a memory function, has the greatest advantage that information can be stored without providing a power supply, and can be applied to the fields of non-loss storage, learning, adaptation, spontaneous behavior simulation and the like. Therefore, relatively few researches on the memory capacitor are carried out at present, and the main reasons are that the actual physical device of the memory capacitor is not realized yet, the mathematical model and the circuit structure are not perfect enough, and the researches in the nonlinear field are few. Therefore, the functions and the characteristics of the memcapacitor can be realized by building an emulator circuit of the memcapacitor, and the memcapacitor is further researched. Therefore, the simulator circuit of the memcapacitor plays an important role in the development of the memcapacitor in the future.
Disclosure of Invention
Aiming at the fact that no actual commercial device exists in the current memory capacitor, the invention provides a charge control memory capacitor simulator circuit which is used for simulating the voltage and charge characteristics of the memory capacitor and replacing the actual memory capacitor to conduct experiments, application and research.
In order to solve the technical problems in the prior art, the technical scheme of the invention is as follows:
a charge-controlled memcapacitor emulator circuit is characterized by comprising a capacitance network, a sampling charge circuit, an inverse integrator, an inverse proportioner and a multiplier, wherein,
configuring a capacitor network for converting an input signal in a circuit into a charge signal;
the sampling charge circuit is configured and used for sampling a charge signal output by the capacitor network;
configuring an inverse integrator for realizing integral operation of an input voltage signal, wherein the output and the input are in inverse phase;
configuring an inverting proportioner for realizing that the output voltage and the input voltage are in proportional operation relation and are in inverting;
configuring a multiplier for realizing the multiplication operation of signals from two input ends;
the sampling charge circuit is implemented by a first operational amplifier U1;
the inverting integrator is implemented using a second operational amplifier U2;
the inverting proportioner is implemented by a third operational amplifier U3;
the multiplier is realized by a multiplier U4;
the charge-controlled memcapacitor emulator circuit comprises a 1 st resistor R1, a 2 nd resistor R2, a 3 rd resistor R3, a 4 th resistor R4, a 5 th resistor R5, a 6 th resistor R6, a 7 th resistor R7, a 1 st capacitor C1, a 2 nd capacitor C2, a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3 and a multiplier U4, wherein,
one end of a 1 st resistor R1 and one end of a 2 nd capacitor C2 are connected with an input signal Vc, the other end of a 1 st resistor R1 and one end of a 2 nd resistor R2 are connected with a 2 nd pin of an inverting input end of a first operational amplifier U1, the other end of R2 is grounded, the other end of a 2 nd capacitor C2 and the other end of a 3 rd resistor R3 are connected with a W pin of a multiplier U4, the other end of a 3 rd resistor R3 and one end of a 4 th resistor R4 are connected with a 3 rd pin of a non-inverting input end of a first operational amplifier U1, a 6 th pin of an output end of the first operational amplifier U1, the other end of a 4 th resistor R4 and the other end of a 5 th resistor R5 are connected with an X1 pin of the multiplier U4, a 4 th pin of the first operational amplifier U1 is connected with a power supply VEE and a 7 th pin VCC, and the;
the other end of the 5 th resistor R5 and one end of the 1 st capacitor C1 are connected with the 2 nd pin of the inverting input end of the second operational amplifier U2, the other end of the 1 st capacitor C1 and one end of the 6 th resistor R6 are connected with the 6 th pin of the output end of the second operational amplifier U2, the 3 rd pin of the non-inverting input end of the second operational amplifier U2 is grounded, the 4 th pin is connected with the VEE, the 7 th pin is connected with the VCC, and the 1 st pin and the 8 th pin are suspended;
one end of a 7 th resistor R7 and the other end of a 6 th resistor R6 are connected with a 2 nd pin of an inverting input end of a third operational amplifier U3, the other end of the 7 th resistor R7 and a 6 th pin of an output end of the third operational amplifier U3 are connected with a Y1 pin of a multiplier U4, a 3 rd pin of a non-inverting input end of the third operational amplifier U3 is grounded, a 4 th pin is connected with a power supply VEE, a 7 th pin is connected with the power supply VEE, and a 1 st pin and an 8 th pin are suspended;
an X2 pin of the multiplier U4 is grounded with a Y2 pin, VS + is connected with a power supply VCC, VS-is connected with a power supply VEE, a Z pin is grounded, a 6 th pin of an output end of the first operational amplifier U1, the other end of the 4 th resistor R4 and the other end of the 5 th resistor R5 are connected with an X1 pin of a multiplier U4, the other end of the 7 th resistor R7 and the 6 th pin of an output end of the third operational amplifier are connected with a Y1 pin of a multiplier U4, and the other end of the second capacitor C2 and the other end of the 3 rd resistor R3 are connected with a W pin of a multiplier U4.
As a further improvement, the first operational amplifier U1 employs a chip OP07 CP.
As a further improvement, the second operational amplifier U2 employs a chip OP07 CP.
As a further improvement, the third operational amplifier U3 employs a chip OP07 CP.
As a further improvement, the multiplier U4 adopts a chip AD633 AN.
In the above technical solution, the charge control memcapacitor provided by the present invention is defined as:
in the formula (1), C is the capacitance of a memcapacitor, qcTo pass the charge of the memcapacitor, xcIs an internal state variable for remembering the container.
The modeling of the patent is as follows:
in the formula (2), the circuit parameters of the memcapacitor model are shown, and the memcapacitor is charge-controlled according to the voltage and charge expression, so that the memcapacitor is called as a charge-controlled memcapacitor.
The memory capacitor is a special nonlinear element and is very easy to generate chaos when applied to a circuit. Because the physical memcapacitor does not serve as an actual element to the market, even after the memcapacitor is commercialized, the physical memcapacitor exists in a large-scale integrated circuit mode, and a nano-scale memcapacitor which is separated independently is difficult to use. Therefore, the equivalent analog circuit is used for replacing a real object memory capacitor, and the circuit design and application by using the equivalent analog circuit have wide and profound significance.
The invention simulates the voltage and charge relation of an actual memcapacitor through the combination of an operational amplifier, a capacitor, a resistor and some basic components of a multiplier. To verify the feasibility of the memristor provided by the invention, the voltage and charge characteristic curves of the hysteresis memristor are simulated by Multisim software. Firstly, sinusoidal signals v are added to two ends of a memory containerinSin (2 pi f) V, then varying the frequency f of the sinusoidal signal, observing V as a function of frequency fc-qcAnd (5) a characteristic curve change rule. Recall v of the capacitor as a function of frequency fc-qcThe characteristic curve is shown in FIG. 3, due to the obtained vc-qcThe hysteresis loops are located in the first and third quadrants, so the proposed memcapacitor is also passive. Therefore, the hysteresis sidelobe area is monotonically increased along with the reduction of f, and the load control memcapacitor model provided by the invention meets the essential characteristics of a generalized memcapacitor.
Compared with the prior art, the invention has the following technical effects:
the invention designs an emulator circuit capable of realizing voltage and charge characteristics of a memory capacitor, the emulator circuit comprises 3 operational amplifiers and 1 multiplier, has a simple structure, can replace circuit design, experiments and application related to the memory capacitor, and has important significance for researching the characteristics and the application of the memory capacitor.
The invention relates to an analog circuit for realizing a memcapacitor, which realizes the voltage and charge characteristics of the memcapacitor by utilizing the analog circuit. The invention utilizes an integrated operation circuit to realize corresponding operation in the characteristics of a memory capacitor, wherein an inverting integrator is used for realizing integral operation on input voltage, an inverting proportioner is used for realizing that output voltage and input voltage are in proportional operation relation and are in inverting, and a multiplication circuit is used for realizing multiplication of input signals from two ends.
Drawings
FIG. 1 is a block diagram of a circuit structure of a charge-controlled memcapacitor emulator of the present invention.
FIG. 2 is a schematic diagram of a charge-controlled memcapacitor emulator circuit of the present invention.
FIG. 3 shows v being connected at the inputinAfter sin (2 pi f) V alternating current voltage source, acquiring V of the charge control memcapacitor by using Multisim software under different frequency conditions by changing frequency fc-qcAnd (4) a hysteresis characteristic curve simulation graph. (a) 1000Hz, (b) 400Hz, and (c) 100 Hz.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1-2, the charge-controlled memcapacitor emulator circuit of the present embodiment includes a capacitor network, a sampled charge circuit, an inverse integrator, an inverse scaler, and a multiplier, wherein,
configuring a capacitor network for converting an input signal in a circuit into a charge signal;
the sampling charge circuit is configured and used for sampling a charge signal output by the capacitor network;
configuring an inverse integrator for realizing integral operation of an input voltage signal, wherein the output and the input are in inverse phase;
configuring an inverting proportioner for realizing that the output voltage and the input voltage are in proportional operation relation and are in inverting;
configuring a multiplier for realizing the multiplication operation of signals from two input ends;
the sampling charge circuit is implemented by a first operational amplifier U1;
the inverting integrator is implemented using a second operational amplifier U2;
the inverting proportioner is implemented by a third operational amplifier U3;
the multiplier is realized by a multiplier U4;
u1, U2 and U3 all adopt a chip OP07CP, and a multiplier U4 adopts AD633 AN. OP07CP and AD633AN are both conventional chips.
Referring to fig. 2, the charge-controlled memcapacitor emulator circuit includes a 1 st resistor R1, a 2 nd resistor R2, a 3 rd resistor R3, a 4 th resistor R4, a 5 th resistor R5, a 6 th resistor R6, a 7 th resistor R7, a 1 st capacitor C1, a 2 nd capacitor C2, a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3 and a multiplier U4, wherein,
one end of a 1 st resistor R1 and one end of a 2 nd capacitor C2 are connected with an input signal Vc, the other end of a 1 st resistor R1 and one end of a 2 nd resistor R2 are connected with a 2 nd pin of an inverting input end of a first operational amplifier U1, the other end of R2 is grounded, the other end of a 2 nd capacitor C2 and the other end of a 3 rd resistor R3 are connected with a W pin of a multiplier U4, the other end of a 3 rd resistor R3 and one end of a 4 th resistor R4 are connected with a 3 rd pin of a non-inverting input end of a first operational amplifier U1, a 6 th pin of an output end of the first operational amplifier U1, the other end of a 4 th resistor R4 and the other end of a 5 th resistor R5 are connected with an X1 pin of the multiplier U4, a 4 th pin of the first operational amplifier U1 is connected with a power supply VEE and a 7 th pin VCC, and the;
the other end of the 5 th resistor R5 and one end of the 1 st capacitor C1 are connected with the 2 nd pin of the inverting input end of the second operational amplifier U2, the other end of the 1 st capacitor C1 and one end of the 6 th resistor R6 are connected with the 6 th pin of the output end of the second operational amplifier U2, the 3 rd pin of the non-inverting input end of the second operational amplifier U2 is grounded, the 4 th pin is connected with the VEE, the 7 th pin is connected with the VCC, and the 1 st pin and the 8 th pin are suspended;
one end of a 7 th resistor R7 and the other end of a 6 th resistor R6 are connected with a 2 nd pin of an inverting input end of a third operational amplifier U3, the other end of the 7 th resistor R7 and a 6 th pin of an output end of the third operational amplifier U3 are connected with a Y1 pin of a multiplier U4, a 3 rd pin of a non-inverting input end of the third operational amplifier U3 is grounded, a 4 th pin is connected with a power supply VEE, a 7 th pin is connected with the power supply VEE, and a 1 st pin and an 8 th pin are suspended;
an X2 pin of the multiplier U4 is grounded with a Y2 pin, VS + is connected with a power supply VCC, VS-is connected with a power supply VEE, a Z pin is grounded, a 6 th pin of an output end of the first operational amplifier U1, the other end of the 4 th resistor R4 and the other end of the 5 th resistor R5 are connected with an X1 pin of a multiplier U4, the other end of the 7 th resistor R7 and the 6 th pin of an output end of the third operational amplifier are connected with a Y1 pin of a multiplier U4, and the other end of the second capacitor C2 and the other end of the 3 rd resistor R3 are connected with a W pin of a multiplier U4.
In the above technical solution, one end of the capacitor C2 is connected to the connection input terminal, and the other end is connected to the W pin of the multiplier U4 and further connected to the resistor R3. Voltage across C2 is vc2The charge on C2 is qc2If the sampling charge circuit U1 is used for sampling charge, the output of the 6 th pin of the sampling charge circuit U1 is:
the inverting integrator U2 is used for integrating the input current, and the voltage at the pin 6 of the inverting integrator U2 is defined as vU2For recalling state variable x of containercThen, the following formula can be obtained:
vU2＝xc(4)
an inverting scaler U3 for realizing the input voltage vU3And vU2Is the voltage v of the 6 th pin of U3U3Comprises the following steps:
multiplier U4, model AD633AN, for implementing the inverse proportioner sampling the output signal at pin 6 of the charge circuit U1 and implementing the inverse proportioner U3 output signal vU3I.e. the voltage v at the W pin of the output of the multiplier U4U4Comprises the following steps:
then memory total v of the containercComprises the following steps:
FIG. 3 shows a design of a charge control memcapacitor simulator circuit simulated by Multisim softwarec-qcAnd (4) a hysteresis characteristic simulation diagram. When the input signal is added to two ends of a memory capacitor, a sine signal v is addedinSin (2 pi f) V, then varying the frequency f of the sinusoidal signal, observing V as a function of frequency fc-qcAnd (5) a characteristic curve change rule. Recall v of the capacitor as a function of frequency fc-qcThe characteristic curve is shown in FIG. 3, due to the obtained vc-qcThe hysteresis loops are located in the first and third quadrants, so the proposed memcapacitor is also passive. Therefore, the hysteresis sidelobe area is monotonically increased along with the decrease of f, namely, the curve is continuously shrunk along with the increase of the input frequency, and therefore, the charge control memcapacitor model provided by the invention meets the essential characteristics of the memcapacitor.
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not to be construed as limiting the present invention, and that the changes and modifications of the above embodiments are within the scope of the present invention.
Claims (5)
1. A charge-controlled memcapacitor emulator circuit is characterized by comprising a capacitance network, a sampling charge circuit, an inverse integrator, an inverse proportioner and a multiplier, wherein,
configuring a capacitor network for converting an input signal in a circuit into a charge signal;
the sampling charge circuit is configured and used for sampling a charge signal output by the capacitor network;
configuring an inverse integrator for realizing integral operation of an input voltage signal, wherein the output and the input are in inverse phase;
configuring an inverting proportioner for realizing that the output voltage and the input voltage are in proportional operation relation and are in inverting;
configuring a multiplier for realizing the multiplication operation of signals from two input ends;
the sampling charge circuit is implemented by a first operational amplifier U1;
the inverting integrator is implemented using a second operational amplifier U2;
the inverting proportioner is implemented by a third operational amplifier U3;
the multiplier is realized by a multiplier U4;
the charge-controlled memcapacitor emulator circuit comprises a 1 st resistor R1, a 2 nd resistor R2, a 3 rd resistor R3, a 4 th resistor R4, a 5 th resistor R5, a 6 th resistor R6, a 7 th resistor R7, a 1 st capacitor C1, a 2 nd capacitor C2, a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3 and a multiplier U4, wherein,
one end of a 1 st resistor R1 and one end of a 2 nd capacitor C2 are connected with an input signal Vc, the other end of a 1 st resistor R1 and one end of a 2 nd resistor R2 are connected with a 2 nd pin of an inverting input end of a first operational amplifier U1, the other end of R2 is grounded, the other end of a 2 nd capacitor C2 and the other end of a 3 rd resistor R3 are connected with a W pin of a multiplier U4, the other end of a 3 rd resistor R3 and one end of a 4 th resistor R4 are connected with a 3 rd pin of a non-inverting input end of a first operational amplifier U1, a 6 th pin of an output end of the first operational amplifier U1, the other end of a 4 th resistor R4 and the other end of a 5 th resistor R5 are connected with an X1 pin of the multiplier U4, a 4 th pin of the first operational amplifier U1 is connected with a power supply VEE and a 7 th pin VCC, and the;
the other end of the 5 th resistor R5 and one end of the 1 st capacitor C1 are connected with the 2 nd pin of the inverting input end of the second operational amplifier U2, the other end of the 1 st capacitor C1 and one end of the 6 th resistor R6 are connected with the 6 th pin of the output end of the second operational amplifier U2, the 3 rd pin of the non-inverting input end of the second operational amplifier U2 is grounded, the 4 th pin is connected with the VEE, the 7 th pin is connected with the VCC, and the 1 st pin and the 8 th pin are suspended;
one end of a 7 th resistor R7 and the other end of a 6 th resistor R6 are connected with a 2 nd pin of an inverting input end of a third operational amplifier U3, the other end of the 7 th resistor R7 and a 6 th pin of an output end of the third operational amplifier U3 are connected with a Y1 pin of a multiplier U4, a 3 rd pin of a non-inverting input end of the third operational amplifier U3 is grounded, a 4 th pin is connected with a power supply VEE, a 7 th pin is connected with the power supply VEE, and a 1 st pin and an 8 th pin are suspended;
an X2 pin of the multiplier U4 is grounded with a Y2 pin, VS + is connected with a power supply VCC, VS-is connected with a power supply VEE, a Z pin is grounded, a 6 th pin of an output end of the first operational amplifier U1, the other end of the 4 th resistor R4 and the other end of the 5 th resistor R5 are connected with an X1 pin of a multiplier U4, the other end of the 7 th resistor R7 and the 6 th pin of an output end of the third operational amplifier are connected with a Y1 pin of a multiplier U4, and the other end of the second capacitor C2 and the other end of the 3 rd resistor R3 are connected with a W pin of a multiplier U4.
2. The charge-controlled memcapacitor emulator circuit of claim 1, wherein the first operational amplifier U1 is implemented as a chip OP07 CP.
3. The charge-controlled memcapacitor emulator circuit of claim 1, wherein the second operational amplifier U2 employs a chip OP07 CP.
4. The charge-controlled memcapacitor emulator circuit of claim 1, wherein the third operational amplifier U3 is implemented as a chip OP07 CP.
5. The charge-controlled memcapacitor emulator circuit of claim 1, wherein the multiplier U4 employs a chip AD633 AN.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111327286A (en) * | 2020-03-05 | 2020-06-23 | 杭州电子科技大学 | Mechanical load control memristor based on hardware integral control |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015123802A1 (en) * | 2014-02-22 | 2015-08-27 | 梅增霞 | Classical lorenz-type chaotic system switching method and circuit with differentfractional orders |
| CN107451380A (en) * | 2017-09-08 | 2017-12-08 | 杭州电子科技大学 | Realize that the circuit of container emulator is recalled in exponential type lotus control |
| CN108736860A (en) * | 2018-05-24 | 2018-11-02 | 杭州电子科技大学 | Container equivalent-circuit model is recalled in a kind of lotus control |
-
2019
- 2019-09-06 CN CN201910840294.1A patent/CN110728099B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015123802A1 (en) * | 2014-02-22 | 2015-08-27 | 梅增霞 | Classical lorenz-type chaotic system switching method and circuit with differentfractional orders |
| CN107451380A (en) * | 2017-09-08 | 2017-12-08 | 杭州电子科技大学 | Realize that the circuit of container emulator is recalled in exponential type lotus control |
| CN108736860A (en) * | 2018-05-24 | 2018-11-02 | 杭州电子科技大学 | Container equivalent-circuit model is recalled in a kind of lotus control |
Non-Patent Citations (1)
| Title |
|---|
| 袁方;王光义;靳培培;: "一种忆感器模型及其振荡器的动力学特性研究" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111327286A (en) * | 2020-03-05 | 2020-06-23 | 杭州电子科技大学 | Mechanical load control memristor based on hardware integral control |
| CN111327286B (en) * | 2020-03-05 | 2023-06-27 | 杭州电子科技大学 | Mechanical load control memristor based on hardware integral control |
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Effective date of registration: 20231129 Address after: 272000 north of Hongxiang road and east of Jiamei Road, Jining Economic Development Zone, Jining City, Shandong Province Patentee after: SHANDONG LUNENG GUANGDA ELECTRIC POWER EQUIPMENT Co.,Ltd. Address before: 579 qianwangang Road, Huangdao District, Qingdao City, Shandong Province Patentee before: SHANDONG University OF SCIENCE AND TECHNOLOGY |