CN110147597B - Multi-stable-state magnetic control memristor equivalent simulation circuit - Google Patents
Multi-stable-state magnetic control memristor equivalent simulation circuit Download PDFInfo
- Publication number
- CN110147597B CN110147597B CN201910388072.0A CN201910388072A CN110147597B CN 110147597 B CN110147597 B CN 110147597B CN 201910388072 A CN201910388072 A CN 201910388072A CN 110147597 B CN110147597 B CN 110147597B
- Authority
- CN
- China
- Prior art keywords
- pin
- inverse proportion
- resistor
- multiplier
- proportion device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a multistable magnetic control memristor equivalent simulation circuit, which belongs to the technical field of circuit design, and is characterized in that a generalized memristor volt-ampere characteristic is realized by using a simulation circuit, and corresponding operation in the memristor characteristic is realized by using an integrated operation circuit, wherein a voltage follower is used for realizing that output voltage is equal to input voltage, an inverting integrator is used for realizing integral operation on the input voltage, and an inverting proportioner is used for realizing that the output voltage and the input voltage are in proportional operation relation and are in inverting phase; the multiplication circuit is used for realizing multiplication of input signals from two ends. The memristor-based circuit design and experiment device is simple in structure, can replace an actual generalized memristor to achieve circuit design, experiment and application related to the memristor, and has important significance for researching characteristics and application of the memristor.
Description
Technical Field
The invention belongs to the technical field of circuit design, and particularly relates to a multistable magnetic control memristor equivalent analog circuit.
Background
The fourth basic circuit element of the memristor, which is followed by the resistor, the capacitor and the inductor, describes the relationship between magnetic flux and electric charge, has the characteristic that any combination of the other three basic circuit elements cannot be copied, and is a nonlinear resistor with a memory function. Chua theoretically predicts the existence of memristive elements according to the principle of completeness of circuit basic variable combination in 1971, and the physical TiO2 memristor is not made for the first time in Hewlett packard laboratory in 2008. The memristor can memorize the quantity of charges flowing through the memristor, so that the memristor becomes a natural nonvolatile memory, the integrated circuit element becomes small in size and convenient to carry due to the existence of the memristor, and meanwhile, the memristor is widely applied to the fields of neural networks, electronic engineering, communication engineering and the like. However, the nanometer technology has the disadvantages of high cost and difficult realization, and the physical memristor is not taken as an actual element to be brought to the market; even after the memristor is commercialized, the memristor exists in the form of a large-scale integrated circuit, and a single separated nanoscale memristor is difficult to utilize. Therefore, the equivalent analog circuit is used for replacing the physical memristor, and the circuit design and application by using the equivalent analog circuit have wide and profound significance.
At present, reported memristor simulation models comprise a PSPICE simulation model and a hardware equivalent circuit for simulating a memristor, and on one hand, the two memristor models are complex in principle and difficult to realize in practice; on the other hand, the two classes of memristors are difficult to accurately simulate the characteristics of the actual memristors. Therefore, it is of great significance to design a memristor equivalent circuit which is simple in principle, easy to implement and high in accuracy degree.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides the multistable magnetic control memristor equivalent analog circuit which is reasonable in design, overcomes the defects in the prior art and has a good effect.
In order to achieve the purpose, the invention adopts the following technical scheme:
a multi-stable-state magnetic control memristor equivalent analog circuit comprises a resistance network, a voltage follower, an inverse integrator, an inverse proportioner and a multiplier;
a voltage follower configured to achieve an output voltage equal to an input voltage;
an inverting integrator configured to perform an integration operation on an input voltage;
an inverting scaler configured to achieve that the output voltage is in a proportional operation relationship with the input voltage and is in an inverted phase;
a multiplier configured to effect multiplication of two input signals;
the multi-stable-state magnetic control memristor equivalent analog circuit comprises two closed-loop circuits; the resistance network, the voltage follower U1, the first inverse phase proportioner U2, the inverse phase integrator U3, the first multiplier UA1, the second multiplier UA2 and the second inverse phase proportioner U5 are sequentially connected through a line to form a first closed loop circuit; the resistance network, the voltage follower U1, the third inverse proportion device U4, the second multiplier UA2 and the second inverse proportion device U5 are sequentially connected through a circuit to form a second closed loop circuit;
the resistor network comprises a resistor R11, one end of the resistor R11 is connected with a pin 3 of the voltage follower U1 to serve as an input end, and the other end of the resistor R11 is connected with a pin 6 of the third inverse phase proportioner U4 to serve as an output end.
The input end of the resistor network is connected with a pin 3 of a voltage follower U1, a pin 2 of the voltage follower U1 is in short circuit with a pin 6, the pin 3 and one end of a first resistor R1 are connected with a pin 2 of a first inverse proportion device U2 through a circuit, the pin 4 is connected with a power supply VEE, the pin 7 is connected with a power supply VCC, and the pin 1 and the pin 8 are suspended; a 6 th pin of the first inverse phase proportioner U2 is connected with a2 nd pin thereof through a second resistor R2, the 6 th pin of the first inverse phase proportioner U2 is also connected with a2 nd pin of the inverse phase integrator U3 through a third resistor R3, the 3 rd pin of the first inverse phase proportioner U is grounded, the 4 th pin of the first inverse phase proportioner U is connected with a power supply VEE, the 7 th pin of the first inverse phase proportioner U is connected with a power supply VCC, and the 1 st pin and the 8 th pin of the first inverse phase proportioner U are suspended; a2 nd pin of the inverse integrator U3 is connected with a 6 th pin through a parallel circuit consisting of a fourth resistor R4 and a first capacitor C1, the 6 th pin is also connected with an X1 pin of a first multiplier UA1, the 3 rd pin is grounded, the 4 th pin is connected with a power supply VEE, the 7 th pin is connected with a power supply VCC, and the 1 st pin and the 8 th pin are suspended; a Y1 pin of the first multiplier UA1 is connected with a sixth pin of the voltage tracker U1, an X2 pin and a Y2 pin of the first multiplier UA1 are grounded, a VS + pin is connected with a power supply VCC and is connected with the ground through a second capacitor C2, a VS-pin is connected with a power supply VEE and is connected with the ground through a third capacitor C3, a Z pin is grounded, and a W pin is connected with an X1 pin of the second multiplier UA 2; a pin Y1 of a second multiplier UA2 is connected with a pin 2 of a second inverse proportion device U5 through a tenth resistor R10 and is also connected with a pin 6 of the second inverse proportion device U5, a pin X2 and a pin Y2 of the second inverse proportion device U2 are grounded, a pin VS + of the second inverse proportion device U2 is connected with the ground through a fourth capacitor C4 while being connected with a power supply VCC, a pin VS-pin of the second inverse proportion device U2 is connected with the ground through a fifth capacitor C5 while being connected with a power supply VEE, a pin Z of the second inverse proportion device U2 is grounded, and a pin W of the second inverse proportion device U2 is connected with a pin 2 of a third inverse proportion device U4 through a sixth resistor R6; a2 nd pin of the second inverse proportion device U5 is connected with a parallel circuit of a tenth resistor R10 through a ninth resistor R9, a 3 rd pin of the second inverse proportion device U is grounded, a 6 th pin of the second inverse proportion device U5 is connected with a second pin of a third inverse proportion device U4 through an eighth resistor R8 and is connected with a Y1 pin of a second multiplier UA2, a 4 th pin of the second inverse proportion device U is connected with a power supply VEE, a 7 th pin of the second inverse proportion device U is connected with a power supply VCC, and a1 st pin and an 8 th pin of the second inverse proportion device U are suspended; the 2 nd pin of the third inverse proportion device U4 is connected with the w pin of the second multiplier UA2 through a sixth resistor R6, the 6 th pin of the third inverse proportion device U4 is used as the output end of the circuit and is connected with the 6 th pin of the integrator U3 through a fifth resistor R5, the 6 th pin of the third inverse proportion device U is connected with the 2 nd pin through a seventh resistor R7, the 6 th pin of the third inverse proportion device U is connected with the input end through an 11 th resistor R11, the 4 th pin of the third inverse proportion device U4 is connected with the power VEE, the 3 rd pin is grounded, the 7 th pin is connected with the power VCC, and the 1 st pin and the 8 th pin are suspended.
As a further improvement, the voltage follower U1, the inverting integrator U3, the first inverting proportion device U2, the second inverting proportion device U5 and the third inverting proportion device U4 all adopt an OP07CP chip.
The invention has the following beneficial technical effects:
the analog equivalent circuit capable of realizing the volt-ampere characteristic of the generalized memristor is designed, the analog circuit comprises 5 operational amplifiers and 2 multipliers, is simple in structure, can replace the actual generalized memristor to realize circuit design, experiments and application related to the memristor, and has important significance for research on the characteristic and application of the memristor.
The analog circuit for realizing the memristor utilizes the analog circuit to realize the volt-ampere characteristic of the generalized memristor, and particularly realizes the volt-ampere characteristic of the generalized memristor. The memristor characteristic corresponding operation is realized by utilizing an integrated operation circuit, wherein a voltage follower is used for realizing that the output voltage is equal to the input voltage, an inverting integrator is used for realizing the integral operation of the input voltage, and an inverting proportioner is used for realizing that the output voltage and the input voltage are in proportional operation relation and are in inverting phase; the multiplication circuit is used for realizing multiplication of input signals from two ends.
Drawings
Fig. 1 is a block diagram of the circuit configuration of the present invention.
FIG. 2 is a schematic diagram of an equivalent simulation circuit of the multistable magnetic control memristor.
Detailed Description
The invention is described in further detail below with reference to the following figures and embodiments:
the theoretical starting point of the invention is a defined expression of the generalized memristor:
as shown in FIG. 1, the multi-stable-state magnetic control memristor equivalent analog circuit comprises a resistance network, a voltage follower, an inverse integrator, an inverse proportion device, an operational amplifier and a multiplier;
a voltage follower configured to achieve an output voltage equal to an input voltage;
an inverting integrator configured to perform an integration operation on an input voltage;
an inverting scaler configured to achieve that the output voltage is proportional to the input voltage and in an inverted phase; the device comprises a first inverse proportion device U2 and a third inverse proportion device U4;
a multiplier configured to effect multiplication of signals of two inputs; comprising a first multiplier UA1 and a second multiplier UA2.
As shown in fig. 2, the resistor network includes a resistor R11, one end of the resistor R11 is connected to the 3 rd pin of the voltage follower U1 as an input end, and the other end of the resistor R11 is connected to the 6 th pin of the third inverse phase proportioner U4 as an output end;
a2 nd pin and a 6 th pin of the voltage follower U1 are in short circuit, a 3 rd pin and one end of a first resistor R1 are connected with a2 nd pin of the first inverse phase proportioner U2 through a line, a 4 th pin is connected with a power supply VEE, a 7 th pin is connected with a power supply VCC, and a1 st pin and an 8 th pin are suspended; the 6 th pin of the first inverse proportion device U2 is connected with the 2 nd pin through a second resistor R2, the 6 th pin of the first inverse proportion device U2 is also connected with the 2 nd pin of the inverse proportion device U3 through a third resistor R3, the 3 rd pin of the first inverse proportion device U2 is grounded, the 4 th pin of the first inverse proportion device U4 is connected with a power supply VEE, the 7 th pin of the first inverse proportion device U2 is connected with a power supply VCC, and the 1 st pin and the 8 th pin of the first inverse proportion device U2 are suspended; a2 nd pin of the inverse integrator U3 is connected with a 6 th pin through a parallel circuit consisting of a fourth resistor R4 and a first capacitor C1, the 6 th pin is also connected with an X1 pin of a first multiplier UA1, the 3 rd pin is grounded, the 4 th pin is connected with a power supply VEE, the 7 th pin is connected with a power supply VCC, and the 1 st pin and the 8 th pin are suspended; a Y1 pin of the first multiplier UA1 is connected with a sixth pin of the voltage tracker U1, an X2 pin and a Y2 pin of the first multiplier UA1 are grounded, a VS + pin is connected with a power supply VCC and is connected with the ground through a second capacitor C2, a VS-pin is connected with a power supply VEE and is connected with the ground through a third capacitor C3, a Z pin is grounded, and a W pin is connected with an X1 pin of the second multiplier UA 2; a pin Y1 of the second multiplier UA2 is connected with a pin 2 of a second inverse proportion device U5 through a tenth resistor R10, and is connected with a pin 6 of the second inverse proportion device U5, a pin X2 and a pin Y2 of the second multiplier UA2 are grounded, a pin VS + of the second multiplier UA2 is connected with a power supply VCC and is simultaneously connected with the ground through a fourth capacitor C4, a pin VS-is connected with a power supply VEE and is simultaneously connected with the ground through a fifth capacitor C5, a pin Z of the second multiplier UA2 is grounded, and a pin W of the second multiplier UA2 is connected with a pin 2 of a third inverse proportion device U4 through a sixth resistor R6; a2 nd pin of the second inverse proportion device U5 is connected with a parallel circuit of a tenth resistor R10 through a ninth resistor R9, a 3 rd pin of the second inverse proportion device U5 is grounded, a 6 th pin of the second inverse proportion device U5 is connected with a second pin of a third inverse proportion device U4 through an eighth resistor R8 and is connected with a Y1 pin of a second multiplier UA2, a 4 th pin of the second inverse proportion device U4 is connected with a power supply VEE, a 7 th pin of the second inverse proportion device U4 is connected with a power supply VCC, and a1 st pin and an 8 th pin of the second inverse proportion device U5 are suspended; the 2 nd pin of the third inverse proportion device U4 is connected with the w pin of the second multiplier UA2 through a sixth resistor R6, the 6 th pin of the third inverse proportion device U4 is used as the output end of the circuit and is connected with the 6 th pin of the integrator U3 through a fifth resistor R5, the 6 th pin of the third inverse proportion device U is connected with the 2 nd pin through a seventh resistor R7, the 6 th pin of the third inverse proportion device U is connected with the input end through an 11 th resistor R11, the 4 th pin of the third inverse proportion device U4 is connected with the power VEE, the 3 rd pin is grounded, the 7 th pin is connected with the power VCC, and the 1 st pin and the 8 th pin are suspended.
In a preferred embodiment, the voltage follower U1, the inverse integrator U3, the first inverse proportion device U2, the second inverse proportion device U5 and the third inverse proportion device U4 all adopt an OP07CP chip.
In the above technical solution, the output voltage v of the 3 rd pin of the voltage follower U1 13 To the voltage v of the connection input in And (3) equality:
v 13 ＝v in (2)；
the voltage follower U1 is used for realizing the input voltage v in With currentless, unattenuated transmission, i.e. pin 6 v of the voltage follower U1 16 Comprises the following steps:
v 16 ＝v 13 ＝v in (3)；
the output value of the first inverse proportion device U2 has inverse proportion relation with the output value, so
v 26 ＝-v 16 ＝-v in (4)；
The inverting integrator U3 is used for integrating the input current and defining the voltage v of the pin 6 of the inverting integrator U3 36 For the state variable x of the memristor, the following equation can be obtained:
v 36 ＝x (5)；
if take R 4 Far greater than R 3 Then, then
The X1 pin of the first multiplier UA1 is connected with the 6 th pin of the integrator U3, the Y1 pin of the first multiplier UA1 is connected with the sixth pin of the voltage tracker U1, the X2 pin and the Y2 pin of the first multiplier UA1 are grounded, the VS + pin of the first multiplier UA1 is connected with the power VCC and is connected with the ground through the second capacitor C2, the VS-pin of the first multiplier UA1 is connected with the power VEE and is connected with the ground through the third capacitor C3, the Z pin of the first multiplier UA1 is grounded, and the W pin of the first multiplier UA1 is connected with the X1 pin of the second multiplier UA2, namely the W pin of the first multiplier UA1 outputs voltage v 1w Comprises the following steps:
v 1w ＝v 16 ·v 36 ＝xv in (8)；
the ninth resistor R9 and the tenth resistor R10 in the second inverse proportion device U5 have the same resistance value, so that the input voltage v can be realized in 0 follows in antiphase, i.e. the voltage v of the 6 th pin of the second inverse proportional U5 36 Comprises the following steps:
the X1 pin of the second multiplier UA2 is connected with the w pin of the first multiplier UA1, and the Y1 pin thereof is connected with the second inverse proportion device through a tenth resistor R10A pin 2 of the U5 is connected with a pin 6 of the U5 of the second inverse proportion device, a pin X2 and a pin Y2 of the U5 are grounded, a pin VS + of the U5 is connected with the ground through a fourth capacitor C4 while being connected with a power supply VCC, a pin VS-of the U5 is connected with the ground through a fifth capacitor C5 while being connected with a power supply VEE, a pin Z of the U5 is grounded, and a pin W of the U5 is connected with a pin 2 of the U4 of the third inverse proportion device through a sixth resistor R6; i.e. the output voltage v of the W pin of the first multiplier UA1 2w Comprises the following steps:
v 2w ＝v 56 ·v 1w ＝-xv in 2 (10)；
and the third inverse proportion device U4 is used for realizing the proportional amplification relation of the output and the input and is in an inverse phase. The voltage v of the 6 th pin of the second and third inverse proportion device U4 46 Comprises the following steps:
as shown in fig. 2, assuming that the current flowing through the first resistor R1 is i (t), the current-voltage characteristic at both ends of the first resistor R1 is:
let R be 7 ＝R 8 Then equation 12 can be transformed to:
the internal state variable equation of the memristor equivalent circuit is as follows:
to sum up, the expression of the memristor equivalent circuit is:
it is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (2)
1. The multi-stable-state magnetic control memristor equivalent analog circuit is characterized by comprising a resistance network, a voltage follower, an inverse integrator, an inverse proportioner and a multiplier;
a voltage follower configured for achieving equality of the output voltage and the input voltage;
an inverting integrator configured to perform an integration operation on an input voltage;
an inverting scaler configured to achieve that the output voltage is in a proportional operation relationship with the input voltage and is in an inverted phase;
a multiplier configured to effect multiplication of two input signals;
the multi-stable-state magnetic control memristor equivalent analog circuit comprises two closed-loop circuits; the resistance network, the voltage follower U1, the first inverse phase proportioner U2, the inverse phase integrator U3, the first multiplier UA1, the second multiplier UA2 and the second inverse phase proportioner U5 are sequentially connected through a line to form a first closed loop circuit; the resistance network, the voltage follower U1, the third inverse proportion device U4, the second multiplier UA2 and the second inverse proportion device U5 are sequentially connected through a circuit to form a second closed loop circuit;
the resistor network comprises a resistor R11, one end of the resistor R11 is connected with a No. 3 pin of the voltage follower U1 to serve as an input end, and the other end of the resistor R11 is connected with a No. 6 pin of the third inverse phase proportioner U4 to serve as an output end;
a2 nd pin and a 6 th pin of the voltage follower U1 are in short circuit, a 3 rd pin and one end of a first resistor R1 are connected with a2 nd pin of the first inverse phase proportioner U2 through a line, a 4 th pin is connected with a power supply VEE, a 7 th pin is connected with a power supply VCC, and a1 st pin and an 8 th pin are suspended; the 6 th pin of the first inverse proportion device U2 is connected with the 2 nd pin through a second resistor R2, the 6 th pin of the first inverse proportion device U2 is also connected with the 2 nd pin of the inverse proportion device U3 through a third resistor R3, the 3 rd pin of the first inverse proportion device U2 is grounded, the 4 th pin of the first inverse proportion device U4 is connected with a power supply VEE, the 7 th pin of the first inverse proportion device U2 is connected with a power supply VCC, and the 1 st pin and the 8 th pin of the first inverse proportion device U2 are suspended; a2 nd pin of the inverse integrator U3 is connected with a 6 th pin through a parallel circuit consisting of a fourth resistor R4 and a first capacitor C1, the 6 th pin is also connected with an X1 pin of a first multiplier UA1, the 3 rd pin is grounded, the 4 th pin is connected with a power supply VEE, the 7 th pin is connected with a power supply VCC, and the 1 st pin and the 8 th pin are suspended; a Y1 pin of the first multiplier UA1 is connected with a sixth pin of the voltage tracker U1, an X2 pin and a Y2 pin of the first multiplier UA1 are grounded, a VS + pin is connected with a power supply VCC and is connected with the ground through a second capacitor C2, a VS-pin is connected with a power supply VEE and is connected with the ground through a third capacitor C3, a Z pin is grounded, and a W pin is connected with an X1 pin of the second multiplier UA 2; a pin Y1 of the second multiplier UA2 is connected with a pin 2 of a second inverse proportion device U5 through a tenth resistor R10, and is connected with a pin 6 of the second inverse proportion device U5, a pin X2 and a pin Y2 of the second multiplier UA2 are grounded, a pin VS + of the second multiplier UA2 is connected with a power supply VCC and is simultaneously connected with the ground through a fourth capacitor C4, a pin VS-is connected with a power supply VEE and is simultaneously connected with the ground through a fifth capacitor C5, a pin Z of the second multiplier UA2 is grounded, and a pin W of the second multiplier UA2 is connected with a pin 2 of a third inverse proportion device U4 through a sixth resistor R6; a2 nd pin of the second inverse proportion device U5 is connected with a parallel circuit of a tenth resistor R10 through a ninth resistor R9, a 3 rd pin of the second inverse proportion device U is grounded, a 6 th pin of the second inverse proportion device U5 is connected with a second pin of a third inverse proportion device U4 through an eighth resistor R8 and is connected with a Y1 pin of a second multiplier UA2, a 4 th pin of the second inverse proportion device U is connected with a power supply VEE, a 7 th pin of the second inverse proportion device U is connected with a power supply VCC, and a1 st pin and an 8 th pin of the second inverse proportion device U are suspended; the 2 nd pin of the third inverse proportion device U4 is connected with the w pin of the second multiplier UA2 through a sixth resistor R6, the 6 th pin of the third inverse proportion device U4 is used as the output end of the circuit and is connected with the 6 th pin of the integrator U3 through a fifth resistor R5, the 6 th pin of the third inverse proportion device U is connected with the 2 nd pin through a seventh resistor R7, the 6 th pin of the third inverse proportion device U is connected with the input end through an 11 th resistor R11, the 4 th pin of the third inverse proportion device U4 is connected with the power VEE, the 3 rd pin is grounded, the 7 th pin is connected with the power VCC, and the 1 st pin and the 8 th pin are suspended.
2. The multistable magnetic control memristor equivalent analog circuit according to claim 1, wherein the voltage follower U1, the inverse integrator U3, the first inverse proportion U2, the second inverse proportion U5 and the third inverse proportion U4 all adopt OP07CP chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910388072.0A CN110147597B (en) | 2019-05-10 | 2019-05-10 | Multi-stable-state magnetic control memristor equivalent simulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910388072.0A CN110147597B (en) | 2019-05-10 | 2019-05-10 | Multi-stable-state magnetic control memristor equivalent simulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110147597A CN110147597A (en) | 2019-08-20 |
| CN110147597B true CN110147597B (en) | 2022-12-27 |
Family
ID=67595128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910388072.0A Active CN110147597B (en) | 2019-05-10 | 2019-05-10 | Multi-stable-state magnetic control memristor equivalent simulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110147597B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110728102B (en) * | 2019-09-29 | 2023-09-22 | 山东科技大学 | Multistable memristor analog circuit |
| CN113645023B (en) * | 2021-08-12 | 2023-11-21 | 深圳大学 | Chaotic signal steady-state circuit and memristor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219983A (en) * | 2013-04-16 | 2013-07-24 | 杭州电子科技大学 | Memristor equivalent simulation circuit |
| CN203193601U (en) * | 2013-04-16 | 2013-09-11 | 杭州电子科技大学 | Analog circuit with characteristic of memristor |
| CN107169253A (en) * | 2017-07-19 | 2017-09-15 | 杭州电子科技大学 | Logarithmic recalls container equivalent simulation circuit |
| CN107526897A (en) * | 2017-09-08 | 2017-12-29 | 杭州电子科技大学 | A kind of equivalent simulation circuit for flowing control and recalling sensor |
| CN107526896A (en) * | 2017-09-08 | 2017-12-29 | 杭州电子科技大学 | A kind of magnetic control recalls the equivalent simulation circuit of sensor model |
| CN206977024U (en) * | 2017-08-02 | 2018-02-06 | 山东科技大学 | A kind of overcurrent-overvoltage protecting circuit |
| CN206991310U (en) * | 2017-07-19 | 2018-02-09 | 杭州电子科技大学 | A kind of logarithmic recalls container equivalent simulation circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9152827B2 (en) * | 2012-12-19 | 2015-10-06 | The United States Of America As Represented By The Secretary Of The Air Force | Apparatus for performing matrix vector multiplication approximation using crossbar arrays of resistive memory devices |
| US10885429B2 (en) * | 2015-07-06 | 2021-01-05 | University Of Dayton | On-chip training of memristor crossbar neuromorphic processing systems |
-
2019
- 2019-05-10 CN CN201910388072.0A patent/CN110147597B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219983A (en) * | 2013-04-16 | 2013-07-24 | 杭州电子科技大学 | Memristor equivalent simulation circuit |
| CN203193601U (en) * | 2013-04-16 | 2013-09-11 | 杭州电子科技大学 | Analog circuit with characteristic of memristor |
| CN107169253A (en) * | 2017-07-19 | 2017-09-15 | 杭州电子科技大学 | Logarithmic recalls container equivalent simulation circuit |
| CN206991310U (en) * | 2017-07-19 | 2018-02-09 | 杭州电子科技大学 | A kind of logarithmic recalls container equivalent simulation circuit |
| CN206977024U (en) * | 2017-08-02 | 2018-02-06 | 山东科技大学 | A kind of overcurrent-overvoltage protecting circuit |
| CN107526897A (en) * | 2017-09-08 | 2017-12-29 | 杭州电子科技大学 | A kind of equivalent simulation circuit for flowing control and recalling sensor |
| CN107526896A (en) * | 2017-09-08 | 2017-12-29 | 杭州电子科技大学 | A kind of magnetic control recalls the equivalent simulation circuit of sensor model |
Non-Patent Citations (2)
| Title |
|---|
| "一种基于SBT忆阻器荷控模型的混沌电路";左鹏 等;《2017中国自动化大会（CAC2017）暨国际智能制造创新大会（CIMIC2017）论文集》;20180228;第375-378页 * |
| "基于单T网络的忆阻混沌电路";陈菊芳 等;《物理实验》;20180620;第38卷(第6期);第20-25页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110147597A (en) | 2019-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109829194B (en) | Absolute value magnetic control memristor equivalent simulation circuit | |
| CN110147597B (en) | Multi-stable-state magnetic control memristor equivalent simulation circuit | |
| CN103294872A (en) | Memristor equivalent circuit and construction method thereof | |
| CN110222425B (en) | Equivalent analog circuit with twin local active domain cubic polynomial magnetic control memristor | |
| CN107451380B (en) | Circuit for realizing exponential type charge control memory capacitor simulator | |
| CN103326704A (en) | Magnetic control memristor equivalent circuit | |
| CN108959837B (en) | Realization circuit of four-value memristor simulator | |
| CN110245421B (en) | Log absolute value local active memristor circuit model | |
| CN104702264A (en) | Programmable analog circuit based on memory resistor and operation method thereof | |
| CN105375914A (en) | Analog circuit for realizing characteristics of memory inductor | |
| CN109840365B (en) | Active memristor simulator | |
| CN110598371A (en) | Three-value local active memristor simulator | |
| CN111079365A (en) | Arc tangent trigonometric function memristor circuit model | |
| CN105373679A (en) | Analog circuit for realizing capacitance characteristic of capacitor with memory function | |
| CN109885858B (en) | Equivalent analog circuit of secondary curve memristor | |
| CN110175384B (en) | Secondary smooth flow control memristor simulation circuit | |
| CN109766643B (en) | Circuit model of three-value memristor | |
| CN209168107U (en) | A kind of circuit model of three values memristor | |
| CN109670221B (en) | Cubic nonlinear magnetic control memristor circuit composed of fractional order capacitors | |
| CN110728099B (en) | Charge control memory capacitor simulator circuit | |
| CN110110494B (en) | Equivalent analog circuit of resistor is recalled to two local active absolute value magnetic controls | |
| CN110198164B (en) | Absolute value flow control memristor simulation circuit | |
| CN114841112A (en) | Memory coupler equivalent analog circuit and electronic equipment | |
| CN211506501U (en) | Floating-ground magnetic control memristor simulator | |
| CN110728100B (en) | Equivalent analog circuit of segmented voltage-controlled memristor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |