CN110601695A - High-precision dynamic comparator - Google Patents

High-precision dynamic comparator Download PDF

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CN110601695A
CN110601695A CN201910856644.3A CN201910856644A CN110601695A CN 110601695 A CN110601695 A CN 110601695A CN 201910856644 A CN201910856644 A CN 201910856644A CN 110601695 A CN110601695 A CN 110601695A
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dynamic
stage
clock signal
circuit
tube
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CN110601695B (en
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李兴平
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Chengdu Rui Core Micro Polytron Technologies Inc
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Chengdu Rui Core Micro Polytron Technologies Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a high-precision dynamic comparator, and relates to the technical field of integrated circuits. The high-precision dynamic comparator comprises a latch circuit, a sequential logic circuit and at least two stages of dynamic pre-amplifying circuits, wherein the sequential logic circuit and the at least two stages of dynamic pre-amplifying circuits are mutually connected; a first-stage dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits receives the voltage to be compared and amplifies the voltage to be compared according to a first clock signal sent by the sequential logic circuit; the next stage of dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits amplifies an input signal according to a clock signal sent by the sequential logic circuit, wherein the input signal is a voltage to be compared after the previous stage of dynamic pre-amplifying circuit is preprocessed; the latch circuit receives the output signal processed by the last stage of dynamic pre-amplifying circuit, processes the output signal according to the latch clock signal sent by the sequential logic circuit and outputs a comparison result. The invention adopts a cascade structure of multi-stage dynamic preamplification and latching, and realizes high comparison precision and no static power consumption.

Description

High-precision dynamic comparator
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-precision dynamic comparator.
Background
In portable and internet of things application scenarios, a low-power-consumption high-precision SAR ADC (Successive approximation Analog-to-Digital Converter) has become a popular direction of research, and as a comparator of a core circuit of the SAR ADC, higher requirements are provided for power consumption and precision of the SAR ADC.
In the prior art, a dynamic comparator is high in speed and free of static power consumption, but has low resolution, and is generally used for a low-and-medium-resolution SAR ADC; the accuracy of the static comparator is usually high, but there is static power consumption in the circuit, which is generally adopted in the high resolution SAR ADC.
As shown in fig. 1, the dynamic comparator in the prior art generally adopts a structure of a one-stage dynamic pre-amplifying circuit pre _ dcomp and a latch, but due to the limitation of noise and gain, the dynamic comparator is generally only used for sar adc with a resolution below 12bit, and it is difficult to achieve higher precision. As shown in fig. 2, a static comparator in the prior art is generally composed of two stages of static pre-amplifying circuits pre _ amp1, pre _ amp2 and latch, and the static comparator is easy to realize higher resolution, but the comparator has static power consumption and is not suitable for low power consumption application.
Disclosure of Invention
The invention mainly aims to provide a high-precision dynamic comparator, aiming at realizing a high-precision comparator with low power consumption.
In order to achieve the above object, the present invention provides a high-precision dynamic comparator, which comprises a latch circuit, a sequential logic circuit and at least two stages of dynamic pre-amplifying circuits, wherein the sequential logic circuit and the at least two stages of dynamic pre-amplifying circuits are connected with each other;
a first-stage dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits receives a voltage to be compared, and amplifies the voltage to be compared according to a first clock signal sent by the sequential logic circuit; the next-stage dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits amplifies an input signal according to a clock signal sent by the sequential logic circuit, wherein the input signal is the voltage to be compared after the previous-stage dynamic pre-amplifying circuit is preprocessed;
the latch circuit receives the output signal processed by the last stage of dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits, processes the output signal according to the latch clock signal sent by the sequential logic circuit and outputs a comparison result.
Preferably, the first stage dynamic pre-amplification circuit includes a first PMOS transistor and a second PMOS transistor that receive the voltage to be compared, and further includes a third PMOS transistor connected to a power supply voltage, where the third PMOS transistor is connected to the first PMOS transistor and the second PMOS transistor through a first resistor; the first PMOS tube is grounded through a first capacitor, and the second PMOS tube is grounded through a second capacitor;
the first PMOS tube is also connected with a first NMOS tube and a second NMOS tube, and the first NMOS tube and the second NMOS tube are respectively grounded; the first capacitor and the second capacitor are connected with a third NMOS tube; the second PMOS tube is connected with a fourth NMOS tube, and the fourth NMOS tube is grounded.
Preferably, the source of the first PMOS transistor is connected to the drain of the third PMOS transistor through a first resistor, the drain of the first PMOS transistor is grounded through a first capacitor, and the gate of the first PMOS transistor is connected to a first voltage of the voltages to be compared; the source electrode of the second PMOS tube is connected to the drain electrode of the third PMOS tube through a first resistor, the drain electrode of the second PMOS tube is grounded through a second capacitor, and the grid electrode of the second PMOS tube is connected to a second voltage in the voltages to be compared; the source electrode of the third PMOS tube is connected to a power supply, and the grid electrode of the third PMOS tube receives the first clock signal;
the drain electrode of the first NMOS tube is connected to the source electrode of the first PMOS tube, the grid electrode of the first NMOS tube receives the first clock signal, and the source electrode of the first NMOS tube is grounded; the drain electrode of the second NMOS tube is connected to the drain electrode of the first PMOS tube, the grid electrode of the second NMOS tube receives the first clock signal, and the source electrode of the second NMOS tube is grounded; the source electrode of the third NMOS tube is connected to the drain electrode of the first PMOS tube and the first capacitor, and the drain electrode of the third NMOS tube is connected to the drain electrode of the second PMOS tube and the second capacitor; the drain electrode of the fourth NMOS tube is connected to the drain electrode of the second PMOS tube, the grid electrode of the fourth NMOS tube receives the first clock signal, and the source electrode of the fourth NMOS tube is grounded.
Preferably, each stage of the at least two stages of dynamic pre-amplification circuits has the same structure as the first stage of dynamic pre-amplification circuit.
Preferably, the at least two stages of dynamic pre-amplification circuits further include a second stage of dynamic pre-amplification circuit, and the structure of the second stage of dynamic pre-amplification circuit is the same as that of the first stage of dynamic pre-amplification circuit;
and the second-stage dynamic pre-amplifying circuit receives a second clock signal so as to pre-amplify the voltage to be compared, which is processed by the first-stage dynamic pre-amplifying circuit.
Preferably, a gate of the third NMOS transistor in the first stage dynamic pre-amplifier circuit receives a first pre-clock sent by the sequential logic circuit, and the first clock signal is delayed by a first time from the first pre-clock and inverted, so that the third NMOS transistor is turned off before the first PMOS transistor and the second PMOS transistor are turned on.
Preferably, the second-stage dynamic pre-amplification circuit further receives a second pre-clock sent by the sequential logic circuit, and the second pre-clock delays a second time than the first clock signal to perform inversion, so that the second-stage dynamic pre-amplification circuit operates after the first-stage dynamic pre-amplification circuit completes operation; the second clock signal is inverted with a third time delay from the second pre-clock.
Preferably, the latch clock signal is inverted with a fourth time delay from the second clock signal.
The technical scheme of the invention adopts a cascade structure of the multistage dynamic preamplifier circuit and the latch circuit, and then the multistage dynamic preamplifier circuit is controlled by sending the preset time sequence through the time sequence logic circuit, thereby realizing higher comparison precision without static power consumption and providing a solution with low power consumption for the SAR ADC with medium and high precision.
Drawings
FIG. 1 is a schematic diagram of a prior art dynamic comparator;
FIG. 2 is a schematic diagram of a prior art static comparator;
FIG. 3 is a schematic diagram of a high precision dynamic comparator according to the present invention;
FIG. 4 is a schematic diagram of the circuit of the high precision dynamic comparator of the present invention;
FIG. 5 is a timing diagram of clock signals according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a sequential logic circuit of the high precision dynamic comparator according to the present invention;
fig. 7 is a schematic diagram of further embodiments of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
A high-precision dynamic comparator, as shown in FIG. 3, comprises a latch circuit, a sequential logic circuit and at least two stages of dynamic pre-amplifying circuits, wherein the sequential logic circuit and the at least two stages of dynamic pre-amplifying circuits are connected with each other;
a first-stage dynamic pre-amplifying circuit pre _ dcomp1 in the at least two stages of dynamic pre-amplifying circuits receives voltages (VIPN and VINN) to be compared, and amplifies the voltages to be compared according to a first clock signal CLK1 sent by the sequential logic circuit; the next-stage dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits amplifies an input signal according to a clock signal sent by the sequential logic circuit, wherein the input signal is the voltage to be compared after the previous-stage dynamic pre-amplifying circuit is preprocessed;
the latch circuit receives the output signal processed by the last stage of dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits, and outputs comparison results (Q and QN) after processing the output signal according to a latch clock signal CLK3 sent by the sequential logic circuit. In a specific embodiment, the comparison result output by the latch circuit is either high or low.
As shown in fig. 4, the first stage dynamic pre-amp circuit pre _ dcomp1 includes a first PMOS transistor PM1 and a second PMOS transistor PM2 for receiving the voltage to be compared, and further includes a third PMOS transistor PM3 connected to the supply voltage vdd, where the third PMOS transistor PM3 is connected to the first PMOS transistor PM1 and the second PMOS transistor PM2 through a first resistor R1; the first PMOS transistor PM1 is grounded vss through a first capacitor C1, and the second PMOS transistor PM2 is grounded vss through a second capacitor C2;
the first PMOS transistor PM1 is further connected to a first NMOS transistor NM1 and a second NMOS transistor NM2, and the first NMOS transistor NM1 and the second NMOS transistor NM2 are respectively grounded vss; the first capacitor C1 and the second capacitor C2 are connected with a third NMOS transistor NM 3; the second PMOS transistor PM2 is connected to a fourth NMOS transistor NM4, and the fourth NMOS transistor NM4 is grounded vss.
Specifically, the values of the first capacitor C1 and the second capacitor C2 are equal.
The first stage dynamic pre-amplifier circuit pre _ dcomp1 is current limited by a first resistor R1, and the effective charging time of the first capacitor C1 and the second capacitor C2 by the circuit can be adjusted to increase the gain of the first stage dynamic pre-amplifier circuit pre _ dcomp 1.
As shown in fig. 4, the source of the first PMOS transistor PM1 is connected to the drain of the third PMOS transistor PM3 through a first resistor R1, the drain is connected to ground vss through a first capacitor C1, and the gate is connected to a first voltage VINN of the voltages to be compared; the source of the second PMOS transistor PM2 is connected to the drain of the third PMOS transistor PM3 through a first resistor R1, the drain is grounded vss through a second capacitor C2, and the gate is connected to a second voltage VINP of the voltages to be compared; the source of the third PMOS transistor PM3 is connected to the power vdd, and the gate receives the first clock signal CLK 1;
the drain of the first NMOS transistor NM1 is connected to the source of the first PMOS transistor PM1, the gate thereof receives the first clock signal CLK1, and the source thereof is grounded vss; the drain of the second NMOS transistor NM2 is connected to the drain of the first PMOS transistor PM1, the gate thereof receives the first clock signal CLK1, and the source thereof is grounded vss; the source of the third NMOS transistor NM3 is connected to the drain of the first PMOS transistor PM1 and the first capacitor C1, and the drain is connected to the drain of the second PMOS transistor PM2 and the second capacitor C2; the drain of the fourth NMOS transistor NM4 is connected to the drain of the second PMOS transistor PM2, the gate thereof receives the first clock signal CLK1, and the source thereof is grounded vss.
As shown in fig. 3 and4, the at least two-stage dynamic pre-amplifying circuit further includes a second-stage dynamic pre-amplifying circuit pre _ dcomp2, and the structure of the second-stage dynamic pre-amplifying circuit pre _ dcomp2 is the same as that of the first-stage dynamic pre-amplifying circuit pre _ dcomp 1; the second stage dynamic pre-amplifying circuit pre _ dcomp2 receives a second clock signal CLK2 to pre-amplify the voltage to be compared processed by the first stage dynamic pre-amplifying circuit pre _ dcomp 1.
As shown in fig. 4, the second stage dynamic pre-amp circuit pre _ dcomp2 includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM 5; the gate of the fourth PMOS transistor PM4 is connected to the drain of the second PMOS transistor PM2, and is configured to receive the second voltage VON1 amplified by the first stage dynamic pre-amp circuit pre _ dcomp 1; the drain of the fifth PMOS transistor PM5 is connected to the drain of the first PMOS transistor PM1, and is configured to receive the first voltage VOP1 amplified by the first stage dynamic pre-amp circuit pre _ dcomp 1;
the sources of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are connected to the drain of the sixth PMOS transistor PM6 through the second resistor R2, the source of the sixth PMOS transistor PM6 is connected to the power voltage vdd, and the gate of the sixth PMOS transistor PM6 is connected to the second clock signal CLK 2. The source of the fourth PMOS transistor PM4 is connected to the drain of the fifth NMOS transistor NM5, the source of the fifth NMOS transistor NM5 is grounded vss, and the gate is connected to the second clock signal CLK 2; the drain of the fourth PMOS transistor PM4 is connected to the drain of the sixth NMOS transistor NM6, the source of the seventh NMOS transistor NM7, and one end of the third capacitor C3, the other end of the third capacitor C3 is grounded vss, the source of the sixth NMOS transistor NM6 is grounded vss, and the gate is connected to the second clock signal CLK 2; the source of the seventh NMOS transistor NM7 is further connected to one end of the third capacitor C3, the drain is connected to the drain of the fifth PMOS transistor PM5, and the gate is connected to the second PRE-clock CLK2_ PRE. The drain of the fifth PMOS transistor PM5 is connected to the drain of the eighth NMOS transistor NM8 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, the source of the eighth NMOS transistor NM8 is grounded vss, and the gate is connected to the second clock signal CLK 2. The drain of the fourth PMOS transistor PM4 outputs the amplified second voltage VOP2 and the drain of the fifth PMOS transistor PM5 outputs the amplified first voltage VON 2.
The latch circuit receives the first voltage VON2 after the second stage dynamic pre-amplifying circuit pre _ dcomp2 outputs the amplified voltage VON2 and the second voltage VOP2 after the second stage dynamic pre-amplifying circuit outputs the amplified voltage VOP2, and latches the amplified voltage VON2 according to a latch clock signal CLK3 sent by the sequential logic circuit to output the result.
As shown in fig. 5, the gate of the third NMOS tube NM3 in the first stage dynamic PRE-amp circuit PRE _ dcomp1 receives a first PRE-clock CLK1_ PRE sent by the sequential logic circuit, and the first clock signal CLK1 is delayed from the first PRE-clock CLK1_ PRE by a first time TD1 to flip, so that the third NMOS tube NM3 is turned off before the first PMOS tube PM1 and the second PMOS tube PM2 are turned on. The third NMOS 3 is turned off before the first stage dynamic pre-amplifier circuit pre _ dcomp1 starts to charge the first capacitor C1 and the second capacitor C2, which is beneficial to reducing the differential mode noise across the first capacitor C1 and the second capacitor C2.
As shown in fig. 5, the second stage dynamic PRE-amplifying circuit PRE _ dcomp2 further receives a second PRE-clock CLK2_ PRE sent by the sequential logic circuit, where the second PRE-clock CLK2_ PRE is delayed from the first clock signal CLK1 by a second time TD2 and is inverted, so that the second stage dynamic PRE-amplifying circuit PRE _ dcomp2 operates after the first stage dynamic PRE-amplifying circuit PRE _ dcomp1 completes its operation; the second clock signal CLK2 is delayed from the second preamble clock CLK2_ PRE by a third time TD3 to flip. The latching clock signal CLK3 toggles with a delay of a fourth time TD4 from the second clock signal CLK 2. Specifically, the first time TD1 and the third time TD3 are greater than 0 and as small as possible, i.e., the front-end clock only needs to be turned on a short time before the clock signal.
The second time TD2 can be adjusted according to the equivalent input noise of the second stage dynamic pre-amplifying circuit pre _ dcomp2, when the second stage dynamic pre-amplifying circuit pre _ dcomp2 is turned on, the first stage dynamic pre-amplifying circuit pre _ dcomp1 needs to amplify the voltage to be compared to exceed the equivalent input noise of the second stage dynamic pre-amplifying circuit pre _ dcomp 2.
The fourth time TD4 can be set according to the total equivalent input noise of the latch circuit, and when the latch circuit is turned on, the voltage to be compared amplified by the first stage dynamic pre-amp circuit pre _ dcomp1 and the second stage dynamic pre-amp circuit pre _ dcomp2 needs to be greater than the total equivalent input noise of the third stage latch circuit. When the second stage dynamic pre-amp circuit pre _ dcomp2 outputs the amplified voltage, it can be turned on to start the latch circuit.
In a specific embodiment, after the latch circuit is turned on for the fifth time TD5, the first PRE-clock CLK1_ PRE, the first clock signal CLK1, the second PRE-clock CLK2_ PRE, and the second clock signal CLK2 are again inverted to reset the first stage dynamic PRE-amplifier circuit PRE _ dcomp1 and the second stage dynamic PRE-amplifier circuit PRE _ dcomp2, thereby reducing the power consumption of the circuit. The fifth time TD5 can be set according to the working time of the latch circuit, and when the latch is completed, the circuit can enter the reset state.
Specifically, the input clock signal CLK _ IN is input to the sequential logic circuit to cause the sequential logic circuit to generate the first PRE-clock CLK1_ PRE, the first clock signal CLK1, the second PRE-clock CLK2_ PRE, and the second clock signal CLK2 and the latch clock signal CLK3, the first PRE-clock CLK1_ PRE being inverted by a sixth time TD 6. Specifically, the sixth time TD6 is greater than 0 and as small as possible.
Specifically, the sequential logic circuit may be configured according to the timing diagram shown IN fig. 5, AND fig. 6 shows one embodiment of the sequential logic circuit, IN which the input clock signal CLK _ IN sequentially passes through a sixth delay device TD6, a first delay device TD1, a second delay device TD2, a third delay device TD3, a fourth delay device TD4, a fifth delay device TD5 AND an inverter INV AND is anded with the input clock signal CLK _ IN to obtain a clock AND operation result CLK _ AND, AND the clock AND operation result CLK _ IN AND the input clock signal CLK _ IN delayed by the sixth delay device TD6 are NAND-operated to obtain a NAND operation result NAND1 to obtain a first PRE-clock CLK1_ PRE; NAND operation NAND2 is performed on the clock AND operation result CLK _ AND the input clock signal CLK _ IN delayed by the sixth delay device TD6 AND the first delay device TD1 to obtain a first clock signal CLK 1; NAND operation NAND3 is carried out on the clock AND operation result CLK _ AND the input clock signal CLK _ IN delayed by a sixth delay device TD6, a first delay device TD1 AND a second delay device TD2 to obtain a second front clock CLK2_ PRE; the NAND operation on the clock AND operation result CLK _ AND the input clock signal CLK _ IN delayed by the sixth delay device TD6, the first delay device TD1, the second delay device TD2, AND the third delay device TD3 is performed 4 to obtain the second clock signal CLK 2. The input clock signal CLK _ IN sequentially passes through the sixth delay device TD6, the first delay device TD1, the second delay device TD2, the third delay device TD3 and the fourth delay device TD4 to obtain the latch clock signal CLK 3. When the input clock signal CLK _ IN is high, the sequential logic circuit begins to operate.
Specifically, the time lengths delayed by the first time delay TD1, the second time delay TD2, the third time delay TD3, the fourth time delay TD4, the fifth time delay TD5 and the sixth time delay TD6 are sequentially a first time TD1, a second time TD2, a third time TD3, a fourth time TD4, a fifth time TD5 and a sixth time TD 6.
The working principle of the embodiment of the invention is as follows: before the comparator starts to operate, the input clock signal CLK _ IN is at a low level, and at this time, the first stage dynamic pre-amp circuit pre _ dcomp1, the second stage dynamic pre-amp circuit pre _ dcomp2, and the latch circuit are all IN the reset phase, and the voltages at the nodes VOP1, VON1, VOP2, VON2, Q, QN are set to 0. VINN and VINP are the voltages to be compared.
When the input clock signal CLK _ IN is at a high level, the sequential logic circuit sequentially outputs the first PRE-clock signal CLK1_ PRE, the first clock signal CLK1, the second PRE-clock signal CLK2_ PRE, the second clock signal CLK2, the latch clock signal CLK3 to the first stage dynamic PRE-amp circuit PRE _ dcomp1, the second stage dynamic PRE-amp circuit PRE _ dcomp2, and the latch circuit IN a timing diagram.
First, the first front clock CLK1_ PRE flips (changes from high level to low level), and the third NMOS transistor NM3 turns off. The first clock signal CLK1 is inverted, the first stage dynamic pre-amplifying circuit pre _ dcomp1 pre-amplifies an input voltage to be compared, the third PMOS transistor PM3 is turned on, the first NMOS transistor NM1, the second NMOS transistor NM2 and the fourth NMOS transistor NM4 are turned off, the first PMOS transistor PM1 and the second PMOS transistor PM2 are biased by the voltage to be compared, at this time, the first stage dynamic pre-amplifying circuit pre _ dcomp1 enters a pre-amplifying stage, and a current passes through the third PMOS transistor PM3, the first resistor R1, the first PMOS transistor PM1 and the second PMOS transistor PM2 to charge the first capacitor C1 and the second capacitor C2 respectively.
Since the first voltage VINN and the second voltage VINP of the voltages to be compared are not equal, the charging speeds of the first capacitor C1 and the second capacitor C2 may be different, and the gain of the output and the input may be represented by equation one:
(one) of the two types of the raw materials,
wherein g ism0Is an approximate transconductance of the first PMOS transistor PM1 or the second PMOS transistor PM2,a duration of a low level in one clock cycle of the first clock signal CLK 1;
the maximum value of the effective pre-amplification time can be calculated by equation two:
(II) performing a second step of,
wherein VCMINFor common mode of the voltages to be compared, VthIs the threshold voltage, I, of the first and second PMOS transistors PM1 and PM2bThe average current flowing through the first resistor R1 can be represented by the equationAnd (4) calculating.
The maximum gain of the effective pre-amplification can be calculated by equation three:
(III);
in thatThe equivalent output noise at a time can be calculated by equation four:
(IV) performing a first step of performing a second step of performing a third step of,
where k is Boltzmann's constant, T is the thermodynamic temperature, gamma is a constant, C0Is the value of the first capacitance C1 or the second capacitance C2;
the optimal equivalent input noise can be obtained by substituting equation two into equation four, as equation five:
(V);
as can be seen from equation five, the capacitance C is increased0Or to extend the effective pre-amplification time(i.e. decrease I)b) The comparator equivalent input noise can be reduced.
Then, the second PRE-clock signal CLK2_ PRE and the second clock signal CLK2 sequentially flip, and the second stage dynamic PRE-amp circuit PRE _ dcomp2 starts to operate in the same manner as the first stage dynamic PRE-amp circuit PRE _ dcomp 1.
Finally, the latch clock signal CLK3 is inverted, and the amplified output of the second stage dynamic pre-amp circuit pre _ dcomp2 is latched as a high-low output by the latch circuit.
According to the embodiment of the invention, the mode that the first-stage dynamic pre-amplifying circuit pre _ dcomp1 works first and then the second-stage dynamic pre-amplifying circuit pre _ dcomp2 is started to work is adopted, so that the equivalent input noise is reduced under the condition of maintaining the gain, and the precision of the comparator is improved.
In some embodiments, each stage of the at least two stages of dynamic pre-amplifying circuits has the same structure as the first stage of dynamic pre-amplifying circuit pre _ dcomp 1.
In other embodiments, as shown in fig. 7, the at least two stages of dynamic preamplifiers include a first stage dynamic preamplification circuit pre _ dcomp1, a second stage dynamic preamplification circuit pre _ dcomp2, and a third stage dynamic preamplification circuit pre _ dcomp 3. The precision of the comparator can be improved by adding one more stage of amplification.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.

Claims (8)

1. A high-precision dynamic comparator comprises a latch circuit and is characterized by further comprising a sequential logic circuit and at least two stages of dynamic pre-amplifying circuits which are connected with each other;
a first-stage dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits receives a voltage to be compared, and amplifies the voltage to be compared according to a first clock signal sent by the sequential logic circuit; the next-stage dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits amplifies an input signal according to a clock signal sent by the sequential logic circuit, wherein the input signal is the voltage to be compared after the previous-stage dynamic pre-amplifying circuit is preprocessed;
the latch circuit receives the output signal processed by the last stage of dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits, processes the output signal according to the latch clock signal sent by the sequential logic circuit and outputs a comparison result.
2. The high-precision dynamic comparator according to claim 1, wherein the first stage dynamic pre-amplifying circuit comprises a first PMOS transistor and a second PMOS transistor for receiving the voltage to be compared, and further comprises a third PMOS transistor connected to a power supply voltage, and the third PMOS transistor is connected to the first PMOS transistor and the second PMOS transistor through a first resistor; the first PMOS tube is grounded through a first capacitor, and the second PMOS tube is grounded through a second capacitor;
the first PMOS tube is also connected with a first NMOS tube and a second NMOS tube, and the first NMOS tube and the second NMOS tube are respectively grounded; the first capacitor and the second capacitor are connected with a third NMOS tube; the second PMOS tube is connected with a fourth NMOS tube, and the fourth NMOS tube is grounded.
3. The high-precision dynamic comparator according to claim 2, wherein the source of the first PMOS transistor is connected to the drain of the third PMOS transistor through a first resistor, the drain of the first PMOS transistor is grounded through a first capacitor, and the gate of the first PMOS transistor is connected to a first voltage of the voltages to be compared; the source electrode of the second PMOS tube is connected to the drain electrode of the third PMOS tube through a first resistor, the drain electrode of the second PMOS tube is grounded through a second capacitor, and the grid electrode of the second PMOS tube is connected to a second voltage in the voltages to be compared; the source electrode of the third PMOS tube is connected to a power supply, and the grid electrode of the third PMOS tube receives the first clock signal;
the drain electrode of the first NMOS tube is connected to the source electrode of the first PMOS tube, the grid electrode of the first NMOS tube receives the first clock signal, and the source electrode of the first NMOS tube is grounded; the drain electrode of the second NMOS tube is connected to the drain electrode of the first PMOS tube, the grid electrode of the second NMOS tube receives the first clock signal, and the source electrode of the second NMOS tube is grounded; the source electrode of the third NMOS tube is connected to the drain electrode of the first PMOS tube and the first capacitor, and the drain electrode of the third NMOS tube is connected to the drain electrode of the second PMOS tube and the second capacitor; the drain electrode of the fourth NMOS tube is connected to the drain electrode of the second PMOS tube, the grid electrode of the fourth NMOS tube receives the first clock signal, and the source electrode of the fourth NMOS tube is grounded.
4. The high precision dynamic comparator according to claim 3, wherein each stage of the at least two stages of dynamic pre-amplifying circuits has the same structure as the first stage of dynamic pre-amplifying circuit.
5. The high precision dynamic comparator according to claim 3, wherein the at least two stages of dynamic pre-amplifying circuits further comprise a second stage of dynamic pre-amplifying circuit, and the structure of the second stage of dynamic pre-amplifying circuit is the same as that of the first stage of dynamic pre-amplifying circuit;
and the second-stage dynamic pre-amplifying circuit receives a second clock signal so as to pre-amplify the voltage to be compared, which is processed by the first-stage dynamic pre-amplifying circuit.
6. The high-precision dynamic comparator according to claim 5, wherein a gate of the third NMOS transistor in the first stage dynamic pre-amplifying circuit receives a first pre-clock sent by the sequential logic circuit, and the first clock signal is delayed by a first time from the first pre-clock and inverted, so that the third NMOS transistor is turned off before the first PMOS transistor and the second PMOS transistor are turned on.
7. The high-precision dynamic comparator according to claim 6, wherein the second stage dynamic pre-amplifying circuit further receives a second pre-clock sent by the sequential logic circuit, and the second pre-clock is delayed by a second time from the first clock signal to be inverted, so that the second stage dynamic pre-amplifying circuit operates after the first stage dynamic pre-amplifying circuit completes its operation; the second clock signal is inverted with a third time delay from the second pre-clock.
8. The high accuracy dynamic comparator according to claim 7, wherein the latching clock signal is inverted with a fourth time delay from the second clock signal.
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