WO2016206123A1

WO2016206123A1 - Cmos master and slave sample and hold circuit

Info

Publication number: WO2016206123A1
Application number: PCT/CN2015/082601
Authority: WO
Inventors: 胡蓉彬; 胡刚毅; 蒋和全; 王永禄; 张正平; 付东兵; 王健安; 王育新; 周述涛
Original assignee: 中国电子科技集团公司第二十四研究所
Priority date: 2015-06-24
Filing date: 2015-06-29
Publication date: 2016-12-29
Also published as: CN104901699A; CN104901699B

Abstract

A CMOS master and slave sample and hold circuit comprises: an input buffer amplifier (1) configured to receive and buffer an externally input analog signal and drive a master sample and hold circuit (2); the master sample and hold circuit (2), configured to sample and hold an output signal of the input buffer amplifier (1) and output a first sampled signal; an intermediate buffer amplifier (3), configured to receive and buffer the first sampled signal and drive a slave sample and hold circuit (4); the slave sample and hold circuit (4), configured to sample and hold an output signal of the intermediate buffer amplifier (3) and output a second sampled signal; a clock circuit (5), configured to receive an external clock signal, and generate a pair of non-overlapping first internal clock signal and second internal clock signal, wherein the first internal clock signal is provided to the master sample and hold circuit (2) as a clock signal, and the second internal clock signal is provided to the slave sample and hold circuit (4) as a clock signal. The non-overlapping first internal clock signal and second internal clock signal are provided to the master and slave sample and hold circuits (2, 4) as the clock signals, respectively, so as to hold a signal constant in a complete clock cycle.

Description

一种CMOS主从式采样保持电路CMOS master-slave sample-and-hold circuit

技术领域Technical field

本发明属于模拟/混合信号集成电路领域，具体涉及一种CMOS主从式采样保持电路。The invention belongs to the field of analog/mixed signal integrated circuits, and in particular relates to a CMOS master-slave sample-and-hold circuit.

背景技术Background technique

CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)工艺由于极高的集成度和极低的加工价格，普遍用于模拟和混合信号集成电路设计。CMOS采样保持电路广泛应用于模数转换器前端，它能采样模拟信号瞬时值并将其保持一段时间。在这段时间里，模数转换器将处理一个不变的信号，这大大提高了模数转换器的精度和准确性。CMOS (Complementary Metal Oxide Semiconductor) processes are commonly used in analog and mixed-signal integrated circuit designs due to their high integration and low processing price. CMOS sample-and-hold circuits are widely used in analog-to-digital converter front ends to sample the instantaneous value of an analog signal and hold it for a period of time. During this time, the analog-to-digital converter will process a constant signal, which greatly improves the accuracy and accuracy of the analog-to-digital converter.

图1为现有技术中用于模数转换器前端的CMOS单级采样保持电路，包括一NMOS晶体管Ns，一采样电容Cd，NMOS晶体管Ns用作采样开关，其栅极连接时钟信号CLK，源极连接模拟信号SIN，漏极连接采样电容Cd上极板并输出信号SOUT，采样电容Cd下极板接地。图1中CMOS单级采样保持电路的工作原理如下：1 is a CMOS single-stage sample-and-hold circuit for an analog-to-digital converter front end, comprising an NMOS transistor Ns, a sampling capacitor Cd, an NMOS transistor Ns serving as a sampling switch, and a gate connected to a clock signal CLK, a source The pole is connected to the analog signal SIN, the drain is connected to the upper plate of the sampling capacitor Cd and the signal SOUT is output, and the lower plate of the sampling capacitor Cd is grounded. The working principle of the CMOS single-stage sample-and-hold circuit in Figure 1 is as follows:

请参考图2，当时钟信号CLK为高电平时，NMOS晶体管Ns开启，连接采样电容Cd的上极板SOUT到模拟信号SIN，采样电容Cd的上极板SOUT跟随模拟信号SIN。当时钟信号CLK为低电平时，NMOS晶体管Ns截止，断开采样电容Cd的上极板SOUT与模拟信号SIN间的电连接。由于采样电容Cd具有电荷保持能力，采样电容Cd的上极板将采样并保持时钟下降沿处的模拟信号瞬时值。Referring to FIG. 2, when the clock signal CLK is at a high level, the NMOS transistor Ns is turned on, and the upper plate SOUT of the sampling capacitor Cd is connected to the analog signal SIN, and the upper plate SOUT of the sampling capacitor Cd follows the analog signal SIN. When the clock signal CLK is at a low level, the NMOS transistor Ns is turned off, and the electrical connection between the upper plate SOUT of the sampling capacitor Cd and the analog signal SIN is turned off. Since the sampling capacitor Cd has charge retention capability, the upper plate of the sampling capacitor Cd will sample and maintain the instantaneous value of the analog signal at the falling edge of the clock.

但是，本发明的发明人经过研究发现，现有技术的CMOS单级采样保持电路，只能在半个时钟周期内保持信号不变，并且还受到电荷注入、非线型导通电阻等非理想效应影响，因而已经不能满足现在高速高精度模数转换器需要。However, the inventors of the present invention have found through research that the prior art CMOS single stage The sample-and-hold circuit can keep the signal unchanged for half a clock cycle, and is also affected by non-ideal effects such as charge injection and non-linear on-resistance, so it cannot meet the needs of high-speed and high-precision analog-to-digital converters.

发明内容Summary of the invention

针对现有技术的CMOS单级采样保持电路，只能在半个时钟周期内保持信号不变的技术问题，本发明提供一种新型的CMOS主从式采样保持电路。The present invention provides a novel CMOS master-slave sample-and-hold circuit for the prior art CMOS single-stage sample-and-hold circuit that maintains the signal constant for only half a clock cycle.

为了实现上述目的，本发明采用如下技术方案：In order to achieve the above object, the present invention adopts the following technical solutions:

一种CMOS主从式采样保持电路，包括：A CMOS master-slave sample-and-hold circuit includes:

输入缓冲放大器，适于接收和缓冲外部输入的模拟信号，并驱动主采样保持电路；An input buffer amplifier adapted to receive and buffer an externally input analog signal and drive the main sample and hold circuit;

主采样保持电路，适于采样保持输入缓冲放大器的输出信号，并输出第一采样信号；a main sample and hold circuit adapted to sample and hold an output signal of the input buffer amplifier and output a first sampling signal;

级间缓冲放大器，适于接收和缓冲第一采样信号，并驱动从采样保持电路；An interstage buffer amplifier adapted to receive and buffer the first sampled signal and drive the slave sample and hold circuit;

从采样保持电路，适于采样保持级间缓冲放大器的输出信号，并输出第二采样信号，且第二采样信号为所述CMOS主从式采样保持电路的最终输出信号；The sample-and-hold circuit is adapted to sample and hold an output signal of the interstage buffer amplifier, and output a second sampling signal, and the second sampling signal is a final output signal of the CMOS master-slave sample-and-hold circuit;

时钟电路，适于接收外部时钟信号，产生第一内部时钟信号和第二内部时钟信号，所述第一内部时钟信号和第二内部时钟信号为一对非交叠的时钟信号，且第一内部时钟信号用于给主采样保持电路提供时钟信号，第二内部时钟信号用于给从采样保持电路提供时钟信号。a clock circuit adapted to receive an external clock signal to generate a first internal clock signal and a second internal clock signal, the first internal clock signal and the second internal clock signal being a pair of non-overlapping clock signals, and the first internal The clock signal is used to provide a clock signal to the main sample and hold circuit, and the second internal clock signal is used to provide a clock signal to the sample and hold circuit.

本发明提供的CMOS主从式采样保持电路中，时钟电路产生一对非交叠的第一内部时钟信号和第二内部时钟信号，第一内部时钟信号用于给主采样保持电路提供时钟信号，第二内部时钟信号用于给从采样保持电路提供时钟信号，因而主采样保持电路和从保持采样电路共两级保持电路能够在整个时钟周期内保持信号不变；同时，还包括一个输入缓冲放大器用于接收和缓冲外部输入的模拟信号，一个级间缓冲放大器被***到两级采样保持电路之间，用于隔离主采样保持电路和从采样保持电路的采样电容，防止电荷分享效应发生。本发明应用于模数转换器前端，能大大提高模数转换器性能。In the CMOS master-slave sample-and-hold circuit provided by the present invention, the clock circuit generates a pair of non-overlapping first internal clock signals and a second internal clock signal, and the first internal clock signal is used to provide a clock signal to the main sample and hold circuit. The second internal clock signal is used to give The sample-and-hold circuit provides a clock signal, so that the main sample-and-hold circuit and the hold-sampling circuit maintain a two-stage hold circuit capable of maintaining the signal for the entire clock cycle; and an input buffer amplifier for receiving and buffering the external input. Signal, an interstage buffer amplifier is inserted between the two stages of sample and hold circuits to isolate the main sample and hold circuit and the sample capacitor from the sample and hold circuit to prevent charge sharing effects. The invention is applied to the front end of an analog-to-digital converter, which can greatly improve the performance of the analog-to-digital converter.

进一步，所述输入缓冲放大器采用单端电路形式，包括第一NMOS晶体管和第二NMOS晶体管，所述第一NMOS晶体管为工作晶体管，其栅极接收外部输入的模拟信号，源极输出缓冲后的模拟信号，漏极连接电源VCC；所述第二NMOS晶体管为偏置晶体管，其漏极连接第一NMOS晶体管的源极，为第一NMOS晶体管提供偏置电流，源极接地，栅极连接第一偏置电压。Further, the input buffer amplifier is in the form of a single-ended circuit, including a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is a working transistor, and the gate thereof receives an externally input analog signal, and the source output is buffered. An analog signal, the drain is connected to the power supply VCC; the second NMOS transistor is a bias transistor, the drain thereof is connected to the source of the first NMOS transistor, the bias current is supplied to the first NMOS transistor, the source is grounded, and the gate is connected A bias voltage.

进一步，所述主采样保持电路和从采样保持电路均采用单端电路形式并具有相同的电路结构，包括采样开关和采样电容，所述采样电容的下极板接地，上极板连接采样开关的一端，采样开关的另一端连接输入信号，采样开关的控制端与内部时钟信号连接，且所述采样电容上极板信号作为主从采样保持电路的输出采样信号。Further, the main sample-and-hold circuit and the slave sample-and-hold circuit are both in the form of a single-ended circuit and have the same circuit structure, including a sampling switch and a sampling capacitor. The lower plate of the sampling capacitor is grounded, and the upper plate is connected to the sampling switch. At one end, the other end of the sampling switch is connected to the input signal, and the control end of the sampling switch is connected to the internal clock signal, and the upper plate signal of the sampling capacitor is used as the output sampling signal of the master-slave sampling and holding circuit.

进一步，所述采样开关为自举开关，包括第一反相器、第二反相器、第三反相器、第四反相器、第三NMOS晶体管、第四NMOS晶体管、第五NMOS晶体管、第六NMOS晶体管、第七NMOS晶体管、第一PMOS晶体管、第二PMOS晶体管、第三PMOS晶体管、电容器和主开关晶体管；所述主开关晶体管的源极连接输入信号，漏极连接所述采样电容的上极板，栅极同时连接第六NMOS晶体管、第七NMOS晶体管和第三PMOS晶体管的栅极，第一反相器的输入端连接内部时钟信号，输出端与第二反相器和第三反相器的输入端连接，第二反相器的输出端连接第三NMOS晶体管的源极,第三反相器的输出端连接第四反相器的输入端、第二PMOS晶体管和第五NMOS晶体管的栅极，第四反相器的输出端连接第四NMOS晶体管的栅极，第一反相器、第二反相器、第三反相器和第四反相器为CMOS静态逻辑门电路，由电源VCC供电，第三NMOS晶体管的栅极接电源VCC，漏极连接主开关晶体管的栅极和第一PMOS晶体管的漏极，第一PMOS晶体管的栅极连接第二PMOS晶体管、第五NMOS晶体管和第七NMOS晶体管的漏极，电容器的上极板连接第一PMOS晶体管的源极和第三PMOS晶体管的漏极，第三PMOS晶体管的源极连接电源VCC，电容器的下极板连接第五NMOS晶体管和第七NMOS晶体管的源极以及第四NMOS晶体管和第六NMOS晶体管的漏极，第四NMOS晶体管的源极接地，第六NMOS晶体管的源极与主开关晶体管的源极连接。Further, the sampling switch is a bootstrap switch, including a first inverter, a second inverter, a third inverter, a fourth inverter, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a capacitor, and a main switching transistor; a source of the main switching transistor is connected to an input signal, and a drain is connected to the sampling The upper plate of the capacitor is connected to the gates of the sixth NMOS transistor, the seventh NMOS transistor and the third PMOS transistor, and the input end of the first inverter is connected to the internal clock signal, the output terminal and the second inverter are The input end of the third inverter is connected, the output end of the second inverter is connected to the source of the third NMOS transistor, and the third inverter The output end is connected to the input end of the fourth inverter, the gates of the second PMOS transistor and the fifth NMOS transistor, and the output end of the fourth inverter is connected to the gate of the fourth NMOS transistor, the first inverter, the first The second inverter, the third inverter and the fourth inverter are CMOS static logic gate circuits, which are powered by the power supply VCC, the gate of the third NMOS transistor is connected to the power supply VCC, and the drain is connected to the gate of the main switching transistor and a drain of a PMOS transistor, a gate of the first PMOS transistor is connected to drains of the second PMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor, and an upper plate of the capacitor is connected to a source of the first PMOS transistor and a third PMOS a drain of the transistor, a source of the third PMOS transistor is connected to the power source VCC, a lower plate of the capacitor is connected to a source of the fifth NMOS transistor and the seventh NMOS transistor, and a drain of the fourth NMOS transistor and the sixth NMOS transistor, fourth The source of the NMOS transistor is grounded, and the source of the sixth NMOS transistor is connected to the source of the main switching transistor.

进一步，所述级间缓冲放大器采用单端电路形式，包括第八NMOS晶体管、第九NMOS晶体管、第一电阻器和第二电阻器，所述第八NMOS晶体管为工作晶体管，其栅极与主采样保持电路输出的第一采样信号连接，漏极输出缓冲后的第一采样信号，源极连接第一电阻器的一端，第一电阻器的另一端接地；所述第九NMOS晶体管为负载晶体管，其栅极连接第二偏置电压，漏极连接电源VCC，源极连接第二电阻器的一端，第二电阻器的另一端与第八NMOS晶体管的漏极连接。Further, the interstage buffer amplifier is in the form of a single-ended circuit, and includes an eighth NMOS transistor, a ninth NMOS transistor, a first resistor, and a second resistor, the eighth NMOS transistor being a working transistor, and a gate and a main The first sampling signal outputted by the sample-and-hold circuit is connected, the first sampling signal after the buffer is buffered, the source is connected to one end of the first resistor, and the other end of the first resistor is grounded; the ninth NMOS transistor is a load transistor The gate is connected to the second bias voltage, the drain is connected to the power source VCC, the source is connected to one end of the second resistor, and the other end of the second resistor is connected to the drain of the eighth NMOS transistor.

进一步，所述第八NMOS晶体管和第九NMOS晶体管的跨导相等，且所述第一电阻器和第二电阻器的阻值相等。Further, the transconductance of the eighth NMOS transistor and the ninth NMOS transistor are equal, and the resistances of the first resistor and the second resistor are equal.

进一步，所述时钟电路包括第一与非门、第二与非门、第五反相器、第六反相器、第七反相器和数字缓冲器，所述第五反相器和数字缓冲器的输入端接收外部时钟信号，第五反相器的输出端与第一与非门的第一输入端连接，数字缓冲器的输出端与第二与非门的第一输入端连接，第一与非门的输出端与第六反相器的输入端和第二与非门的第二输入端连接，第二与非门的输出端与第七反相器的输入端和第一与非门的第二输入端连接，第六反相器的输出端输出第一内部时钟信号，第七反相器的输出端输出第二内部时钟信号。Further, the clock circuit includes a first NAND gate, a second NAND gate, a fifth inverter, a sixth inverter, a seventh inverter, and a digital buffer, the fifth inverter and the digital The input end of the buffer receives an external clock signal, the output of the fifth inverter is connected to the first input of the first NAND gate, and the output of the digital buffer and the first input of the second NAND gate End connection, the output of the first NAND gate is connected to the input of the sixth inverter and the second input of the second NAND gate, the output of the second NAND gate and the input of the seventh inverter And connected to the second input end of the first NAND gate, the output end of the sixth inverter outputs a first internal clock signal, and the output end of the seventh inverter outputs a second internal clock signal.

进一步，所述输入缓冲放大器采用差分电路形式，其包括两个单端电路形式，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括第一NMOS晶体管和第二NMOS晶体管，所述第一NMOS晶体管为工作晶体管，其栅极接收外部输入的模拟信号，源极输出缓冲后的模拟信号，漏极连接电源VCC；所述第二NMOS晶体管为偏置晶体管，其漏极连接第一NMOS晶体管的源极，为第一NMOS晶体管提供偏置电流，源极接地，栅极连接第一偏置电压。Further, the input buffer amplifier is in the form of a differential circuit comprising two single-ended circuits, the two single-ended circuits respectively for processing a positive phase portion and an inverting portion of the differential signal, each single-ended circuit including the first An NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor is a working transistor, a gate thereof receives an externally input analog signal, a source outputs a buffered analog signal, and a drain is connected to the power source VCC; the second NMOS transistor is The bias transistor has a drain connected to the source of the first NMOS transistor, a bias current for the first NMOS transistor, a source grounded, and a gate connected to the first bias voltage.

进一步，所述主采样保持电路和从采样保持电路均采用差分电路形式并具有相同的电路结构，其包括两个单端电路形式，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括采样开关和采样电容，所述采样电容的下极板接地，上极板连接采样开关的一端，采样开关的另一端连接输入信号，采样开关的控制端与内部时钟信号连接，且所述采样电容上极板信号作为主从采样保持电路的输出采样信号。Further, the main sample-and-hold circuit and the slave sample-and-hold circuit both adopt a differential circuit form and have the same circuit structure, and include two single-ended circuit forms, and two single-ended circuits are respectively used to process the positive phase portion of the differential signal. And the inverting portion, each single-ended circuit includes a sampling switch and a sampling capacitor, the lower plate of the sampling capacitor is grounded, the upper plate is connected to one end of the sampling switch, and the other end of the sampling switch is connected to the input signal, and the control end of the sampling switch Connected to the internal clock signal, and the upper plate signal of the sampling capacitor acts as an output sampling signal of the master-slave sample-and-hold circuit.

进一步，所述级间缓冲放大器采用差分电路形式，其包括两个单端电路形式和尾电流源，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括第八NMOS晶体管、第九NMOS晶体管、第一电阻器和第二电阻器，所述第八NMOS晶体管为工作晶体管，其栅极与主采样保持电路输出的第一采样信号连接，漏极输出缓冲后的第一采样信号，源极连接第一电阻器的一端，第一电阻器的另一端经尾电流源接地；所述第九NMOS晶体管为负载晶体管，其栅极连接第二偏置电压，漏极连接电源VCC，源极连接第二电阻器的一端，第二电阻器的另一端与第八NMOS晶体管的漏极连接。Further, the interstage buffer amplifier is in the form of a differential circuit comprising two single-ended circuit forms and a tail current source, and the two single-ended circuits are respectively configured to process the positive phase portion and the inverted phase portion of the differential signal, each single The terminal circuit includes an eighth NMOS transistor, a ninth NMOS transistor, a first resistor and a second resistor, wherein the eighth NMOS transistor is a working transistor, and a gate thereof is connected to a first sampling signal output by the main sample-and-hold circuit, and the drain The first sampling signal after the buffer is output, the source is connected to one end of the first resistor, and the other end of the first resistor is grounded via a tail current source; the ninth NMOS transistor is a supporting crystal The body tube has a gate connected to the second bias voltage, a drain connected to the power source VCC, a source connected to one end of the second resistor, and the other end of the second resistor connected to the drain of the eighth NMOS transistor.

附图说明DRAWINGS

图1是现有技术提供的CMOS单级采样保持电路结构示意图。FIG. 1 is a schematic structural diagram of a CMOS single-stage sample and hold circuit provided by the prior art.

图2是现有技术提供的CMOS单级采样保持电路时序示意图。2 is a timing diagram of a CMOS single-stage sample and hold circuit provided by the prior art.

图3是本发明提供的CMOS主从式采样保持电路单端原理框图。3 is a block diagram of a single-ended principle of a CMOS master-slave sample-and-hold circuit provided by the present invention.

图4是本发明提供的CMOS主从式采样保持电路时序示意图。4 is a timing diagram of a CMOS master-slave sample-and-hold circuit provided by the present invention.

图5是图3中输入缓冲放大器的实施线路图。Figure 5 is a circuit diagram showing the implementation of the input buffer amplifier of Figure 3.

图6是图3中主从采样保持电路的实施线路图。Figure 6 is a circuit diagram showing the implementation of the master-slave sample-and-hold circuit of Figure 3.

图7是图6中采样开关的实施线路图。Figure 7 is a circuit diagram showing the implementation of the sampling switch of Figure 6.

图8是图3中级间缓冲放大器的实施线路图。Figure 8 is a circuit diagram showing the implementation of the interstage buffer amplifier of Figure 3.

图9是图3中时钟电路的实施线路图。Figure 9 is a circuit diagram showing the implementation of the clock circuit of Figure 3.

图10是图9所示时钟电路工作时序示意图。FIG. 10 is a timing chart showing the operation of the clock circuit shown in FIG. 9.

图11是本发明提供的CMOS主从式采样保持电路差分原理框图。11 is a block diagram of a differential principle of a CMOS master-slave sample-and-hold circuit provided by the present invention.

图12是图11中输入缓冲放大器的实施线路图。Figure 12 is a circuit diagram showing the implementation of the input buffer amplifier of Figure 11.

图13是图11中主从采样保持电路的实施线路图。Figure 13 is a circuit diagram showing the implementation of the master-slave sample-and-hold circuit of Figure 11;

图14是图11中级间缓冲放大器的实施线路图。Figure 14 is a circuit diagram showing the implementation of the interstage buffer amplifier of Figure 11;

图中，1、输入缓冲放大器；2、主采样保持电路；3、级间缓冲放大器；4、从采样保持电路；5、时钟电路。In the figure, 1, input buffer amplifier; 2, main sample and hold circuit; 3, interstage buffer amplifier; 4, slave sample and hold circuit; 5, clock circuit.

具体实施方式detailed description

为了使本发明实现的技术手段、创作特征、达成目的与功效易于明白了解，下面结合具体图示，进一步阐述本发明。 In order to make the technical means, creative features, achievement goals and effects achieved by the present invention easy to understand, the present invention will be further described below in conjunction with specific illustrations.

请参考图3所示，本发明提供一种CMOS主从式采样保持电路，包括：Referring to FIG. 3, the present invention provides a CMOS master-slave sample and hold circuit, including:

输入缓冲放大器1，适于接收和缓冲外部输入的模拟信号Ain，并驱动主采样保持电路2；The input buffer amplifier 1 is adapted to receive and buffer an externally input analog signal Ain and drive the main sample and hold circuit 2;

主采样保持电路2，适于采样保持输入缓冲放大器1的输出信号BAin，并输出第一采样信号SS1；The main sample and hold circuit 2 is adapted to sample and hold the output signal BAin of the input buffer amplifier 1, and output the first sampling signal SS1;

级间缓冲放大器3，适于接收和缓冲第一采样信号SS1，并驱动从采样保持电路4；The interstage buffer amplifier 3 is adapted to receive and buffer the first sampling signal SS1 and drive the slave sample and hold circuit 4;

从采样保持电路4，适于采样保持级间缓冲放大器3的输出信号BSS1，并输出第二采样信号SS2，且第二采样信号SS2为所述CMOS主从式采样保持电路的最终输出信号；The sampling and holding circuit 4 is adapted to sample and hold the output signal BSS1 of the interstage buffer amplifier 3, and output the second sampling signal SS2, and the second sampling signal SS2 is the final output signal of the CMOS master-slave sampling and holding circuit;

时钟电路5，适于接收外部时钟信号CK，产生第一内部时钟信号CKI1和第二内部时钟信号CKI2，所述第一内部时钟信号CKI1和第二内部时钟信号CKI2为一对非交叠的时钟信号，且第一内部时钟信号CKI1用于给主采样保持电路2提供时钟信号，第二内部时钟信号CKI2用于给从采样保持电路4提供时钟信号。The clock circuit 5 is adapted to receive the external clock signal CK to generate a first internal clock signal CKI1 and a second internal clock signal CKI2, the first internal clock signal CKI1 and the second internal clock signal CKI2 being a pair of non-overlapping clocks The signal, and the first internal clock signal CKI1 is used to provide a clock signal to the main sample and hold circuit 2, and the second internal clock signal CKI2 is used to supply a clock signal to the sample and hold circuit 4.

本发明提供的CMOS主从式采样保持电路中，时钟电路产生一对非交叠的第一内部时钟信号和第二内部时钟信号，第一内部时钟信号用于给主采样保持电路提供时钟信号，第二内部时钟信号用于给从采样保持电路提供时钟信号，因而主采样保持电路和从保持采样电路共两级保持电路能够在整个时钟周期内保持信号不变；同时，还包括一个输入缓冲放大器用于接收和缓冲外部输入的模拟信号，一个级间缓冲放大器被***到两级采样保持电路之间，用于隔离主采样保持电路和从采样保持电路的采样电容，防止电荷分享效应发生。本发明应用于模数转换器前端，能大大提高模数转换器性能。In the CMOS master-slave sample-and-hold circuit provided by the present invention, the clock circuit generates a pair of non-overlapping first internal clock signals and a second internal clock signal, and the first internal clock signal is used to provide a clock signal to the main sample and hold circuit. The second internal clock signal is used to provide a clock signal from the sample-and-hold circuit, so that the main sample-and-hold circuit and the slave-sampling circuit maintain a two-stage hold circuit capable of maintaining the signal for the entire clock cycle; and an input buffer amplifier is also included. An analog signal for receiving and buffering external inputs, an interstage buffer amplifier is inserted between the two stages of sample and hold circuits to isolate the sampling capacitors of the main sample and hold circuit and the slave sample and hold circuit to prevent charge sharing effects from occurring. The invention is applied to the front end of an analog-to-digital converter, which can greatly improve the performance of the analog-to-digital converter.

在本发明中，所述主采样保持电路2和从采样保持电路4在时钟信号驱动下周期性工作，每个工作周期分跟踪相和采样相两部分。在跟踪相，主采样保持电路2和从采样保持电路4的输出跟随其输入信号；在保持相，主采样保持电路2和从采样保持电路4的输出信号保持不变。当第一内部时钟信号CKI1为高电平时，主采样保持电路2处于跟踪相，当第一内部时钟信号CKI1为低电平时，主采样保持电路2处于保持相；当第二内部时钟信号CKI2为高电平时，从采样保持电路4处于跟踪相，当第二内部时钟信号CKI2为低电平时，从采样保持电路4处于保持相。由于第一内部时钟信号CKI1和第二内部时钟信号CKI2为一对非交叠的时钟信号，因而主跟踪保持电路2和从跟踪保持电路4不会同时处于跟踪相。In the present invention, the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 are clocked The signal is driven periodically, and each working cycle is divided into two parts: the phase and the sampling phase. In the tracking phase, the output of the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 follows its input signal; in the sustain phase, the output signals of the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 remain unchanged. When the first internal clock signal CKI1 is at a high level, the main sample and hold circuit 2 is in a tracking phase, when the first internal clock signal CKI1 is at a low level, the main sample and hold circuit 2 is in a hold phase; when the second internal clock signal CKI2 is When the level is high, the slave sample-and-hold circuit 4 is in the tracking phase, and when the second internal clock signal CKI2 is at the low level, the slave sample-and-hold circuit 4 is in the hold phase. Since the first internal clock signal CKI1 and the second internal clock signal CKI2 are a pair of non-overlapping clock signals, the main track hold circuit 2 and the slave track hold circuit 4 are not simultaneously in the tracking phase.

具体请参考图4，在开始时刻，第一内部时钟信号CKI1和第二内部时钟信号CKI2都为低电平，主采样保持电路2和从采样保持电路4都处于保持相。在某一时间t，第一内部时钟信号CKI1上升沿到来，其从低电平跳变到高电平，主采样保持电路2进入跟踪相，其输出的第一采样信号SS1跟随外部输入的模拟信号Ain；经过一个脉冲时间τp后，第一内部时钟信号CKI1下降沿到来，其从高电平跳变为低电平，主采样保持电路2采样并保持该时刻的外部输入的模拟信号Ain，之后主采样保持电路2进入保持相，其输出的第一采样信号SS1信号保持不变；再经过一个时钟非交叠时间，第二内部时钟信号CKI2上升沿到来，其从低电平跳变到高电平，从采样保持电路4进入跟踪相，其输出的第二采样信号SS2跟随第一采样信号SS1；经过一个脉冲时间τp后，第二内部时钟信号CKI2下降沿到来，其从高电平跳变为低电平，从采样保持电路4采样并保持该时刻的第一采样信号SS1后进入保持相，其输出的第二采样信号SS2保持不变。此后，在第一内部时钟信号CKI1和第二内部时钟信号CKI2的驱动下，主采样保持电路2和从采样保持电路4交叠地对信号进行采样和保持。并且从图4可以看出，从采样保持电路4输出的第二采样信号SS2在整个时钟周期内保持不变。Specifically, referring to FIG. 4, at the beginning, the first internal clock signal CKI1 and the second internal clock signal CKI2 are both at a low level, and the main sample hold circuit 2 and the slave sample and hold circuit 4 are both in a hold phase. At a certain time t, the rising edge of the first internal clock signal CKI1 comes, which transitions from a low level to a high level, the main sample and hold circuit 2 enters the tracking phase, and the output of the first sampling signal SS1 follows the analog of the external input. The signal Ain; after a pulse time τp, the falling edge of the first internal clock signal CKI1 comes, and it jumps from a high level to a low level, and the main sample and hold circuit 2 samples and maintains the external input analog signal Ain at that moment, After that, the main sample-and-hold circuit 2 enters the hold phase, and the output of the first sample signal SS1 signal remains unchanged; after a clock non-overlap time, the rising edge of the second internal clock signal CKI2 arrives, and it jumps from a low level to The high level enters the tracking phase from the sample and hold circuit 4, and the second sampling signal SS2 of the output follows the first sampling signal SS1; after a pulse time τp, the falling edge of the second internal clock signal CKI2 comes, and the high level is from the high level. Jumping to a low level, the sampled and held circuit 4 samples and holds the first sampled signal SS1 at that moment and enters the hold phase, and the output of the second sampled signal SS2 remains unchanged. Thereafter, under the driving of the first internal clock signal CKI1 and the second internal clock signal CKI2, the main sample-and-hold circuit 2 and the sample-and-hold circuit 4 are superimposed to sample the signal and maintain. And as can be seen from FIG. 4, the second sampling signal SS2 output from the sample and hold circuit 4 remains unchanged throughout the entire clock cycle.

作为一种具体实施例，图3中的所有信号和模块都采用单端信号或者单端电路形式。As a specific embodiment, all of the signals and modules in Figure 3 are in the form of single-ended signals or single-ended circuits.

请参考图5，其示出了图3中输入缓冲放大器1采用单端电路形式实现的线路图，所述输入缓冲放大器1包括第一NMOS晶体管N1和第二NMOS晶体管N2，所述第一NMOS晶体管N1为工作晶体管，其栅极接收外部输入的模拟信号Ain，源极输出缓冲后的模拟信号BAin，漏极连接电源VCC；所述第二NMOS晶体管N2为偏置晶体管，其漏极连接第一NMOS晶体管N1的源极，为第一NMOS晶体管N1提供偏置电流，源极接地，栅极连接第一偏置电压BIAS1。该第一偏置电压BIAS1为一电压信号，可由芯片内的偏置信号产生电路产生，且改变该第一偏置电压BIAS1的大小，可以调节所述第二NMOS晶体管N2提供给第一NMOS晶体管N1的偏置电流大小。Please refer to FIG. 5, which shows a circuit diagram of the input buffer amplifier 1 of FIG. 3 implemented in a single-ended circuit form. The input buffer amplifier 1 includes a first NMOS transistor N1 and a second NMOS transistor N2, the first NMOS. The transistor N1 is a working transistor, the gate thereof receives an externally input analog signal Ain, the source output buffered analog signal BAin, and the drain is connected to the power supply VCC; the second NMOS transistor N2 is a bias transistor, and its drain is connected The source of an NMOS transistor N1 supplies a bias current to the first NMOS transistor N1, the source is grounded, and the gate is coupled to the first bias voltage BIAS1. The first bias voltage BIAS1 is a voltage signal, which can be generated by a bias signal generating circuit in the chip, and the size of the first bias voltage BIAS1 is changed, and the second NMOS transistor N2 can be adjusted to be supplied to the first NMOS transistor. The magnitude of the bias current of N1.

请参考图6所示，所述主采样保持电路2和从采样保持电路4具有相同的电路结构，它们的单端电路实现形式包括采样开关SW和采样电容Cs，所述采样电容Cs的下极板接地，上极板连接采样开关SW的一端，采样开关SW的另一端连接输入信号VIN，采样开关SW的控制端与内部时钟信号CKI连接，且所述采样电容Cs上极板信号作为主从采样保持电路的输出采样信号SS。具体地，在所述主采样保持电路2中，所述采样开关SW的另一端连接的输入信号是BAin，采样开关SW的控制端与内部时钟信号CKI1连接，且所述采样电容Cs上极板信号作为主采样保持电路2的输出采样信号SS1；在所述从采样保持电路4中，所述采样开关SW的另一端连接的输入信号是BSS1，采样开关SW的控制端与内部时钟信号CKI2连接，且所述采样电容Cs上极板信号作为从采样保持电路4的输出采样信号SS2。具体工作过程中，当时钟信号CKI为高电平时，采样开关SW闭合，连接输入信号VIN与采样电容Cs的上极板SS，此时采样电容Cs上极板SS跟踪输入信号VIN；当时钟信号CKI为低电平时，采样开关SW断开，此时采样电容Cs的上极板SS信号保持不变。Referring to FIG. 6, the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 have the same circuit structure. Their single-ended circuit implementation forms a sampling switch SW and a sampling capacitor Cs, and the lower pole of the sampling capacitor Cs. The board is grounded, the upper board is connected to one end of the sampling switch SW, the other end of the sampling switch SW is connected to the input signal VIN, the control end of the sampling switch SW is connected to the internal clock signal CKI, and the plate signal of the sampling capacitor Cs is used as the master. The output sample signal SS of the sample and hold circuit. Specifically, in the main sample and hold circuit 2, the input signal connected to the other end of the sampling switch SW is BAin, the control end of the sampling switch SW is connected to the internal clock signal CKI1, and the sampling capacitor Cs is on the upper plate. The signal is used as the output sampling signal SS1 of the main sample and hold circuit 2; in the slave sample and hold circuit 4, the input signal connected to the other end of the sampling switch SW is BSS1, and the control end of the sampling switch SW is connected to the internal clock signal CKI2. And the plate signal on the sampling capacitor Cs is used as the output sampling signal SS2 from the sample and hold circuit 4. In the specific working process, when the clock signal CKI is high level, the sampling switch SW is closed, and the input signal VIN is connected with the upper plate SS of the sampling capacitor Cs. At this time, the sampling plate Cs upper plate SS tracks the input signal VIN; when the clock signal When CKI is low, the sampling switch SW is turned off, and the SS signal of the upper plate of the sampling capacitor Cs remains unchanged.

作为具体实施例，请参考图7所示，所述采样开关SW为自举开关，包括第一反相器T1、第二反相器T2、第三反相器T3、第四反相器T4、第三NMOS晶体管N3、第四NMOS晶体管N4、第五NMOS晶体管N5、第六NMOS晶体管N6、第七NMOS晶体管N7、第一PMOS晶体管P1、第二PMOS晶体管P2、第三PMOS晶体管P3、电容器Ca和主开关晶体管N0；其中，所述主开关晶体管N0为自举开关的主要开关器件，其源极连接输入信号VIN，漏极连接所述采样电容Cs的上极板SS，栅极同时连接第六NMOS晶体管N6、第七NMOS晶体管N7和第三PMOS晶体管P3的栅极，第一反相器T1的输入端连接内部时钟信号CKI，输出端与第二反相器T2和第三反相器T3的输入端连接，第二反相器T2的输出端连接第三NMOS晶体管N3的源极,第三反相器T3的输出端连接第四反相器T4的输入端、第二PMOS晶体管P2和第五NMOS晶体管N5的栅极，第四反相器T4的输出端连接第四NMOS晶体管N4的栅极，第一反相器T1、第二反相器T2、第三反相器T2和第四反相器T4为CMOS静态逻辑门电路，由电源VCC供电，因此其输出高电平为电源电压VCC，输出低电平为地电平gnd，第三NMOS晶体管N3的栅极接电源VCC，漏极连接主开关晶体管N0的栅极和第一PMOS晶体管P1的漏极，第一PMOS晶体管P1的栅极连接第二PMOS晶体管P2、第五NMOS晶体管N5和第七NMOS晶体管N7的漏极，电容器Ca的上极板连接第一PMOS晶体管P1的源极和第三PMOS晶体管P3的漏极，第三PMOS晶体管P3的源极连接电源VCC，电容器Ca的下极板连接第五NMOS晶体管N5和第七NMOS晶体管N7的源极以及第四NMOS晶体管N4和第六NMOS晶体管N6的漏极，第四NMOS晶体管N4的源极接地，第六NMOS晶体管N6的源极与主开关晶体管N0的源极连接。所述自举开关的工作原理如下：As a specific embodiment, referring to FIG. 7, the sampling switch SW is a bootstrap switch, including a first inverter T1, a second inverter T2, a third inverter T3, and a fourth inverter T4. Third NMOS transistor N3, fourth NMOS transistor N4, fifth NMOS transistor N5, sixth NMOS transistor N6, seventh NMOS transistor N7, first PMOS transistor P1, second PMOS transistor P2, third PMOS transistor P3, capacitor Ca and a main switching transistor N0; wherein the main switching transistor N0 is a main switching device of the bootstrap switch, the source is connected to the input signal VIN, the drain is connected to the upper plate SS of the sampling capacitor Cs, and the gate is simultaneously connected The gates of the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the third PMOS transistor P3, the input end of the first inverter T1 is connected to the internal clock signal CKI, the output terminal is opposite to the second inverter T2 and the third inverter The input end of the second inverter T2 is connected to the source of the third NMOS transistor N3, and the output end of the third inverter T3 is connected to the input end of the fourth inverter T4, the second PMOS transistor P2 and the gate of the fifth NMOS transistor N5, the output of the fourth inverter T4 Connecting the gate of the fourth NMOS transistor N4, the first inverter T1, the second inverter T2, the third inverter T2, and the fourth inverter T4 are CMOS static logic gate circuits, and are powered by the power source VCC, The output high level is the power supply voltage VCC, the output low level is the ground level gnd, the gate of the third NMOS transistor N3 is connected to the power supply VCC, and the drain is connected to the gate of the main switching transistor N0 and the drain of the first PMOS transistor P1. The gate of the first PMOS transistor P1 is connected to the drains of the second PMOS transistor P2, the fifth NMOS transistor N5 and the seventh NMOS transistor N7, and the upper plate of the capacitor Ca is connected to the source of the first PMOS transistor P1 and the third The drain of the PMOS transistor P3, the source of the third PMOS transistor P3 is connected to the power source VCC, and the lower plate of the capacitor Ca is connected. The sources of the fifth NMOS transistor N5 and the seventh NMOS transistor N7 and the drains of the fourth NMOS transistor N4 and the sixth NMOS transistor N6, the source of the fourth NMOS transistor N4 is grounded, and the source and the main of the sixth NMOS transistor N6 The source of the switching transistor N0 is connected. The working principle of the bootstrap switch is as follows:

当时钟信号CKI为低电平时，第二反相器T2输出低电平，第三NMOS晶体管N3开启，主开关晶体管N0的栅极被拉低，主开关晶体管N0截止，断开其源极与栅极间的电学连接。由于图6中采样电容Cs的信号保持功能，位于主开关晶体管N0漏极的信号SS将被采样并保持；同时，第六NMOS晶体管N6的栅极电位被拉低，第六NMOS晶体管N6截止，断开电容器Ca下极板与输入信号VIN的电学连接；同时，第三PMOS晶体管P3的栅极电位被拉低，第三PMOS晶体管P3开启，把电容器Ca的上极板连接到电源VCC。第七NMOS晶体管N7的栅极被拉低，第七NMOS晶体管N7截止，部分断开(因为电容器Ca的下极板与第一PMOS晶体管P1的栅极通过N7和N5连接，N7截止只是部分断开，只有当N5也截止时才完全断开)第一PMOS晶体管P1的栅极与电容器Ca下极板间的电学连接。同时，第三反相器T3输出为低电平，第五NMOS晶体管N5的栅极为低电平，第五NMOS晶体管N5截止，进一步完全断开第一PMOS晶体管P1的栅极与电容器Ca下极板间的电学连接。同时，第二PMOS晶体管P2的栅极为低电平，第二PMOS晶体管P2开启，把第一PMOS晶体管P1的栅极连接到电源VCC，第一PMOS晶体管截止，断开电容器Ca上极板与主开关晶体管N0栅极间的电学连接。同时，第四反相器T4的输出为高电平，第四NMOS晶体管N4栅极为高电平，第四NMOS晶体管N4开启，把电容器Ca的下极板连接到地gnd。由此可见，电容器Ca的上极板通过第三PMOS晶体管P3连接到电源VCC，下极板通过第四NMOS晶体管N4连接到地，电源VCC对电容器Ca充电直至电容器两端的电压差达到电源电压VCC。When the clock signal CKI is low, the second inverter T2 outputs a low level, the third NMOS transistor N3 is turned on, the gate of the main switching transistor N0 is pulled low, the main switching transistor N0 is turned off, and the source thereof is turned off. Electrical connection between the gates. Due to the signal holding function of the sampling capacitor Cs in FIG. 6, the signal SS at the drain of the main switching transistor N0 is sampled and held; meanwhile, the gate potential of the sixth NMOS transistor N6 is pulled low, and the sixth NMOS transistor N6 is turned off. The electrical connection between the lower plate of the capacitor Ca and the input signal VIN is disconnected; at the same time, the gate potential of the third PMOS transistor P3 is pulled low, the third PMOS transistor P3 is turned on, and the upper plate of the capacitor Ca is connected to the power supply VCC. The gate of the seventh NMOS transistor N7 is pulled low, and the seventh NMOS transistor N7 is turned off and partially turned off (because the lower plate of the capacitor Ca is connected to the gate of the first PMOS transistor P1 through N7 and N5, the N7 cutoff is only partially broken. On, the electrical connection between the gate of the first PMOS transistor P1 and the lower plate of the capacitor Ca is only completely disconnected when N5 is also turned off. At the same time, the third inverter T3 outputs a low level, the gate of the fifth NMOS transistor N5 is at a low level, and the fifth NMOS transistor N5 is turned off, further completely turning off the gate of the first PMOS transistor P1 and the lower pole of the capacitor Ca. Electrical connection between boards. At the same time, the gate of the second PMOS transistor P2 is at a low level, the second PMOS transistor P2 is turned on, the gate of the first PMOS transistor P1 is connected to the power source VCC, the first PMOS transistor is turned off, and the upper plate and the main electrode of the capacitor Ca are disconnected. Electrical connection between the gates of the switching transistor N0. At the same time, the output of the fourth inverter T4 is at a high level, the gate of the fourth NMOS transistor N4 is at a high level, and the fourth NMOS transistor N4 is turned on, connecting the lower plate of the capacitor Ca to the ground gnd. It can be seen that the upper plate of the capacitor Ca is connected to the power source VCC through the third PMOS transistor P3, and the lower plate is connected to the ground through the fourth NMOS transistor N4, and the power source VCC pair The capacitor Ca is charged until the voltage difference across the capacitor reaches the supply voltage VCC.

当时钟信号CKI为高电平时，第二反相器T2的输出为高电平，第三NMOS晶体管N3截止，断开其源极与漏极间的电学连接。第三反相器T3输出为高电平，第二PMOS晶体管P2截止，断开第一PMOS晶体管P1栅极与电源VCC的电学连接。同时，第五NMOS晶体管N5开启，把第一PMOS晶体管P1的栅极连接到电容器Ca的下极板。这样，电容器Ca上、下极板间的电压差VCC被加到第一PMOS晶体管P1的源、栅极间，第一PMOS晶体管P1开启，从而把电容器Ca的上极板连接到主开关晶体管N0的栅极。这样，电容器Ca上、下极板间的压差VCC被加到了第七NMOS晶体管N7的栅、源极间，第七NMOS晶体管N7开启，这样第一PMOS晶体管P1的栅极进一步被充分地连接到电容器Ca的下极板。同时，第四反相器T4的输出为低电平，第四NMOS晶体管N4截止，断开了电容器Ca下极板与地gnd的电学连接。同时，电容器Ca上、下极板的压差VCC被加到了第六NMOS晶体管的栅、源极之间，第六NMOS晶体管开启，从而把电容器Ca的下极板连接到主开关晶体管N0的源极。这时，电容器Ca上、下极板间的压差VCC被加到主开关晶体管N0的栅、源极间，主开关晶体管N0开启，从而连接输入信号VIN与输出信号SS。由于电容器Ca的信号保持功能，在输入信号VIN变化时，主开关晶体管N0的栅极与源极间始终保持VCC的压差。When the clock signal CKI is at a high level, the output of the second inverter T2 is at a high level, and the third NMOS transistor N3 is turned off, turning off the electrical connection between the source and the drain. The third inverter T3 outputs a high level, the second PMOS transistor P2 is turned off, and the electrical connection between the gate of the first PMOS transistor P1 and the power source VCC is turned off. At the same time, the fifth NMOS transistor N5 is turned on to connect the gate of the first PMOS transistor P1 to the lower plate of the capacitor Ca. Thus, the voltage difference VCC between the upper and lower plates of the capacitor Ca is applied between the source and the gate of the first PMOS transistor P1, and the first PMOS transistor P1 is turned on, thereby connecting the upper plate of the capacitor Ca to the main switching transistor N0. The gate. Thus, the voltage difference VCC between the upper and lower plates of the capacitor Ca is applied between the gate and the source of the seventh NMOS transistor N7, and the seventh NMOS transistor N7 is turned on, so that the gate of the first PMOS transistor P1 is further sufficiently connected. Go to the lower plate of capacitor Ca. At the same time, the output of the fourth inverter T4 is at a low level, and the fourth NMOS transistor N4 is turned off, and the electrical connection between the lower plate of the capacitor Ca and the ground gnd is broken. At the same time, the voltage difference VCC of the upper and lower plates of the capacitor Ca is applied between the gate and the source of the sixth NMOS transistor, and the sixth NMOS transistor is turned on, thereby connecting the lower plate of the capacitor Ca to the source of the main switching transistor N0. pole. At this time, the voltage difference VCC between the upper and lower plates of the capacitor Ca is applied between the gate and the source of the main switching transistor N0, and the main switching transistor N0 is turned on, thereby connecting the input signal VIN and the output signal SS. Due to the signal holding function of the capacitor Ca, when the input signal VIN changes, the voltage difference of VCC is always maintained between the gate and the source of the main switching transistor N0.

根据半导体器件的物理知识，主开关晶体管N0的导通电阻为：According to the physics knowledge of the semiconductor device, the on-resistance of the main switching transistor N0 is:

上式中μ_n为电子迁移率，C_ox为MOS晶体管单位面积栅电容，W和L分别为主开关晶体管N0的栅宽和栅长，V_g和V_s分别为主开关晶体管N0栅极和源极电位，V_th为MOS晶体管的阈值电压；因为 In the above formula, μ _n is the electron mobility, C _ox is the gate capacitance of the MOS transistor per unit area, W and L are the gate width and the gate length of the main switching transistor N0, respectively, and V _g and V _s are the gates of the main switching transistor N0, respectively. Source potential, V _th is the threshold voltage of the MOS transistor;

V_g-V_s＝VCC (2)V _g -V _s =VCC (2)

把(2)式代入(1)式得到Substituting (2) into (1)

由(3)式可知，主开关管晶体管N0的导通电阻不随输入信号VIN变化，这提高了主从式采样保持电路的线型性；具体由图7可知，主开关晶体管N0的源极电位V_s其实是输入信号VIN，而(3)式中消去了V_s，也就是说导通电阻R_on与输入信号VIN无关。所以，本发明采样开关SW采用专门设计的自举开关，极大地提高了采样开关SW的线型性。It can be seen from equation (3) that the on-resistance of the main switching transistor N0 does not change with the input signal VIN, which improves the linearity of the master-slave sampling and holding circuit; as specifically shown in FIG. 7, the source potential of the main switching transistor N0 V _s is actually the input signal VIN, and V _s is eliminated in (3), that is, the on-resistance R _{on is} independent of the input signal VIN. Therefore, the sampling switch SW of the present invention adopts a specially designed bootstrap switch, which greatly improves the linearity of the sampling switch SW.

作为具体实施例，请参考图8所示，所述级间缓冲放大器3采用单端电路形式，其包括第八NMOS晶体管N8、第九NMOS晶体管N9、第一电阻器R1和第二电阻器R2，所述第八NMOS晶体管N8为工作晶体管，其栅极与主采样保持电路2输出的第一采样信号SS1连接，漏极输出缓冲后的第一采样信号BSS1，源极连接第一电阻器R1的一端，第一电阻器R1的另一端接地；所述第九NMOS晶体管N9为负载晶体管，其栅极连接第二偏置电压BIAS2，漏极连接电源VCC，源极连接第二电阻器R2的一端，第二电阻器R2的另一端与第八NMOS晶体管N8的漏极连接。其中，所述第一电阻器R1作为退化电阻用于提高所述级间缓冲放大器3的线型性，所述第二偏置电压BIAS2为电压信号，可由芯片内偏置产生单元产生。整个级间缓冲放大器3的增益可表示为：As a specific embodiment, referring to FIG. 8, the interstage buffer amplifier 3 adopts a single-ended circuit form, which includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, a first resistor R1, and a second resistor R2. The eighth NMOS transistor N8 is a working transistor, the gate thereof is connected to the first sampling signal SS1 outputted by the main sample-and-hold circuit 2, the drain outputs the buffered first sampling signal BSS1, and the source is connected to the first resistor R1. One end of the first resistor R1 is grounded; the ninth NMOS transistor N9 is a load transistor, the gate is connected to the second bias voltage BIAS2, the drain is connected to the power source VCC, and the source is connected to the second resistor R2. At one end, the other end of the second resistor R2 is connected to the drain of the eighth NMOS transistor N8. The first resistor R1 is used as a degeneration resistor for increasing the linearity of the interstage buffer amplifier 3. The second bias voltage BIAS2 is a voltage signal, which can be generated by an on-chip bias generating unit. The gain of the interstage buffer amplifier 3 can be expressed as:

上式中，g_m8和g_m9分别是第八NMOS晶体管N8和第九NMOS晶体管N9的跨导；作为一种具体实施方式，所述第八NMOS晶体管N8与第九NMOS晶体管N9具有相同的尺寸，即所述第八NMOS晶体管N8和第九NMOS晶体管N9的跨导相等，所以In the above formula, g _m8 and g _m9 are transconductances of the eighth NMOS transistor N8 and the ninth NMOS transistor N9, respectively; as a specific embodiment, the eighth NMOS transistor N8 and the ninth NMOS transistor N9 have the same size. That is, the transconductance of the eighth NMOS transistor N8 and the ninth NMOS transistor N9 is equal, so

g_m8＝g_m9 (5)g _m8 =g _m9 (5)

且所述第一电阻器R1和第二电阻器R2的阻值相等，把(5)式代入(4)式，得到G_ain＝1，即所述级间缓冲放大器3的级间增益为1，因而它不会对第一采样信号SS1放大，缓冲后的第一采样信号BSS1只相对于第一采样信号SS1作信号平移，因此所述级间缓冲放大器3具有极好的线型性。And the first resistor R1 and the second resistor R2 with resistance, the (5) into (4), to give G _ain = 1, i.e., inter-stage buffer amplifier 3 interstage gain of 1 Therefore, it does not amplify the first sampling signal SS1, and the buffered first sampling signal BSS1 only performs signal translation with respect to the first sampling signal SS1, so the interstage buffer amplifier 3 has excellent linearity.

作为具体实施例，请参考图9所示，所述时钟电路5包括第一与非门NAND1、第二与非门NAND2、第五反相器T5、第六反相器T6、第七反相器T7和数字缓冲器B1，所述第五反相器T5和数字缓冲器B1的输入端接收外部时钟信号CK，第五反相器T5的输出端与第一与非门NAND1的第一输入端连接，数字缓冲器B1的输出端与第二与非门NAND2的第一输入端连接，第一与非门NAND1的输出端与第六反相器T6的输入端和第二与非门NAND2的第二输入端连接，第二与非门NAND2的输出端与第七反相器T7的输入端和第一与非门NAND1的第二输入端连接，第六反相器T6的输出端输出第一内部时钟信号CKI1，第七反相器T7的输出端输出第二内部时钟信号CKI2。在下面的原理说明中，为了说明的方便，假设所有数字门电路延迟都相等设为τ_gate。具体地，所述时钟电路5的工作原理如下：As a specific embodiment, as shown in FIG. 9, the clock circuit 5 includes a first NAND gate NAND1, a second NAND gate NAND2, a fifth inverter T5, a sixth inverter T6, and a seventh inversion. The input terminal of the fifth inverter T5 and the digital buffer B1 receives the external clock signal CK, the output of the fifth inverter T5 and the first input of the first NAND gate NAND1 End connection, the output of the digital buffer B1 is connected to the first input of the second NAND gate NAND2, the output of the first NAND gate NAND1 and the input of the sixth inverter T6 and the second NAND gate NAND2 The second input terminal is connected, the output terminal of the second NAND gate NAND2 is connected to the input terminal of the seventh inverter T7 and the second input terminal of the first NAND gate NAND1, and the output terminal of the sixth inverter T6 is output. The first internal clock signal CKI1, the output of the seventh inverter T7 outputs a second internal clock signal CKI2. In the following description of the principle, for convenience of explanation, it is assumed that all digital gate delays are equal to τ _gate . Specifically, the working principle of the clock circuit 5 is as follows:

请参考图10，假设在初始时刻，外部时钟信号CK为低电平(即地)，此时数字缓冲器B1的输出为低电平，第二与非门NAND2的输出为高电平；同时，第五反相器T5的输出为高电平，第一与非门NAND1的输出为低电平。当外部时钟信号CK的上升沿到来时，外部时钟信号CK从低电平变为高电平(即电源电压VCC)，经过一个门延迟时间τ_gate后第五反相器T5的输出从高电平变为低电平，再经过一个门延迟时间τ_gate后，第一与非门NAND1的输出从低电平变为高电平，再经过一个门延迟时间，第二与非门NAND2的输出从高电平变为低电平。再经过半个时钟周期，外部时钟信号CK的下降沿到来，外部时钟信号CK从高电平变为低电平，经过一个门延迟后，数字缓冲器B1的输出从高电平变为低电平，再经过一个门延迟后，第二与非门NAND2的输出从低电平变为高电平，再经过一个门延迟，第一与非门NAND1的输出从高电平变为低电变。由此可见，每当外部时钟信号CK的上升沿到来时，引起第一与非门NAND1的输出从低电平变为高电平，再经过一个门延迟后，引起第二与非门NAND2的输出从高电平变为低电平；每当外部时钟信号CK的下降沿到来时，引起第二与非门NAND2的输出从低电平变为高电平，再经过一个门延迟后，引起第一与非门NAND1的输出从高电平变为低电平。也就是说，第一与非门NAND1的输出与第二与非门NAND2的输出有一个门延迟时间的脉冲交叠时间；当经过第六反相器T6和第七反相器T7反相后，得到的第一内部时钟信号CKI1与第二内部时钟信号CKI2为非交叠时钟，非交叠时间为一个门延迟时间。Referring to FIG. 10, it is assumed that at the initial moment, the external clock signal CK is at a low level (ie, ground), at which time the output of the digital buffer B1 is at a low level, and the output of the second NAND gate NAND2 is at a high level; The output of the fifth inverter T5 is at a high level, and the output of the first NAND gate NAND1 is at a low level. When the rising edge of the external clock signal CK comes, the external clock signal CK changes from a low level to a high level (ie, the power supply voltage VCC), and the output of the fifth inverter T5 goes from a high voltage after a gate delay time τ _gate After going to a low level, after a gate delay time τ _gate , the output of the first NAND gate NAND1 changes from a low level to a high level, and then a gate delay time, the output of the second NAND gate NAND2 Go from high to low. After half a clock cycle, the falling edge of the external clock signal CK comes, and the external clock signal CK changes from a high level to a low level. After a gate delay, the output of the digital buffer B1 changes from a high level to a low level. After a gate delay, the output of the second NAND gate NAND2 changes from a low level to a high level, and after a gate delay, the output of the first NAND gate NAND1 changes from a high level to a low level. . It can be seen that whenever the rising edge of the external clock signal CK comes, the output of the first NAND gate NAND1 is changed from a low level to a high level, and after a gate delay, the second NAND gate NAND2 is caused. The output changes from a high level to a low level; whenever the falling edge of the external clock signal CK comes, the output of the second NAND gate NAND2 is changed from a low level to a high level, and after a gate delay, The output of the first NAND gate NAND1 changes from a high level to a low level. That is, the output of the first NAND gate NAND1 and the output of the second NAND gate NAND2 have a pulse overlap time of a gate delay time; when the sixth inverter T6 and the seventh inverter T7 are inverted The obtained first internal clock signal CKI1 and the second internal clock signal CKI2 are non-overlapping clocks, and the non-overlap time is one gate delay time.

作为另一种具体实施例，本发明还可以采用差分电路形式实现，即图3中的部分信号和模块将采用差分信号和差分模块形式。为了便于说明，本发明将差分形式实现的原理框图重画，具体请参见图11所示。在本发明的差分实现形式中，所述输入缓冲放大器1、主采样保持电路2、级间缓冲放大器3和主采样保持电路4都采用差分电路。As another specific embodiment, the present invention can also be implemented in the form of a differential circuit, that is, part of the signals and modules in FIG. 3 will be in the form of differential signals and differential modules. For convenience of description, the present invention redraws the principle block diagram of the differential form implementation. For details, please refer to FIG. In the differential implementation form of the present invention, the input buffer amplifier 1, the main sample and hold circuit 2, the interstage buffer amplifier 3, and the main sample and hold circuit 4 all employ a differential circuit.

作为具体实施例，请参考图12所示，所述输入缓冲放大器2采用差分电路形式，其包括两个图5所示的单端电路形式输入缓冲放大器，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括第一NMOS晶体管N1和第二NMOS晶体管N2，所述第一NMOS晶体管N1为工作晶体管，其栅极接收外部输入的模拟信号Ain+和Ain-，源极输出缓冲后的模拟信号Bain-和Bain+，漏极连接电源VCC；所述第二NMOS晶体管N2为偏置晶体管，其漏极连接第一NMOS晶体管N1的源极，为第一NMOS晶体管N1提供偏置电流，源极接地gnd，栅极连接第一偏置电压BIAS1。该第一偏置电压BIAS1为一电压信号，可由芯片内的偏置信号产生电路产生，且改变该第一偏置电压BIAS1的大小，可以调节所述第二NMOS晶体管N2提供给第一NMOS晶体管N1的偏置电流大小。As a specific embodiment, referring to FIG. 12, the input buffer amplifier 2 adopts a differential circuit form, which includes two single-ended circuit form input buffer amplifiers as shown in FIG. 5, and two single-ended circuits respectively for processing differentials. a positive phase portion and an inverting portion of the signal, each single-ended circuit comprising a first NMOS transistor N1 and a second NMOS transistor N2, the first NMOS transistor N1 being a working transistor, the gate of which receives an externally input analog signal Ain+ And Ain-, the source signal buffered analog signals Bain- and Bain+, leak The second NMOS transistor N2 is a bias transistor, the drain of which is connected to the source of the first NMOS transistor N1, the bias current is supplied to the first NMOS transistor N1, the source is grounded to gnd, and the gate is connected. A bias voltage BIAS1. The first bias voltage BIAS1 is a voltage signal, which can be generated by a bias signal generating circuit in the chip, and the size of the first bias voltage BIAS1 is changed, and the second NMOS transistor N2 can be adjusted to be supplied to the first NMOS transistor. The magnitude of the bias current of N1.

作为具体实施例，请参考图13所示，所述主采样保持电路2和从采样保持电路4均采用差分电路形式并具有相同的电路结构，其包括两个图6所示的单端电路形式采样保持电路，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括采样开关SW和采样电容Cs，所述采样电容Cs的下极板接地，上极板连接采样开关SW的一端，采样开关的另一端连接输入信号VIN+和VIN-，采样开关SW的控制端与内部时钟信号CKI连接，且所述采样电容Cs上极板信号SS+和SS-作为主从采样保持电路的输出采样信号。具体地，在所述主采样保持电路2中，所述采样开关SW的另一端连接的输入信号是Bain+和Bain-，采样开关SW的控制端与内部时钟信号CKI1连接，且所述采样电容Cs上极板信号作为主采样保持电路2的输出采样信号SS1+和SS1-；在所述从采样保持电路4中，所述采样开关SW的另一端连接的输入信号是BSS1+和BSS1-，采样开关SW的控制端与内部时钟信号CKI2连接，且所述采样电容Cs上极板信号作为从采样保持电路4的输出采样信号SS2+和SS2-。具体工作过程中，当时钟信号CKI为高电平时，采样开关SW闭合，连接输入信号VIN+和VIN-与采样电容Cs的上极板SS+和SS-，此时采样电容Cs上极板SS跟踪输入信号VIN+和VIN-；当时钟信号CKI为低电平时，采样开关SW断开，此时采样电容Cs的上极板SS信号保持不变。 As a specific embodiment, please refer to FIG. 13, the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 are both in the form of a differential circuit and have the same circuit structure, including two single-ended circuit forms as shown in FIG. a sample-and-hold circuit, two single-ended circuits for respectively processing a positive phase portion and an inverting portion of the differential signal, each single-ended circuit comprising a sampling switch SW and a sampling capacitor Cs, the lower plate of the sampling capacitor Cs being grounded, The upper plate is connected to one end of the sampling switch SW, the other end of the sampling switch is connected to the input signals VIN+ and VIN-, the control end of the sampling switch SW is connected to the internal clock signal CKI, and the sampling signals Cs are on the plate signals SS+ and SS- As the output sampling signal of the master-slave sample-and-hold circuit. Specifically, in the main sample and hold circuit 2, the input signals connected to the other end of the sampling switch SW are Bain+ and Bain-, the control end of the sampling switch SW is connected to the internal clock signal CKI1, and the sampling capacitor Cs The upper plate signal is used as the output sampling signals SS1+ and SS1 of the main sample and hold circuit 2; in the slave sample and hold circuit 4, the input signals connected to the other end of the sampling switch SW are BSS1+ and BSS1-, and the sampling switch SW The control terminal is connected to the internal clock signal CKI2, and the plate signal on the sampling capacitor Cs is used as the output sampling signals SS2+ and SS2- from the sample and hold circuit 4. During the specific working process, when the clock signal CKI is high, the sampling switch SW is closed, and the input signals VIN+ and VIN- are connected with the upper plates SS+ and SS- of the sampling capacitor Cs. At this time, the sampling capacitor Cs is the upper plate SS tracking input. Signals VIN+ and VIN-; When the clock signal CKI is low, the sampling switch SW is turned off, and the SS signal of the upper plate of the sampling capacitor Cs remains unchanged.

作为具体实施例，请参考图14所示，所述级间缓冲放大器3采用差分电路形式，其包括两个图8所示的单端电路形式级间缓冲放大器和一尾电流源U1，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括第八NMOS晶体管N8、第九NMOS晶体管N9、第一电阻器R1和第二电阻器R2，所述第八NMOS晶体管N8为工作晶体管，其栅极与主采样保持电路2输出的第一采样信号SS1+和SS1-连接，漏极输出缓冲后的第一采样信号BSS1-和BSS1+，源极连接第一电阻器R1的一端，第一电阻器R1的另一端经尾电流源U1接地gnd；所述第九NMOS晶体管N9为负载晶体管，其栅极连接第二偏置电压BIAS2，漏极连接电源VCC，源极连接第二电阻器R2的一端，第二电阻器R2的另一端与第八NMOS晶体管N8的漏极连接。其中，所述第一电阻器R1作为退化电阻用于提高所述级间缓冲放大器3的线型性，所述第二偏置电压BIAS2为电压信号，可由芯片内偏置产生单元产生。图14所示差分形式的级间缓冲放大器单端等效电路与图8相同，所以其差分增益也为1。另外，图14所示差分形式的级间缓冲放大器的输出共模电平为：As a specific embodiment, referring to FIG. 14, the interstage buffer amplifier 3 is in the form of a differential circuit including two single-ended circuit-level inter-stage buffer amplifiers and a tail current source U1 as shown in FIG. The single-ended circuit is respectively configured to process the positive phase portion and the inverting portion of the differential signal, and each single-ended circuit includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, a first resistor R1, and a second resistor R2. The eighth NMOS transistor N8 is a working transistor, the gate thereof is connected to the first sampling signals SS1+ and SS1- output from the main sample-and-hold circuit 2, and the drain-sampling first sampling signals BSS1- and BSS1+ are connected to the source. One end of a resistor R1, the other end of the first resistor R1 is grounded by a tail current source U1; the ninth NMOS transistor N9 is a load transistor, the gate is connected to the second bias voltage BIAS2, and the drain is connected to the power source VCC The source is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the drain of the eighth NMOS transistor N8. The first resistor R1 is used as a degeneration resistor for increasing the linearity of the interstage buffer amplifier 3. The second bias voltage BIAS2 is a voltage signal, which can be generated by an on-chip bias generating unit. The single-ended equivalent circuit of the differential buffer type interstage buffer amplifier shown in Fig. 14 is the same as that of Fig. 8, so the differential gain is also 1. In addition, the output common mode level of the differential buffer type interstage buffer amplifier shown in Figure 14 is:

上式中，I为尾电流源U1所提供的电流，R为第二电阻器R2的阻值。由此可见，差分形式的级间缓冲放大器的输出共模由其偏置水平和器件参数值决定，与输入信号的共模水平无关。In the above formula, I is the current supplied by the tail current source U1, and R is the resistance of the second resistor R2. It can be seen that the output common mode of the differential interstage buffer amplifier is determined by its bias level and device parameter values, independent of the common mode level of the input signal.

本发明提供的一种CMOS主从式采样保持电路，包括主采样保持电路和从保持采样电路共两级采样保持电路，其能够在整个时钟周期内保持信号不变；所述输入缓冲放大器用于接收和缓冲模拟信号；所述级间缓冲放大器被***到主从两级采样保持电路之间，用于隔离主采样保持电路和从采样保持电路的采样电容，防止电荷分享效应发生；本发明采样开关采用专门设计的自举开关，极大提高了采样开关的线型性。同时，本发明的差分实现形式能最大程度上降低MOS开关电荷注入效应对电路性能的影响；此外，差分实现形式能在主从式采样保持电路内部产生共模信号，该共模信号不受输入信号影响。将本发明提供的CMOS主从式采样保持电路应用于模数转换器前端，能大大提高模数转换器性能。The invention provides a CMOS master-slave sample-and-hold circuit, comprising a main sample-and-hold circuit and a slave-sampling circuit, a two-stage sample-and-hold circuit capable of maintaining a signal constant throughout a clock cycle; the input buffer amplifier is used for Receiving and buffering an analog signal; the interstage buffer amplifier is inserted between the master-slave two-stage sample-and-hold circuit for isolating the sampling capacitor of the main sample-and-hold circuit and the slave sample-and-hold circuit to prevent charge sharing effects from occurring; sampling of the present invention The switch uses a specially designed bootstrap switch, which greatly improves the sampling switch Linearity. At the same time, the differential implementation form of the present invention can minimize the influence of the MOS switch charge injection effect on the circuit performance; in addition, the differential implementation can generate a common mode signal inside the master-slave sample-and-hold circuit, and the common mode signal is not input. Signal impact. Applying the CMOS master-slave sample-and-hold circuit provided by the present invention to the front end of the analog-to-digital converter can greatly improve the performance of the analog-to-digital converter.

以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构，直接或间接运用在其他相关的技术领域，均同理在本发明的专利保护范围之内。 The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure made by the specification and the drawings of the present invention is directly or indirectly applied to other related technical fields. Within the scope of patent protection.

Claims

一种CMOS主从式采样保持电路，其特征在于，包括：A CMOS master-slave sample and hold circuit, comprising:

输入缓冲放大器，适于接收和缓冲外部输入的模拟信号，并驱动主采样保持电路；An input buffer amplifier adapted to receive and buffer an externally input analog signal and drive the main sample and hold circuit;

主采样保持电路，适于采样保持输入缓冲放大器的输出信号，并输出第一采样信号；a main sample and hold circuit adapted to sample and hold an output signal of the input buffer amplifier and output a first sampling signal;

级间缓冲放大器，适于接收和缓冲第一采样信号，并驱动从采样保持电路；An interstage buffer amplifier adapted to receive and buffer the first sampled signal and drive the slave sample and hold circuit;

从采样保持电路，适于采样保持级间缓冲放大器的输出信号，并输出第二采样信号，且第二采样信号为所述CMOS主从式采样保持电路的最终输出信号；The sample-and-hold circuit is adapted to sample and hold an output signal of the interstage buffer amplifier, and output a second sampling signal, and the second sampling signal is a final output signal of the CMOS master-slave sample-and-hold circuit;

时钟电路，适于接收外部时钟信号，产生第一内部时钟信号和第二内部时钟信号，所述第一内部时钟信号和第二内部时钟信号为一对非交叠的时钟信号，且第一内部时钟信号用于给主采样保持电路提供时钟信号，第二内部时钟信号用于给从采样保持电路提供时钟信号。a clock circuit adapted to receive an external clock signal to generate a first internal clock signal and a second internal clock signal, the first internal clock signal and the second internal clock signal being a pair of non-overlapping clock signals, and the first internal The clock signal is used to provide a clock signal to the main sample and hold circuit, and the second internal clock signal is used to provide a clock signal to the sample and hold circuit.
根据权利要求1所述的CMOS主从式采样保持电路，其特征在于，所述输入缓冲放大器采用单端电路形式，包括第一NMOS晶体管和第二NMOS晶体管，所述第一NMOS晶体管为工作晶体管，其栅极接收外部输入的模拟信号，源极输出缓冲后的模拟信号，漏极连接电源VCC；所述第二NMOS晶体管为偏置晶体管，其漏极连接第一NMOS晶体管的源极，为第一NMOS晶体管提供偏置电流，源极接地，栅极连接第一偏置电压。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said input buffer amplifier is in the form of a single-ended circuit, comprising a first NMOS transistor and a second NMOS transistor, said first NMOS transistor being a working transistor The gate receives an externally input analog signal, the source outputs the buffered analog signal, and the drain is connected to the power supply VCC; the second NMOS transistor is a bias transistor whose drain is connected to the source of the first NMOS transistor, The first NMOS transistor provides a bias current, the source is grounded, and the gate is coupled to the first bias voltage.
根据权利要求1所述的CMOS主从式采样保持电路，其特征在于，所述主采样保持电路和从采样保持电路均采用单端电路形式并具有相同的电路结构，包括采样开关和采样电容，所述采样电容的下极板接地，上极板连接采样开关的一端，采样开关的另一端连接输入信号，采样开关的控制端与内部时钟信号连接，且所述采样电容上极板信号作为主从采样保持电路的输出采样信号。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein the main sample-and-hold circuit and the slave sample-and-hold circuit both adopt a single-ended circuit form and have the same circuit structure, including a sampling switch and a sampling capacitor. The lower plate of the sampling capacitor is grounded, the upper plate is connected to one end of the sampling switch, and the other end of the sampling switch is connected to the input. The signal, the control end of the sampling switch is connected to the internal clock signal, and the upper plate signal of the sampling capacitor is used as the output sampling signal of the master-slave sampling and holding circuit.
根据权利要求3所述的CMOS主从式采样保持电路，其特征在于，所述采样开关为自举开关，包括第一反相器、第二反相器、第三反相器、第四反相器、第三NMOS晶体管、第四NMOS晶体管、第五NMOS晶体管、第六NMOS晶体管、第七NMOS晶体管、第一PMOS晶体管、第二PMOS晶体管、第三PMOS晶体管、电容器和主开关晶体管；所述主开关晶体管的源极连接输入信号，漏极连接所述采样电容的上极板，栅极同时连接第六NMOS晶体管、第七NMOS晶体管和第三PMOS晶体管的栅极，第一反相器的输入端连接内部时钟信号，输出端与第二反相器和第三反相器的输入端连接，第二反相器的输出端连接第三NMOS晶体管的源极,第三反相器的输出端连接第四反相器的输入端、第二PMOS晶体管和第五NMOS晶体管的栅极，第四反相器的输出端连接第四NMOS晶体管的栅极，第一反相器、第二反相器、第三反相器和第四反相器为CMOS静态逻辑门电路，由电源VCC供电，第三NMOS晶体管的栅极接电源VCC，漏极连接主开关晶体管的栅极和第一PMOS晶体管的漏极，第一PMOS晶体管的栅极连接第二PMOS晶体管、第五NMOS晶体管和第七NMOS晶体管的漏极，电容器的上极板连接第一PMOS晶体管的源极和第三PMOS晶体管的漏极，第三PMOS晶体管的源极连接电源VCC，电容器的下极板连接第五NMOS晶体管和第七NMOS晶体管的源极以及第四NMOS晶体管和第六NMOS晶体管的漏极，第四NMOS晶体管的源极接地，第六NMOS晶体管的源极与主开关晶体管的源极连接。The CMOS master-slave sample-and-hold circuit according to claim 3, wherein the sampling switch is a bootstrap switch, including a first inverter, a second inverter, a third inverter, and a fourth reverse Phase comparator, third NMOS transistor, fourth NMOS transistor, fifth NMOS transistor, sixth NMOS transistor, seventh NMOS transistor, first PMOS transistor, second PMOS transistor, third PMOS transistor, capacitor, and main switching transistor; The source of the main switching transistor is connected to the input signal, the drain is connected to the upper plate of the sampling capacitor, and the gate is connected to the gates of the sixth NMOS transistor, the seventh NMOS transistor and the third PMOS transistor, the first inverter The input end is connected to the internal clock signal, the output end is connected to the input ends of the second inverter and the third inverter, the output end of the second inverter is connected to the source of the third NMOS transistor, and the third inverter is The output terminal is connected to the input end of the fourth inverter, the gates of the second PMOS transistor and the fifth NMOS transistor, and the output end of the fourth inverter is connected to the gate of the fourth NMOS transistor, the first inverter and the second Inverter, third The phase converter and the fourth inverter are CMOS static logic gate circuits, which are powered by a power supply VCC, the gate of the third NMOS transistor is connected to the power supply VCC, and the drain is connected to the gate of the main switching transistor and the drain of the first PMOS transistor, The gate of a PMOS transistor is connected to the drains of the second PMOS transistor, the fifth NMOS transistor and the seventh NMOS transistor, and the upper plate of the capacitor is connected to the source of the first PMOS transistor and the drain of the third PMOS transistor, the third PMOS The source of the transistor is connected to the power source VCC, the lower plate of the capacitor is connected to the source of the fifth NMOS transistor and the seventh NMOS transistor, and the drains of the fourth NMOS transistor and the sixth NMOS transistor, the source of the fourth NMOS transistor is grounded, The source of the six NMOS transistor is connected to the source of the main switching transistor.
根据权利要求1所述的CMOS主从式采样保持电路，其特征在于，所述级间缓冲放大器采用单端电路形式，包括第八NMOS晶体管、第九NMOS晶体管、第一电阻器和第二电阻器，所述第八NMOS晶体管为工作晶体管，其栅极与主采样保持电路输出的第一采样信号连接，漏极输出缓冲后的第一采样信号，源极连接第一电阻器的一端，第一电阻器的另一端接地；所述第九NMOS晶体管为负载晶体管，其栅极连接第二偏置电压，漏极连接电源VCC，源极连接第二电阻器的一端，第二电阻器的另一端与第八NMOS晶体管的漏极连接。The CMOS master-slave sample-and-hold circuit of claim 1 wherein said interstage buffer amplifier is in the form of a single-ended circuit comprising an eighth NMOS transistor a body tube, a ninth NMOS transistor, a first resistor and a second resistor, the eighth NMOS transistor being a working transistor, the gate of which is connected to the first sampling signal output by the main sample-and-hold circuit, and the drain output is buffered a first sampling signal, the source is connected to one end of the first resistor, and the other end of the first resistor is grounded; the ninth NMOS transistor is a load transistor, the gate is connected to the second bias voltage, and the drain is connected to the power source VCC. The source is connected to one end of the second resistor, and the other end of the second resistor is connected to the drain of the eighth NMOS transistor.
根据权利要求5所述的CMOS主从式采样保持电路，其特征在于，所述第八NMOS晶体管和第九NMOS晶体管的跨导相等，且所述第一电阻器和第二电阻器的阻值相等。The CMOS master-slave sample-and-hold circuit according to claim 5, wherein a transconductance of said eighth NMOS transistor and said ninth NMOS transistor are equal, and resistance values of said first resistor and said second resistor equal.
根据权利要求1所述的CMOS主从式采样保持电路，其特征在于，所述时钟电路包括第一与非门、第二与非门、第五反相器、第六反相器、第七反相器和数字缓冲器，所述第五反相器和数字缓冲器的输入端接收外部时钟信号，第五反相器的输出端与第一与非门的第一输入端连接，数字缓冲器的输出端与第二与非门的第一输入端连接，第一与非门的输出端与第六反相器的输入端和第二与非门的第二输入端连接，第二与非门的输出端与第七反相器的输入端和第一与非门的第二输入端连接，第六反相器的输出端输出第一内部时钟信号，第七反相器的输出端输出第二内部时钟信号。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said clock circuit comprises a first NAND gate, a second NAND gate, a fifth inverter, a sixth inverter, and a seventh An inverter and a digital buffer, the input of the fifth inverter and the digital buffer receives an external clock signal, and the output of the fifth inverter is connected to the first input of the first NAND gate, the digital buffer The output end of the device is connected to the first input end of the second NAND gate, and the output end of the first NAND gate is connected to the input end of the sixth inverter and the second input end of the second NAND gate, the second The output end of the NOT gate is connected to the input end of the seventh inverter and the second input end of the first NAND gate, and the output end of the sixth inverter outputs a first internal clock signal, and the output end of the seventh inverter The second internal clock signal is output.
根据权利要求1所述的CMOS主从式采样保持电路，其特征在于，所述输入缓冲放大器采用差分电路形式，其包括两个单端电路形式，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括第一NMOS晶体管和第二NMOS晶体管，所述第一NMOS晶体管为工作晶体管，其栅极接收外部输入的模拟信号，源极输出缓冲后的模拟信号，漏极连接电源VCC；所述第二NMOS晶体管为偏置晶体管，其漏极连接第一NMOS晶体管的源极，为第一NMOS晶体管提供偏置电流，源极接地，栅极连接第一偏置电压。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said input buffer amplifier is in the form of a differential circuit comprising two single-ended circuits, and two single-ended circuits are respectively used for processing differential signals. a positive phase portion and an inverting portion, each single-ended circuit comprising a first NMOS transistor and a second NMOS transistor, the first NMOS transistor being a working transistor, the gate receiving an externally input analog signal, and the source output buffered Analog signal, the drain is connected to the power supply VCC; the second NMOS transistor is a bias transistor, the drain is connected to the source of the first NMOS transistor, the bias current is supplied to the first NMOS transistor, the source is grounded, and the gate is connected First offset Voltage.
根据权利要求1所述的CMOS主从式采样保持电路，其特征在于，所述主采样保持电路和从采样保持电路均采用差分电路形式并具有相同的电路结构，其包括两个单端电路形式，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括采样开关和采样电容，所述采样电容的下极板接地，上极板连接采样开关的一端，采样开关的另一端连接输入信号，采样开关的控制端与内部时钟信号连接，且所述采样电容上极板信号作为主从采样保持电路的输出采样信号。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said main sample-and-hold circuit and the slave sample-and-hold circuit both adopt a differential circuit form and have the same circuit structure, and include two single-ended circuit forms. Two single-ended circuits are respectively used for processing the positive phase portion and the inverted phase portion of the differential signal. Each single-ended circuit includes a sampling switch and a sampling capacitor. The lower plate of the sampling capacitor is grounded, and the upper plate is connected to the sampling switch. At one end, the other end of the sampling switch is connected to the input signal, the control end of the sampling switch is connected to the internal clock signal, and the upper plate signal of the sampling capacitor is used as the output sampling signal of the master-slave sampling and holding circuit.
根据权利要求1所述的CMOS主从式采样保持电路，其特征在于，所述级间缓冲放大器采用差分电路形式，其包括两个单端电路形式和尾电流源，两个单端电路分别用于处理差分信号中的正相部分和反相部分，每个单端电路包括第八NMOS晶体管、第九NMOS晶体管、第一电阻器和第二电阻器，所述第八NMOS晶体管为工作晶体管，其栅极与主采样保持电路输出的第一采样信号连接，漏极输出缓冲后的第一采样信号，源极连接第一电阻器的一端，第一电阻器的另一端经尾电流源接地；所述第九NMOS晶体管为负载晶体管，其栅极连接第二偏置电压，漏极连接电源VCC，源极连接第二电阻器的一端，第二电阻器的另一端与第八NMOS晶体管的漏极连接。 The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said interstage buffer amplifier is in the form of a differential circuit comprising two single-ended circuit forms and a tail current source, and two single-ended circuits are respectively used. Processing a positive phase portion and an inverting portion of the differential signal, each single-ended circuit comprising an eighth NMOS transistor, a ninth NMOS transistor, a first resistor, and a second resistor, the eighth NMOS transistor being a working transistor, The gate is connected to the first sampling signal outputted by the main sample-and-hold circuit, the drain outputs the buffered first sampling signal, the source is connected to one end of the first resistor, and the other end of the first resistor is grounded via the tail current source; The ninth NMOS transistor is a load transistor, the gate thereof is connected to the second bias voltage, the drain is connected to the power source VCC, the source is connected to one end of the second resistor, and the other end of the second resistor is connected to the drain of the eighth NMOS transistor. Extremely connected.