CN112422128A - Dynamic comparator and method for analog-to-digital converter offset calibration - Google Patents
Dynamic comparator and method for analog-to-digital converter offset calibration Download PDFInfo
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- CN112422128A CN112422128A CN202011502981.1A CN202011502981A CN112422128A CN 112422128 A CN112422128 A CN 112422128A CN 202011502981 A CN202011502981 A CN 202011502981A CN 112422128 A CN112422128 A CN 112422128A
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Abstract
The invention belongs to the field of analog integrated circuits, and particularly relates to a dynamic comparator and a method for offset calibration of an analog-to-digital converter, wherein the dynamic comparator comprises a first-stage preamplifier, a second-stage preamplifier, a third-stage preamplifier, a fourth-stage preamplifier and a latch which are sequentially connected; the input end of the first-stage preamplifier is connected with the input signal switch and the first switch, and the output end of the first-stage preamplifier is connected with the upper-stage plate of the first calibration capacitor; the input end of the second-stage preamplifier is connected with the second switch and the lower-stage plate of the first calibration capacitor, and the output end of the second-stage preamplifier is connected with the upper-stage plate of the second calibration capacitor; the input end of the third-stage preamplifier is connected with the third switch and the lower-stage plate of the second calibration capacitor, and the output end of the third-stage preamplifier is connected with the upper-stage plate of the third calibration capacitor; the input end of the four-stage preamplifier is connected with the fourth switch and the lower-stage plate of the third calibration capacitor, the output end of the four-stage preamplifier is connected with the input end of the latch, and the output end of the latch is connected with the direction device. The invention has the advantages of small offset voltage, low noise and high speed.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a dynamic comparator and a method for offset calibration of an analog-to-digital converter.
Background
In the real world, signals are mostly continuous analog quantity, and in the field of signal processing, digital signals have the characteristics of strong anti-interference capability, strong encryption, easier processing and the like. Therefore, in the signal processing process, the analog signal is generally converted into a digital signal; the signals are processed in various types in the digital field. Therefore, in the signal processing system, an analog-to-digital converter is required to sample, quantize, encode and convert an actual analog signal into a digital signal, and then perform digital signal processing through a corresponding processing system. The analog-to-digital converter is an important functional module in the signal processing system.
A dynamic comparator (abbreviated as comparator) for offset calibration of an analog-to-digital converter (including a successive approximation register analog-to-digital converter) is a key circuit inside the analog-to-digital converter, and the performance of the comparator is crucial to ensure various performance indexes of the analog-to-digital converter. Currently, most analog-to-digital converters use a conventional two-stage comparator, including a pre-amplification circuit and a latch circuit. The conventional two-stage comparator has the main defect of high noise, and the reduction of the noise usually requires the increase of the capacitive load of an output node, thereby causing the increase of the chip area and further affecting the overall performance of the analog-to-digital converter.
Disclosure of Invention
The object of the present invention is to overcome the drawbacks of the prior art described above, and is achieved by the following technical solution:
a dynamic comparator for analog-to-digital converter offset calibration comprises a first-stage preamplifier, a second-stage preamplifier, a third-stage preamplifier, a fourth-stage preamplifier and a latch which are sequentially connected;
the input end of the first-stage preamplifier is respectively connected with an input signal switch and one end of a first switch, the other end of the input signal switch is connected with an input signal, and the other end of the first switch is connected with a common-mode signal; the output end of the primary preamplifier is connected with an upper-level plate of the first calibration capacitor;
the input end of the second-stage preamplifier is respectively connected with one end of a second switch and a lower-stage plate of the first calibration capacitor, and the other end of the second switch is connected with the common-mode signal; the output end of the secondary preamplifier is connected with the upper-level plate of the second calibration capacitor;
the input end of the third-stage preamplifier is respectively connected with one end of a third switch and a lower-stage plate of the second calibration capacitor, and the other end of the third switch is connected with a common-mode signal; the output end of the third-stage preamplifier is connected with the upper-stage plate of the third calibration capacitor;
the input end of the fourth-stage preamplifier is respectively connected with one end of a fourth switch and a lower-stage plate of the third calibration capacitor, and the other end of the fourth switch is connected with the common-mode signal; the output end of the four-stage preamplifier is connected with the input end of the latch, and the output end of the latch is connected with the direction device.
On the basis of the technical scheme, the invention can be added with the following technical means so as to better or more specifically realize the purpose of the invention:
the first-stage, second-stage, third-stage and fourth-stage pre-amplifiers all have the same circuit structure, and each stage of pre-amplifier comprises a first metal oxide semiconductor tube, a second metal oxide semiconductor tube, a third metal oxide semiconductor tube, a fourth metal oxide semiconductor tube, a fifth metal oxide semiconductor tube and a sixth metal oxide semiconductor tube.
Further, the first metal oxide semiconductor tube and the second metal oxide semiconductor tube form a differential input pair tube; the drains of the first metal oxide semiconductor tube and the second metal oxide semiconductor tube are connected with a power supply; the grid electrode of the first metal oxide semiconductor tube is respectively connected with the positive differential input signal, and the grid electrode of the second metal oxide semiconductor tube is connected with the negative differential input signal; the source electrode of the first metal oxide semiconductor tube is connected with the drain electrode of the fourth metal oxide semiconductor tube, and the source electrode of the second metal oxide semiconductor tube is connected with the drain electrode of the fifth metal oxide semiconductor tube.
Furthermore, the gate of the third metal oxide semiconductor transistor is connected with the clock signal, the drain of the third metal oxide semiconductor transistor is connected with the source of the first metal oxide semiconductor transistor, and the source of the third metal oxide semiconductor transistor is connected with the source of the second metal oxide semiconductor transistor.
Furthermore, the fourth metal oxide semiconductor tube and the fifth metal oxide semiconductor tube are connected in a diode manner; the drain electrode of the fourth metal oxide semiconductor tube is connected with the source electrode of the first metal oxide semiconductor tube, and the drain electrode of the fifth metal oxide semiconductor tube is connected with the source electrode of the second metal oxide semiconductor tube; the grid electrodes of the fourth metal oxide semiconductor tube and the fifth metal oxide semiconductor tube are respectively connected with the drain electrodes of the fourth metal oxide semiconductor tube and the fifth metal oxide semiconductor tube; the source electrodes of the fourth metal oxide semiconductor tube and the fifth metal oxide semiconductor tube are connected to the drain electrode of the sixth metal oxide semiconductor tube; the sixth metal oxide semiconductor tube is used as a tail current source generating tube, the grid electrode of the sixth metal oxide semiconductor tube is connected with the bias voltage circuit, and the source electrode of the sixth metal oxide semiconductor tube is logically grounded.
Further, the latch comprises five N-type metal oxide semiconductor transistors and eight P-type metal oxide semiconductor transistors; the five N-type metal oxide semiconductor tubes are a first N-type metal oxide semiconductor tube, a second N-type metal oxide semiconductor tube, a third N-type metal oxide semiconductor tube, a fourth N-type metal oxide semiconductor tube and a fifth N-type metal oxide semiconductor tube in sequence; the eight P-type metal oxide semiconductor tubes are a first P-type metal oxide semiconductor tube, a second P-type metal oxide semiconductor tube, a third P-type metal oxide semiconductor tube, a fourth P-type metal oxide semiconductor tube, a fifth P-type metal oxide semiconductor tube, a sixth P-type metal oxide semiconductor tube, a seventh P-type metal oxide semiconductor tube and an eighth P-type metal oxide semiconductor tube in sequence.
Furthermore, the first N-type metal oxide semiconductor tube and the second N-type metal oxide semiconductor tube are input tubes; the drain electrode of the first N-type metal oxide semiconductor tube is connected with the source electrodes of the fourth N-type metal oxide semiconductor tube and the fifth P-type metal oxide semiconductor tube, and the grid electrode of the first N-type metal oxide semiconductor tube is connected with the positive differential input signal; the drain electrode of the second N-type metal oxide semiconductor tube is connected with the source electrodes of the fifth N-type metal oxide semiconductor tube and the sixth P-type metal oxide semiconductor tube, and the grid electrode of the second N-type metal oxide semiconductor tube is connected with the negative differential input signal; the source electrodes of the first N-type metal oxide semiconductor tube and the second N-type metal oxide semiconductor tube are connected to the drain electrode of the third N-type metal oxide semiconductor tube together; the grid electrode of the third N-type metal oxide semiconductor tube is connected with the clock signal, and the source electrode of the third N-type metal oxide semiconductor tube is grounded.
Furthermore, the drain of the fourth N-type mos transistor is connected to the source of the first P-type mos transistor, the gate of the fifth N-type mos transistor, and the gate of the second P-type mos transistor, and serves as a negative voltage output node; the grid electrode of the fourth N-type metal oxide semiconductor tube is connected with the grid electrode of the first P-type metal oxide semiconductor tube and the drain electrode of the eighth P-type metal oxide semiconductor tube; the source electrode of the fourth N-type metal oxide semiconductor tube is connected with the drain electrode of the first P-type metal oxide semiconductor tube and the source electrode of the fifth P-type metal oxide semiconductor tube.
Furthermore, the drain of the fifth N-type metal oxide semiconductor tube is connected with the source of the second P-type metal oxide semiconductor tube, the fourth N-type metal oxide semiconductor tube and the gate of the first P-type metal oxide semiconductor tube, and is used as a positive voltage output node; the grid electrode of the fifth N-type metal oxide semiconductor tube is connected with the grid electrode of the second P-type metal oxide semiconductor tube and the drain electrode of the eighth P-type metal oxide semiconductor tube, and the source electrode of the fifth N-type metal oxide semiconductor tube is connected with the drain electrode of the second N-type metal oxide semiconductor tube and the source electrode of the sixth P-type metal oxide semiconductor tube.
Furthermore, the drain of the first P-type metal oxide semiconductor transistor is connected to the power supply, the gate thereof is connected to the gate of the fourth N-type metal oxide semiconductor transistor, the drain of the fifth N-type metal oxide semiconductor transistor, and the source of the second P-type metal oxide semiconductor transistor, and the source thereof is connected to the drain of the fourth N-type metal oxide semiconductor transistor and the source of the third P-type metal oxide semiconductor transistor.
The invention also provides a control method of the dynamic comparator for the offset calibration of the analog-to-digital converter, which carries out state control through a clock signal CLK and a calibration control signal OS, and comprises three working states of an offset calibration stage, a reset stage and a comparison stage, wherein when the calibration control signal OS is equal to 1, the dynamic comparator is in the offset calibration stage; the dynamic comparator is in a reset phase when the calibration control signal OS is 0 and the clock signal CLK is 0, and in a compare phase when the calibration control signal OS is 0 and the clock signal CLK is 1.
The invention has the following beneficial effects:
through the coordination work of the first-stage preamplifier, the second-stage preamplifier, the third-stage preamplifier and the latch, the invention has the advantages of small offset voltage, low noise and high speed, thereby effectively realizing the high-precision and high-speed design of the analog-to-digital converter and obviously improving the speed and the precision of the analog-to-digital converter.
Drawings
FIG. 1 is a schematic diagram of the general structure of one embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a preamplifier according to an embodiment of the invention;
FIG. 3 is a circuit diagram of a latch according to an embodiment of the present invention;
FIG. 4 is a waveform diagram of clock signals and control signals during operation according to one embodiment of the present invention.
Detailed Description
The technical solution and the working method thereof of the present invention are described in detail below by an embodiment with reference to the accompanying drawings.
As shown in fig. 1, a dynamic comparator for offset calibration of an analog-to-digital converter includes a first-stage preamplifier, a second-stage preamplifier, a third-stage preamplifier, a fourth-stage preamplifier, and a LATCH (LATCH COMP) connected in sequence.
The input end of the primary preamplifier is respectively connected with an input signal switch S0 and one end of a first switch S1, the other end of the input signal switch S0 is connected with an input signal, and the other end of the first switch S1 is connected with a common-mode signal VCM; the output end of the primary preamplifier is connected with the upper plate of the first calibration capacitor C1.
The input end of the second-stage preamplifier is respectively connected with one end of a second switch S2 and the lower plate of the calibration capacitor C1, and the other end of the second switch S2 is connected with the common-mode signal VCM; the output of the second-stage preamplifier is connected to the upper stage of a second calibration capacitor C2.
The input end of the third-stage preamplifier is respectively connected with one end of a third switch S3 and the lower plate of a second calibration capacitor C2, and the other end of the third switch S3 is connected with the common-mode signal VCM; the output of the three-stage preamplifier is connected to the upper stage of a third calibration capacitor C3.
The input end of the four-stage preamplifier is respectively connected with one end of a fourth switch S4 and the lower plate of a third calibration capacitor C3, and the other end of the fourth switch S4 is connected with a common-mode signal VCM; the output of the four-stage preamplifier is connected to the input of a LATCH (LATCH COMP), the output of which is connected to a direction director (DOUTP, DOUTN).
As shown in fig. 2, in the present embodiment, the first-stage, second-stage, third-stage and fourth-stage preamplifiers all have the same circuit structure, and each of the first-stage, second-stage, third-stage and fourth-stage preamplifiers includes six Metal Oxide Semiconductor (MOS) transistors, that is, a first metal oxide semiconductor transistor M1, a second metal oxide semiconductor transistor M2, a third metal oxide semiconductor transistor M3, a fourth metal oxide semiconductor transistor M4, a fifth metal oxide semiconductor transistor M5 and a sixth metal oxide semiconductor transistor M6.
The first metal oxide semiconductor transistor M1 and the second metal oxide semiconductor transistor M2 form a differential input pair transistor; the drains of the first and second MOS transistors M1 and M2 are connected to a power supply VDD; the gate of the first MOS transistor M1 is connected to the positive differential input signal VIN +, and the gate of the second MOS transistor M2 is connected to the negative differential input signal VIN-; the source of the first MOS transistor M1 is connected to the drain of the fourth MOS transistor M4, and the source of the second MOS transistor M2 is connected to the drain of the fifth MOS transistor M5.
The gate of the third mos transistor M3 is connected to the clock signal CLK, the drain of the third mos transistor M3 is connected to the source of the first mos transistor M1, and the source of the third mos transistor M3 is connected to the source of the second mos transistor M3.
The fourth metal oxide semiconductor transistor M4 and the fifth metal oxide semiconductor transistor M5 are connected in a diode manner; the drain of the fourth metal oxide semiconductor transistor M4 is connected with the source of the first metal oxide semiconductor transistor M1, and the drain of the fifth metal oxide semiconductor transistor M5 is connected with the source of the second metal oxide semiconductor transistor M2; the gates of the fourth metal oxide semiconductor transistor M4 and the fifth metal oxide semiconductor transistor M5 are respectively connected with the drains thereof; the sources of the fourth and fifth MOS transistors M4 and M5 are commonly connected to the drain of the sixth MOS transistor M6; the sixth mos transistor M6 serves as a tail current source generating transistor, and has a gate connected to the bias voltage circuit VB and a source logically grounded.
As shown in fig. 3, in the present embodiment, the latch includes five N-type metal oxide semiconductor transistors (NMOS transistors) and eight P-type metal oxide semiconductor transistors (PMOS transistors). The five N-type mos transistors are, in order, a first N-type mos transistor NM1, a second N-type mos transistor NM2, a third N-type mos transistor NM3, a fourth N-type mos transistor NM4, and a fifth N-type mos transistor NM. The eight P-type metal oxide semiconductor tubes are a first P-type metal oxide semiconductor tube PM1, a second P-type metal oxide semiconductor tube PM7, a third P-type metal oxide semiconductor tube PM3, a fourth P-type metal oxide semiconductor tube PM4, a fifth P-type metal oxide semiconductor tube PM5, a sixth P-type metal oxide semiconductor tube PM6, a seventh P-type metal oxide semiconductor tube PM7 and an eighth P-type metal oxide semiconductor tube PM8 in sequence.
The first N-type MOS NM1 and the second N-type MOS NM2 are input transistors; the drain of the first nmos 1 is connected to the sources of the fourth nmos 4 and the fifth pmos PM5, the source of the seventh pmos PM7 is connected, and the gate is connected to the positive differential input signal VIN +; the drain of the second nmos 2 is connected to the sources of the fifth and sixth nmos 5, PM6, and the drain of the seventh pmos PM7, and the gate is connected to the negative differential input signal VIN- (differential input, i.e., differential output of the four-stage preamplifier); the sources of the first and second nmos 1, NM2 are commonly connected to the drain of the third nmos 3; the gate of the third nmos 3 is connected to the clock signal CLK, and the source is connected to the ground GND.
The drain of the fourth nmos 4 is connected to the source of the first P-type mos PM1, the source of the third P-type mos PM3, the gate of the fifth N-type mos NM5, and the gate of the second P-type mos PM2, respectively, and serves as a negative voltage output node VO-; the gate of the fourth nmos 4 is connected to the gate of the first pmos PM1 and the drain of the eighth pmos PM8, respectively; the source of the fourth nmos 4 is connected to the drain of the first nmos 1 and the source of the fifth P-type mos PM5, respectively.
The drain of the fifth N-type mos 5 is connected to the source of the second P-type mos PM2, the source of the fourth P-type mos 4, the gate of the fourth N-type mos 4, and the gate of the first P-type mos PM1, respectively, and serves as a positive voltage output node VO +; the gate of the fifth nmos 5 is connected to the gate of the second P-type mos PM2 and the drain of the eighth P-type mos PM8, and the source thereof is connected to the drain of the second N-type mos NM2 and the source of the sixth P-type mos PM 6.
The drain of the first P-type mos transistor PM1 is connected to the power supply VDD, the gate thereof is connected to the gate of the fourth N-type mos transistor NM4, the drain of the fifth N-type mos transistor NM5, and the source of the second P-type mos transistor PM2, respectively, and the source thereof is connected to the drain of the fourth N-type mos transistor NM4 and the source of the third P-type mos transistor PM 3.
The drain of the second P-type mos transistor PM2 is connected to the power supply VDD, the gate thereof is connected to the gate of the fifth N-type mos transistor NM5, the drain of the fourth N-type mos transistor NM4, and the source of the first P-type mos transistor PM1, and the source thereof is connected to the drain of the fifth N-type mos transistor NM5 and the source of the fourth P-type mos transistor PM 4.
The source of the third pmos PM3 is connected to the power supply VDD, the gate thereof is connected to the clock signal circuit CLK, and the source thereof is connected to the drain of the fourth nmos 4 and the source of the first pmos PM 1.
The source of the fourth pmos PM4 is connected to the power supply VDD, the gate thereof is connected to the clock signal circuit CLK, and the source thereof is connected to the drain of the fifth nmos 5 and the source of the second pmos PM 2.
The fifth pmos PM5 has a source connected to the power supply VDD, a gate connected to the clock signal circuit CLK, and a source connected to the drain of the first nmos 1, the source of the fourth nmos 4, and the drain of the seventh pmos PM 7.
The sixth pmos PM6 has a source connected to the power supply VDD, a gate connected to the clock signal CLK, and a source connected to the drain of the second nmos 2, the source of the fifth nmos 5, and the source of the seventh pmos PM 7.
The drain of the seventh P-type mos PM7 is connected to the drain of the first N-type mos 1, the source of the fifth P-type mos PM5, and the source of the fourth N-type mos 4, respectively, the gate thereof is connected to the gate of the eighth P-type mos PM8 and receives the clock signal CLK, and the source thereof is connected to the drain of the second N-type mos NM2, the source of the sixth P-type mos PM6, and the source of the fifth N-type mos NM 5.
The drain of the eighth P-type mos PM8 is connected to the gate of the fourth N-type mos NM4, the gate of the first P-type mos PM1, the drain of the fifth N-type mos NM5, and the source of the second P-type mos PM2, respectively, the gate thereof is connected to the gate of the seventh P-type mos PM7, the clock signal CLK is asserted, and the source thereof is connected to the gate of the fifth N-type mos NM5, the gate of the second P-type mos PM2, the drain of the fourth N-type mos NM4, and the source of the first P-type mos PM 1.
The structural features of an embodiment of the present invention are described in detail above with reference to the accompanying drawings, and the operation thereof is further described below.
When the dynamic comparator (hereinafter referred to as comparator) for analog-to-digital converter offset calibration works, the state control is carried out through the clock signal CLK and the calibration control signal OS. The working process of the comparator can be basically divided into three main working states, namely an offset calibration stage, a reset stage, a comparison stage and the like.
In the offset calibration phase, the calibration control signal OS is 1, and there are two sub-states, a measurement state and a calibration state. In the measuring state, the input end of the preamplifier is connected to the common-mode signal VCM through the switch, the lower plates of the first to third calibration capacitors (C1-C3) are also connected to the common-mode signal VCM, and the output end of the preamplifier is VOUT (VOS), namely the voltage of the test calibration capacitor for storing the VOS. In the calibration state, the first to fourth switches (S1-S4) are all closed, the input end of the comparator is connected to the differential input signal, and the output voltage VOUT is a (VIN-VOS), and after the capacitor is calibrated, the output voltage VOUT is a (VIN-VOS) + a VOS) a (VIN); further, the offset voltage calibration function is realized, and the offset voltage can be completely eliminated theoretically. In the control process of calibrating the capacitor, the opening time of the switch connected with the capacitor needs to have a certain sequence so as to ensure the normal work of the comparator. The waveforms of the clock signal and the control signal in this process are shown in fig. 4.
In the reset stage, when the calibration control signal OS is 0 and the clock signal CLK is 0, the third MOS transistor M3 in fig. 2 is turned off, and other MOS transistors (MOS transistors) operate normally, so that the whole circuit structure realizes the offset voltage calibration of each stage of the preamplifier; at this time, the dynamic latch is in a closed state, the tail current source of the fourth N-type mos M4 in fig. 3 is turned off, the circuit nodes VO +, VO-, M +, M-are charged to the power supply VDD potential through the reset transistors such as the third to sixth P-type mos (PM3, PM4, PM5, PM6) and the like, and the seventh and eighth P-type mos (PM7, PM8) are turned on, so that the voltage balance between the circuit nodes M + and M-, VO +, and VO-is ensured.
In the comparison stage, when the calibration control signal OS is 0 and the clock signal CLK is 1, the third MOS transistor M3 in fig. 2 is turned on, the other MOS transistors (MOS transistors) operate normally, the fourth and fifth MOS transistors (NM4 and NM5) may be regarded as a load resistor, and the fourth-stage preamplifier operates normally to amplify the input signal. The tail current of the third nmos transistor M3 in the latch of fig. 3 is turned on and all reset transistors are turned off, and at this time, the first and second nmos transistors (NM1, NM2) as input pair transistors start to operate. The different grid voltages of the first and second metal oxide semiconductor tubes (NM1, NM2) cause different conduction currents, thereby causing different discharge speeds of the two points M + and M-, and consequently causing different potentials of M + and M-. If V IN + > VIN-, then M-falls faster than M +, and therefore the fourth MOS transistor M4 first enters the conducting state, resulting IN the negative voltage output VO-falling first. When VO-begins to drop to the second PMOS transistor M7 conducting, the positive voltage output VO + node begins to charge. And an inverter formed by the fourth and fifth N-type metal oxide semiconductor transistors (NM4 and NM5) and the first and second P-type metal oxide semiconductor transistors (PM1 and PM2) finally enables the negative voltage output VO-to fall to the ground GND, and the positive voltage output VO + is charged to the power supply VDD, so that the effect of information latching is achieved.
Claims (10)
1. A dynamic comparator for analog-to-digital converter offset calibration, comprising a first-stage preamplifier, a second-stage preamplifier and a latch, characterized in that: the system also comprises a three-stage preamplifier and a four-stage preamplifier; the first-stage preamplifier, the second-stage preamplifier, the third-stage preamplifier, the fourth-stage preamplifier and the latch are sequentially connected;
the input end of the first-stage preamplifier is respectively connected with an input signal switch and one end of a first switch, the other end of the input signal switch is connected with an input signal, and the other end of the first switch is connected with a common-mode signal; the output end of the primary preamplifier is connected with an upper-level plate of the first calibration capacitor;
the input end of the second-stage preamplifier is respectively connected with one end of a second switch and a lower-stage plate of the first calibration capacitor, and the other end of the second switch is connected with the common-mode signal; the output end of the secondary preamplifier is connected with the upper-level plate of the second calibration capacitor;
the input end of the third-stage preamplifier is respectively connected with one end of a third switch and a lower-stage plate of the second calibration capacitor, and the other end of the third switch is connected with a common-mode signal; the output end of the third-stage preamplifier is connected with the upper-stage plate of the third calibration capacitor;
the input end of the fourth-stage preamplifier is respectively connected with one end of a fourth switch and a lower-stage plate of the third calibration capacitor, and the other end of the fourth switch is connected with the common-mode signal; the output end of the four-stage preamplifier is connected with the input end of the latch, and the output end of the latch is connected with the direction device.
2. The dynamic comparator for analog-to-digital converter offset calibration of claim 1, wherein: the first-stage, second-stage, third-stage and fourth-stage pre-amplifiers all have the same circuit structure, and each stage of pre-amplifier comprises a first metal oxide semiconductor tube, a second metal oxide semiconductor tube, a third metal oxide semiconductor tube, a fourth metal oxide semiconductor tube, a fifth metal oxide semiconductor tube and a sixth metal oxide semiconductor tube.
3. The dynamic comparator for analog-to-digital converter offset calibration of claim 2, wherein: the first metal oxide semiconductor tube and the second metal oxide semiconductor tube form a differential input geminate transistor; the drains of the first metal oxide semiconductor tube and the second metal oxide semiconductor tube are connected with a power supply; the grid electrode of the first metal oxide semiconductor tube is respectively connected with the positive differential input signal, and the grid electrode of the second metal oxide semiconductor tube is connected with the negative differential input signal; the source electrode of the first metal oxide semiconductor tube is connected with the drain electrode of the fourth metal oxide semiconductor tube, and the source electrode of the second metal oxide semiconductor tube is connected with the drain electrode of the fifth metal oxide semiconductor tube.
4. The dynamic comparator for analog-to-digital converter offset calibration of claim 2, wherein: the grid electrode of the third metal oxide semiconductor tube is connected with a clock signal, the drain electrode of the third metal oxide semiconductor tube is connected with the source electrode of the first metal oxide semiconductor tube, and the source electrode of the third metal oxide semiconductor tube is connected with the source electrode of the second metal oxide semiconductor tube.
5. The dynamic comparator for analog-to-digital converter offset calibration of claim 2, wherein: the fourth metal oxide semiconductor tube and the fifth metal oxide semiconductor tube are connected in a diode connection mode; the drain electrode of the fourth metal oxide semiconductor tube is connected with the source electrode of the first metal oxide semiconductor tube, and the drain electrode of the fifth metal oxide semiconductor tube is connected with the source electrode of the second metal oxide semiconductor tube; the grid electrodes of the fourth metal oxide semiconductor tube and the fifth metal oxide semiconductor tube are respectively connected with the drain electrodes of the fourth metal oxide semiconductor tube and the fifth metal oxide semiconductor tube; the source electrodes of the fourth metal oxide semiconductor tube and the fifth metal oxide semiconductor tube are connected to the drain electrode of the sixth metal oxide semiconductor tube; the sixth metal oxide semiconductor tube is used as a tail current source generating tube, the grid electrode of the sixth metal oxide semiconductor tube is connected with the bias voltage circuit, and the source electrode of the sixth metal oxide semiconductor tube is logically grounded.
6. The dynamic comparator for analog-to-digital converter offset calibration of claim 1, wherein: the latch comprises five N-type metal oxide semiconductor transistors and eight P-type metal oxide semiconductor transistors; the five N-type metal oxide semiconductor tubes are a first N-type metal oxide semiconductor tube, a second N-type metal oxide semiconductor tube, a third N-type metal oxide semiconductor tube, a fourth N-type metal oxide semiconductor tube and a fifth N-type metal oxide semiconductor tube in sequence; the eight P-type metal oxide semiconductor tubes are a first P-type metal oxide semiconductor tube, a second P-type metal oxide semiconductor tube, a third P-type metal oxide semiconductor tube, a fourth P-type metal oxide semiconductor tube, a fifth P-type metal oxide semiconductor tube, a sixth P-type metal oxide semiconductor tube, a seventh P-type metal oxide semiconductor tube and an eighth P-type metal oxide semiconductor tube in sequence.
7. The dynamic comparator for analog-to-digital converter offset calibration of claim 6, wherein: the first N-type metal oxide semiconductor tube and the second N-type metal oxide semiconductor tube are input tubes; the drain electrode of the first N-type metal oxide semiconductor tube is connected with the source electrodes of the fourth N-type metal oxide semiconductor tube and the fifth P-type metal oxide semiconductor tube, and the grid electrode of the first N-type metal oxide semiconductor tube is connected with the positive differential input signal; the drain electrode of the second N-type metal oxide semiconductor tube is connected with the source electrodes of the fifth N-type metal oxide semiconductor tube and the sixth P-type metal oxide semiconductor tube, and the grid electrode of the second N-type metal oxide semiconductor tube is connected with the negative differential input signal; the source electrodes of the first N-type metal oxide semiconductor tube and the second N-type metal oxide semiconductor tube are connected to the drain electrode of the third N-type metal oxide semiconductor tube together; the grid electrode of the third N-type metal oxide semiconductor tube is connected with the clock signal, and the source electrode of the third N-type metal oxide semiconductor tube is grounded.
8. The dynamic comparator for analog-to-digital converter offset calibration of claim 6, wherein: the drain electrode of the fourth N-type metal oxide semiconductor transistor M4 is connected with the source electrode of the first P-type metal oxide semiconductor transistor, the gate electrode of the fifth N-type metal oxide semiconductor transistor and the gate electrode of the second P-type metal oxide semiconductor transistor, and is used as a negative voltage output node; the grid electrode of the fourth N-type metal oxide semiconductor tube is connected with the grid electrode of the first P-type metal oxide semiconductor tube and the drain electrode of the eighth P-type metal oxide semiconductor tube; the source electrode of the fourth N-type metal oxide semiconductor tube is connected with the drain electrode of the first P-type metal oxide semiconductor tube and the source electrode of the fifth P-type metal oxide semiconductor tube.
9. The dynamic comparator for analog-to-digital converter offset calibration of claim 6, wherein: the drain electrode of the fifth N-type metal oxide semiconductor tube is connected with the source electrode of the second P-type metal oxide semiconductor tube, the fourth N-type metal oxide semiconductor tube and the grid electrode of the first P-type metal oxide semiconductor tube and is used as a positive voltage output node; the grid electrode of the fifth N-type metal oxide semiconductor tube is connected with the grid electrode of the second P-type metal oxide semiconductor tube and the drain electrode of the eighth P-type metal oxide semiconductor tube, and the source electrode of the fifth N-type metal oxide semiconductor tube is connected with the drain electrode of the second N-type metal oxide semiconductor tube and the source electrode of the sixth P-type metal oxide semiconductor tube.
10. A control method of dynamic comparator for analog-to-digital converter offset calibration is provided, which performs state control by clock signal CLK and calibration control signal OS, and is characterized in that: the method comprises three working states of a maladjustment calibration stage, a reset stage and a comparison stage; when the calibration control signal OS is equal to 1, the dynamic comparator is in a maladjustment calibration stage; when the calibration control signal OS is 0 and the clock signal CLK is 0, the dynamic comparator is in a reset phase; when the calibration control signal OS is 0 and the clock signal CLK is 1, the dynamic comparator is in the comparison phase.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113452374A (en) * | 2021-07-07 | 2021-09-28 | 哈尔滨工业大学（威海） | Low-offset switch capacitor comparator |
| CN115709710A (en) * | 2022-12-15 | 2023-02-24 | 江苏润石科技有限公司 | Vehicle body stability control method, chip and system |
-
2020
- 2020-12-18 CN CN202011502981.1A patent/CN112422128A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113452374A (en) * | 2021-07-07 | 2021-09-28 | 哈尔滨工业大学（威海） | Low-offset switch capacitor comparator |
| CN115709710A (en) * | 2022-12-15 | 2023-02-24 | 江苏润石科技有限公司 | Vehicle body stability control method, chip and system |
| CN115709710B (en) * | 2022-12-15 | 2023-09-05 | 江苏润石科技有限公司 | Vehicle body stability control method, chip and system |
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