CN108768351A - The high speed dynamic comparer of low imbalance low-power consumption under a kind of low supply voltage - Google Patents
The high speed dynamic comparer of low imbalance low-power consumption under a kind of low supply voltage Download PDFInfo
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- CN108768351A CN108768351A CN201810541865.7A CN201810541865A CN108768351A CN 108768351 A CN108768351 A CN 108768351A CN 201810541865 A CN201810541865 A CN 201810541865A CN 108768351 A CN108768351 A CN 108768351A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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Abstract
The present invention discloses a kind of high speed dynamic comparer of low imbalance low-power consumption under low supply voltage, including：First order pre-amplification circuit receives in-phase input signals for 1, rp input signal, the first, second voltage bias signal, the first In-phase output signal of output, the first reversed-phase output signal；Second level pre-amplification circuit receives the first In-phase output signal, the first reversed-phase output signal and clock control signal, the second In-phase output signal of output, the second reversed-phase output signal；Cmos latch device circuit receives the second In-phase output signal, the second reversed-phase output signal and clock control signal, output third In-phase output signal, third reversed-phase output signal；Set-reset flip-floop circuit receives third In-phase output signal, third reversed-phase output signal, output In-phase output signal, reversed-phase output signal.The present invention is the high speed dynamic comparer realized at 1.05V, improves the speed of clock control signal, comparator is made still to have the advantages that good low maladjustment voltage, low-power consumption in high-frequency.
Description
Technical field
The invention belongs to the comparator technical fields in analog-digital converter, more particularly to dynamic under a kind of low supply voltage
State comparator.
Background technology
Due to the rapid development of semicon industry and integrated circuit technique so that analog-digital converter becomes electronic technology hair
The key point of exhibition.And comparator, as the core in analog-digital converter circuit, properties characteristic is to entire modulus
The performance of converter all has important influence.It is the supply voltage that circuit provides currently, with the development of integrated circuit technique
It gradually reduces, this just gives the design of traditional dynamic comparer to bring certain difficulty；And how at low supply voltages
It is urgently to be resolved hurrily to still ensure that property indices of comparator circuit, such as offset voltage, transmission delay, power consumption etc. become
Problem.
Invention content
The purpose of the present invention is to provide the high speed dynamic comparers under a kind of low supply voltage, can be in higher work
Under frequency, the property indices for promoting comparator circuit are remained able to, to realize the high-speed applications of analog-digital converter circuit.
To achieve the goals above, the present invention adopts the following technical scheme that：
The high speed dynamic comparer of low imbalance low-power consumption under a kind of low supply voltage, including sequentially connected biasing circuit,
First order pre-amplification circuit, second level pre-amplification circuit, cmos latch device circuit and set-reset flip-floop circuit；
The biasing circuit receives current source signal, output first voltage offset signal, second voltage offset signal；
The first order pre-amplification circuit receives in-phase input signals for 1, rp input signal, first voltage offset signal
With second voltage offset signal, the first In-phase output signal of output, the first reversed-phase output signal；
The second level pre-amplification circuit, receive the first In-phase output signal, the first reversed-phase output signal and when clock
Signal processed, the second In-phase output signal of output, the second reversed-phase output signal；
The cmos latch device circuit receives the second In-phase output signal, the second reversed-phase output signal and clock control
Signal, output third In-phase output signal, third reversed-phase output signal；
The set-reset flip-floop circuit receives third In-phase output signal, third reversed-phase output signal, exports with mutually output
Signal, reversed-phase output signal.
Further, the biasing circuit, including, the first NMOS transistor and the second NMOS transistor, wherein
The source electrode of first NMOS transistor is grounded；
The grid of first NMOS transistor is connected with drain electrode, is connected with the source electrode of second NMOS transistor；
The grid of second NMOS transistor is connected with drain electrode, is connected with current source signal；
The grid of first NMOS transistor exports first voltage offset signal；
The grid of second NMOS transistor exports second voltage offset signal.
Further, the first order pre-amplification circuit, including：Third NMOS transistor, the 4th NMOS transistor,
Five NMOS transistors, the 6th NMOS transistor, the 7th NMOS transistor, the first PMOS transistor, the second PMOS transistor, third
PMOS transistor and the 4th PMOS transistor, wherein
The grid of the third NMOS transistor receives the first biasing voltage signal；
The source electrode of the third NMOS transistor is grounded；
The draining of the third NMOS transistor, the source electrode of the 4th NMOS transistor, the 5th NMOS transistor
Source electrode be connected；
The grid of 4th NMOS transistor receives in-phase input signals for 1；
The grid of 5th NMOS transistor receives rp input signal；
The draining of 4th NMOS transistor, the source electrode of the 6th NMOS transistor is connected；
The draining of 5th NMOS transistor, the source electrode of the 7th NMOS transistor is connected；
The grid of 6th NMOS transistor, the grid of the 7th NMOS transistor are connected with second voltage offset signal
It connects；
The draining of 6th NMOS transistor, the draining of first PMOS transistor, the third PMOS transistor
Drain electrode be connected；
The draining of 7th NMOS transistor, the draining of second PMOS transistor, the 4th PMOS transistor
Drain electrode be connected；
The draining of first PMOS transistor, the grid of first PMOS transistor, second PMOS transistor
Grid be connected；
The grid of the third PMOS transistor, the draining of the 4th PMOS transistor, the 4th PMOS transistor
Grid be connected；
The source electrode of first PMOS transistor, the source electrode of second PMOS transistor, the third PMOS transistor
Source electrode, the 4th PMOS transistor source electrode be connected with supply voltage；
The drain electrode of 6th NMOS transistor exports the first In-phase output signal；
The drain electrode of 7th NMOS transistor exports the first reversed-phase output signal.
Further, the second level pre-amplification circuit, including：8th NMOS transistor, the 9th NMOS transistor,
Ten NMOS transistors, the 11st NMOS transistor and the tenth bi-NMOS transistor, wherein
The grid of 8th NMOS transistor, the grid of the 11st NMOS transistor, the 12nd NMOS are brilliant
The grid of body pipe receives clock control signal；
The draining of 8th NMOS transistor, the source electrode of the 9th NMOS transistor, the tenth NMOS transistor
Source electrode be connected；
The grid of 9th NMOS transistor receives the first reversed-phase output signal；
The grid of tenth NMOS transistor receives the first In-phase output signal；
The draining of 9th NMOS transistor, the source electrode of the 11st NMOS transistor is connected；
The draining of tenth NMOS transistor, the source electrode of the tenth bi-NMOS transistor is connected；
The source electrode of 8th NMOS transistor is connected to the ground；
The drain electrode of 11st NMOS transistor exports the second reversed-phase output signal；
The drain electrode of tenth bi-NMOS transistor exports the second In-phase output signal.
Further, the cmos latch device circuit, including：13rd NMOS transistor, the 14th NMOS transistor,
15th NMOS transistor, the 16th NMOS transistor, the 17th NMOS transistor, the 18th NMOS transistor, the 19th
NMOS transistor, the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor, the 9th
PMOS transistor and the tenth PMOS transistor, wherein
19th NMOS transistor, the tenth PMOS transistor constitute the first phase inverter, the output of phase inverter with
Third In-phase output signal is connected；
18th NMOS transistor, the 9th PMOS transistor constitute the second phase inverter, the output of phase inverter with
Third reversed-phase output signal is connected；
The 13rd NMOS transistor source electrode, the source electrode of the 14th NMOS transistor, the 15th NMOS are brilliant
The source electrode of body pipe, the 16th NMOS transistor source electrode be connected to the ground；
The grid of 13rd NMOS transistor, grid, the 15th PMOS of the 16th NMOS transistor
The grid of transistor, the grid of the 6th PMOS transistor, the grid of the 17th NMOS transistor and clock control are believed
Number it is connected；
The draining of 13rd NMOS transistor, the draining of the 14th NMOS transistor, the 15th NMOS
The grid of transistor, the draining of the 5th PMOS transistor, the input of second phase inverter is connected；
The draining of 16th NMOS transistor, the draining of the 15th NMOS transistor, the 14th NMOS
The grid of transistor, the draining of the 6th PMOS transistor, the input of first phase inverter is connected；
The source electrode of 5th PMOS transistor, source electrode, the 7th PMOS crystal of the 17th NMOS transistor
The draining of pipe, the grid of the 8th PMOS transistor receive the second reversed-phase output signal；
The source electrode of 6th PMOS transistor, the draining of the 17th NMOS transistor, the 7th PMOS crystal
The drain electrode of the grid of pipe, the 8th PMOS transistor receives the second In-phase output signal；
The source electrode of 7th PMOS transistor, the source electrode of the 8th PMOS transistor are connected with supply voltage.
Further, the set-reset flip-floop circuit, including：20th NMOS transistor, the 21st NMOS transistor,
20th bi-NMOS transistor, the 23rd NMOS transistor, the 11st PMOS transistor, the 12nd PMOS transistor, the tenth
Three PMOS transistors and the 14th PMOS transistor, wherein
The source electrode of 20th NMOS transistor, the source electrode of the 21st NMOS transistor are connected to the ground；
The grid of 20th NMOS transistor, the grid of the 11st PMOS transistor receive third with mutually output
Signal；
The grid of 21st NMOS transistor, the grid reception third reverse phase of the 14th PMOS transistor are defeated
Go out signal；
The draining of 20th NMOS transistor, the source electrode of the 20th bi-NMOS transistor is connected；
The draining of 21st NMOS transistor, the source electrode of the 23rd NMOS transistor is connected；
The draining of 23rd NMOS transistor, the draining of the 13rd PMOS transistor, the described 14th
The draining of PMOS transistor, the grid of the grid of the 12nd PMOS transistor, the 20th bi-NMOS transistor are connected
It connects and exports In-phase output signal；
The draining of 20th bi-NMOS transistor, the draining of the 11st PMOS transistor, the described 12nd
The draining of PMOS transistor, the grid of the grid of the 13rd PMOS transistor, the 23rd NMOS transistor are connected
It connects and exports reversed-phase output signal；
The source electrode of 11st PMOS transistor, source electrode, the 13rd PMOS of the 12nd PMOS transistor
The source electrode of transistor, the 14th PMOS transistor source electrode be connected with supply voltage.
Further, the body pole of NMOS transistor all in circuit is connected to the ground, all PMOS crystal in circuit
The body pole of pipe is connected with supply voltage.
Further, the high speed dynamic comparer passes through comparator respectively under the control of clock control signal clk
The regeneration stage of reseting stage and comparator compares to complete a data；By the tail current in the pre-amplification circuit of the second level
Pipe is controlled by clock control signal；When comparator is in regeneration stage, it is inclined to reduce electric current all the way for tail current pipe cut-off
It sets, reduces circuit static power consumption.
Further, comparator circuit undergoes reset and two stages of regeneration under the control of clock control signal；In electricity
When road is in reseting stage：
First, the 17th NMOS transistor enters conducting state, input signal of cmos latch device circuit is adjusted with this
To equilibrium state；
Second, the 5th PMOS transistor and the 6th PMOS transistor enter off state, cmos latch device circuit is resulted in
There is no DC channel between reseting stage, input terminal and ground wire；
Third, the 13rd NMOS transistor and the 16th NMOS transistor enter conducting state, to which the 5th PMOS is brilliant
Voltage at the drain electrode a of body pipe, at the drain electrode b of the 6th PMOS transistor is pulled to low level by force.
Further, it is 1.05V that the low supply voltage, which refers to voltage,.
Compared with the existing technology, the invention has the advantages that：
In the present invention, in the case of tail current and certain threshold voltage, by adjusting the breadth length ratio of pipe, bigger is obtained
Voltage margin, to solve the difficult design of traditional pre-amplification circuit at low supply voltages.
Tail current transistor in pre-amplification circuit in the second level according to the present invention, be by clock control signal to its into
Row control, can both reduce the complexity of circuit design, there is the quiescent dissipation that can reduce circuit in this way.
In the present invention, the pre-arcing transistor by clock control signal is added in cmos latch circuit and plays switch and makees
Transistor, can reduce in this way the quiescent dissipation of circuit, can also be promoted comparator circuit offset voltage performance but also
Reduce the transmission delay of circuit.
The present invention is at low supply voltages (1.05V) so that and comparator can work at still higher frequencies, and
Offset voltage, the transmission delay for improving circuit, the power consumption etc. for reducing circuit are reduced, the high speed for realizing analog-digital converter is answered
With.Fig. 7 be clock control signal be 5GHz when circuit simulation waveform, Fig. 8 be clock control signal be 10GHz when circuit
Simulation waveform；Wherein the first row is in the same direction and reversed input signal, the second row are clock control signal, third fourth line
It is respectively with phase and reversed-phase output signal.As shown in Figure 7, offset voltage of the circuit when clock signal is 5GHz is 0.2mV,
It is 63ps by its transmission delay known to calculating, circuit power consumption 0.37mW；As shown in Figure 8, circuit is 10GHz in clock signal
When offset voltage be 0.8mV, by calculating known to its transmission delay be 44ps, circuit power consumption 0.44mW.
Description of the drawings
Fig. 1 is the biasing circuit schematic diagram according to the present invention；
Fig. 2 is the first order pre-amplification circuit diagram according to the present invention；
Fig. 3 is the second level pre-amplification circuit diagram according to the present invention；
Fig. 4 is the cmos latch device circuit diagram according to the present invention；
Fig. 5 is the set-reset flip-floop circuit diagram according to the present invention；
Fig. 6 is the schematic diagram of the high speed dynamic comparer of low imbalance low-power consumption under a kind of low supply voltage of the present invention；
The simulation waveform of Fig. 7 is clock control signal when being 5GHz circuit；
The simulation waveform of Fig. 8 is clock control signal when being 10GHz circuit.
Specific implementation mode
In order to enable the advantages of purpose of the present invention, technical solution and circuit, is more clear, below in conjunction with specific
Embodiment, and refer to be in attached drawing, explanation that the present invention will be further elaborated.
It please refers to shown in Fig. 6, the high speed Dynamic comparison of low imbalance low-power consumption under a kind of low supply voltage provided by the invention
Device, including sequentially connected biasing circuit, first order pre-amplification circuit, second level pre-amplification circuit, cmos latch device circuit and
Set-reset flip-floop circuit.Wherein：
Biasing circuit receives current source signal, output first voltage offset signal vbias1, second voltage offset signal
vbias2；
First order pre-amplification circuit receives in-phase input signals for 1 vinn, rp input signal vinp, first voltage biasing
Signal vbias1, second voltage offset signal vbias2, the first In-phase output signal of output, the first reversed-phase output signal；
Second level pre-amplification circuit receives the first In-phase output signal, the first reversed-phase output signal, clock control signal
Clk, the second In-phase output signal of output, the second reversed-phase output signal；
Cmos latch device circuit receives the second In-phase output signal, the second reversed-phase output signal, clock control signal,
Export third In-phase output signal, third reversed-phase output signal；
Set-reset flip-floop circuit receives third In-phase output signal, third reversed-phase output signal, exports with mutually output letter
Number, reversed-phase output signal.
Fig. 1 is according to the biasing circuit schematic diagram of the present invention, as shown in Figure 1, biasing circuit includes：First NMOS transistor
M1, the second NMOS transistor M2, wherein
The source electrode of first NMOS transistor M1 is grounded；The grid of first NMOS transistor is connected with drain electrode and the 2nd NMOS
The source electrode of transistor is connected；The grid of second NMOS transistor is connected with drain electrode, is connected with current source signal；First NMOS crystal
The grid output first voltage offset signal vbias1 of pipe；The grid of second NMOS transistor exports second voltage offset signal
vbias2。
The grid of first NMOS transistor M1 is connected with drain electrode, constitutes current mirror form, and exports first voltage biasing
Signal vbias1；
The grid of second NMOS transistor M2 is connected with drain electrode, constitutes current mirror form, and exports second voltage biasing
Signal vbias2；The drain electrode of second NMOS transistor is connected with the current source signal of input.
Fig. 2 is according to the first order pre-amplification circuit diagram of the present invention, as shown in Fig. 2, first order pre-amplification circuit packet
It includes：It is made of the first PMOS transistor P1, the second PMOS transistor P2, third PMOS transistor P3, the 4th PMOS transistor P4
Load layer circuit；The tail current layer circuit being made of third NMOS transistor M3；By the 4th NMOS transistor M4, the 5th NMOS
The differential pair signal input layer circuit that transistor M5 is constituted；And by the 6th NMOS transistor M6, the 7th NMOS transistor M7 structures
At separation layer circuit.
The grid of third NMOS transistor receives the first biasing voltage signal vbias1；The source electrode of third NMOS transistor connects
Ground；The drain electrode of third NMOS transistor, the source electrode of the 4th NMOS transistor, the 5th NMOS transistor source electrode be connected；
The grid of 4th NMOS transistor receives in-phase input signals for 1 vinn；
The grid of 5th NMOS transistor receives rp input signal vinp；
The drain electrode of 4th NMOS transistor, the source electrode of the 6th NMOS transistor are connected；
The drain electrode of 5th NMOS transistor, the source electrode of the 7th NMOS transistor are connected；
The grid of 6th NMOS transistor, the grid of the 7th NMOS transistor are connected with second voltage offset signal vbias2
It connects；
The drain electrode of 6th NMOS transistor, the drain electrode of the first PMOS transistor, the drain electrode of third PMOS transistor are connected；
The drain electrode of 7th NMOS transistor, the drain electrode of the second PMOS transistor, the drain electrode of the 4th PMOS transistor are connected；
The drain electrode of first PMOS transistor, the grid of the first PMOS transistor, the second PMOS transistor grid be connected；
The grid of third PMOS transistor, the drain electrode of the 4th PMOS transistor, the 4th PMOS transistor grid be connected；
The source electrode of first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of third PMOS transistor, the 4th
The source electrode of PMOS transistor is connected with supply voltage；
The drain electrode of 6th NMOS transistor exports the first In-phase output signal voutn1；
The drain electrode of 7th NMOS transistor exports the first reversed-phase output signal voutp1.
Under the supply voltage of script, above-mentioned four layers of circuit design are got up relatively easily, because of higher supply voltage
Enough voltage margins can be provided to circuit, but supply voltage as used in the present invention is only 1.05V, this is not only caused
The output voltage nargin very little of first order pre-amplification circuit also brings certain difficulty to the design of circuit.
For complete design requirement at low supply voltages, in the present invention,
The bias current of this grade of circuit is determined first with tail current layer circuit；
Secondly, in the case where electric current is determining, transistor threshold voltage determines, in order to increase the output voltage of this grade of circuit
Nargin will be in differential pair signal input layer circuit and separation layer circuit under the premise of ensuring that transistor is operated in saturation region
The size of transistor is done larger as far as possible；
Corresponding adjustment finally is made to load layer circuit according to same reason；
The output voltage nargin of this grade of circuit can not only be promoted by designing according to the method described above, can also reduce differential signal
Mismatch, the offset voltage of comparator circuit can also be reduced.
Fig. 3 is according to the second level pre-amplification circuit diagram of the present invention, as shown in figure 3, second level pre-amplification circuit packet
It includes：The 8th NMOS transistor M8 controlled by clock control signal；It is made of the 9th NMOSM9, the tenth NMOS transistor M10
Input is to pipe；And the 11st NMOS transistor M11, the tenth bi-NMOS transistor M12 controlled by clock control signal is constituted
Separation layer electric power road.
Grid, the grid of the 11st NMOS transistor, the grid of the tenth bi-NMOS transistor of 8th NMOS transistor connect
Receive clock control signal clk；
The drain electrode of 8th NMOS transistor, the source electrode of the 9th NMOS transistor, the source electrode of the tenth NMOS transistor are connected；
The grid of 9th NMOS transistor receives the first reversed-phase output signal voutp1；
The grid of tenth NMOS transistor receives the first In-phase output signal voutn1；
The drain electrode of 9th NMOS transistor, the source electrode of the 11st NMOS transistor are connected；
The drain electrode of tenth NMOS transistor, the source electrode of the tenth bi-NMOS transistor are connected；
The source electrode of 8th NMOS transistor is connected to the ground；
The drain electrode of 11st NMOS transistor exports the second reversed-phase output signal voutp2；
The drain electrode of tenth bi-NMOS transistor exports the second In-phase output signal voutn2.
In the present invention, comparator circuit passes through the reset rank of comparator respectively under the control of clock control signal (CLK)
The regeneration stage (CLK is low level) of section (CLK is high level) and comparator compares to complete a data.
Therefore, the tail current pipe in the pre-amplification circuit of the second level is controlled by clock control signal.In this way when comparing
When device is in regeneration stage, tail current pipe cut-off, to reduce current offset all the way, to reach the mesh for reducing circuit static power consumption
's.
Fig. 4 is according to the cmos latch device circuit diagram of the present invention, as shown in figure 4, cmos latch device circuit is in tradition
On the basis of latch, it is added to the switching transistor controlled by clock control signal, the 5th PMOS transistor P5, the 6th
PMOS transistor P6, the 17th NMOS transistor M17, and by clock control signal control pre-arcing transistor, the 13rd
NMOS transistor M13, the 16th NMOS transistor M16, and two phase inverters are added to reduce comparator in this grade of output end
Metastable state effect.
Cmos latch device circuit, including：13rd NMOS transistor M13, the 14th NMOS transistor M14, the 15th
NMOS transistor M15, the 16th NMOS transistor M16, the 17th NMOS transistor M17, the 18th NMOS transistor M18,
19 NMOS transistor M19, the 5th PMOS transistor P5, the 6th PMOS transistor P6, the 7th PMOS transistor P7, the 8th PMOS
Transistor P8, the 9th PMOS transistor P9, the tenth PMOS transistor P10, wherein
19th NMOS transistor, the tenth PMOS transistor constitute the first phase inverter, output and the same phase of third of phase inverter
Output signal voutn3 is connected；
18th NMOS transistor, the 9th PMOS transistor constitute the second phase inverter, output and the third reverse phase of phase inverter
Output signal is connected voutp3；
13rd NMOS transistor source electrode, the source electrode of the 14th NMOS transistor, the source electrode of the 15th NMOS transistor,
The source electrode of 16 NMOS transistors is connected to the ground；
The grid of 13rd NMOS transistor, the grid of the 16th NMOS transistor, the 15th PMOS transistor grid,
The grid of 6th PMOS transistor, the grid of the 17th NMOS transistor are connected with clock control signal clk；
The drain electrode of 13rd NMOS transistor, the drain electrode of the 14th NMOS transistor, the 15th NMOS transistor grid,
The drain electrode of 5th PMOS transistor, the input of the second phase inverter are connected；
The drain electrode of 16th NMOS transistor, the drain electrode of the 15th NMOS transistor, the 14th NMOS transistor grid,
The drain electrode of 6th PMOS transistor, the input of the first phase inverter are connected；
The source electrode of 5th PMOS transistor, the source electrode of the 17th NMOS transistor, the drain electrode of the 7th PMOS transistor, the 8th
The grid of PMOS transistor receives the second reversed-phase output signal voutp2；
The drain electrode of the source electrode, the 17th NMOS transistor of 6th PMOS transistor, the grid of the 7th PMOS transistor, the 8th
The drain electrode of PMOS transistor receives the second In-phase output signal voutn2；
The source electrode of 7th PMOS transistor, the source electrode of the 8th PMOS transistor are connected with supply voltage.
In the present invention, comparator circuit undergoes reset and two stages of regeneration under the control of clock control signal.In electricity
When road is in reseting stage,
First, the 17th NMOS transistor M17 enters conducting state, with this by the input signal tune of cmos latch device circuit
Save equilibrium state；
Second, the 5th PMOS transistor P5 and the 6th PMOS transistor P6 enter off state, cmos latch device is resulted in
Circuit does not have DC channel between reseting stage, input terminal and ground wire；
Third, the 13rd NMOS transistor M13 and the 16th NMOS transistor M16 enter conducting state, thus by a, b two
The voltage at place is pulled to low level by force.
Have the above embodiment it is found that
First, the current path due to this grade of circuit of reseting stage not from supply voltage to ground wire, will reduce
The quiescent dissipation of circuit；
Second, the logic level at a, b two is equal, so in reseting stage, it is transmitted to from cmos latch device circuit next
The signal logic level of grade set-reset flip-floop circuit is equal.The storage effect for reducing cmos latch device circuit, reduces sluggishness, carries
The performance of comparator circuit offset voltage is risen；
Third, the above embodiment can reduce the recovery time of overdrive voltage, to reduce the transmission delay of signal.
Fig. 5 is according to the set-reset flip-floop circuit diagram of the present invention, as shown in figure 5, the structure of set-reset flip-floop is touched with tradition
The structure for sending out device is similar, and addition in the present invention only for enhancing signal strength and plays a protective role to integrated circuit.
Set-reset flip-floop circuit, including：20th NMOS transistor N20, the 21st NMOS transistor N21, the 22nd
NMOS transistor N22, the 23rd NMOS transistor N23, the 11st PMOS transistor P11, the 12nd PMOS transistor P12,
13rd PMOS transistor P13, the 14th PMOS transistor P14, wherein
The source electrode of 20th NMOS transistor, the source electrode of the 21st NMOS transistor are connected to the ground；
The grid of 20th NMOS transistor, the grid of the 11st PMOS transistor receive third In-phase output signal
voutn3；
The grid of 21st NMOS transistor, the grid of the 14th PMOS transistor receive third reversed-phase output signal
voutp3；
The drain electrode of 20th NMOS transistor, the source electrode of the 20th bi-NMOS transistor are connected；
The drain electrode of 21st NMOS transistor, the source electrode of the 23rd NMOS transistor are connected；
The drain electrode of 23rd NMOS transistor, the drain electrode of the 13rd PMOS transistor, the leakage of the 14th PMOS transistor
Pole, the grid of the 12nd PMOS transistor, the 20th bi-NMOS transistor grid be connected and export In-phase output signal
voutn；
The drain electrode of 20th bi-NMOS transistor, the drain electrode of the 11st PMOS transistor, the leakage of the 12nd PMOS transistor
Pole, the grid of the 13rd PMOS transistor, the 23rd NMOS transistor grid be connected and export reversed-phase output signal
voutp；
The source electrode of 11st PMOS transistor, the source electrode of the 12nd PMOS transistor, the 13rd PMOS transistor source electrode,
The source electrode of 14th PMOS transistor is connected with supply voltage.
Finally it should be noted that：Above example is only used to illustrate the technical scheme of the present invention, and is not intended to restrict the invention,
Although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art it should be understood that：Its according to
So can be with technical scheme described in the above embodiments is modified, or which part technical characteristic is equally replaced
It changes.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in the present invention
Protection domain within.
Claims (10)
1. the high speed dynamic comparer of low imbalance low-power consumption under a kind of low supply voltage, which is characterized in that including sequentially connected
Biasing circuit, first order pre-amplification circuit, second level pre-amplification circuit, cmos latch device circuit and set-reset flip-floop circuit；
The biasing circuit receives current source signal, output first voltage offset signal, second voltage offset signal；
The first order pre-amplification circuit receives in-phase input signals for 1, rp input signal, first voltage offset signal and the
Two voltage bias signals, the first In-phase output signal of output, the first reversed-phase output signal；
The second level pre-amplification circuit receives the first In-phase output signal, the first reversed-phase output signal and clock control letter
Number, the second In-phase output signal of output, the second reversed-phase output signal；
The cmos latch device circuit receives the second In-phase output signal, the second reversed-phase output signal and clock control signal,
Export third In-phase output signal, third reversed-phase output signal；
The set-reset flip-floop circuit receives third In-phase output signal, third reversed-phase output signal, exports with mutually output letter
Number, reversed-phase output signal.
2. the high speed dynamic comparer of low imbalance low-power consumption, feature under a kind of low supply voltage according to claim 1
It is, the biasing circuit, including, the first NMOS transistor and the second NMOS transistor, wherein
The source electrode of first NMOS transistor is grounded；
The grid of first NMOS transistor is connected with drain electrode, is connected with the source electrode of second NMOS transistor；
The grid of second NMOS transistor is connected with drain electrode, is connected with current source signal；
The grid of first NMOS transistor exports first voltage offset signal；
The grid of second NMOS transistor exports second voltage offset signal.
3. the high speed dynamic comparer of low imbalance low-power consumption, feature under a kind of low supply voltage according to claim 1
It is, the first order pre-amplification circuit, including：Third NMOS transistor, the 4th NMOS transistor, the 5th NMOS crystal
Pipe, the 6th NMOS transistor, the 7th NMOS transistor, the first PMOS transistor, the second PMOS transistor, third PMOS transistor
With the 4th PMOS transistor, wherein
The grid of the third NMOS transistor receives the first biasing voltage signal；
The source electrode of the third NMOS transistor is grounded；
The draining of the third NMOS transistor, the source of the source electrode of the 4th NMOS transistor, the 5th NMOS transistor
Pole is connected；
The grid of 4th NMOS transistor receives in-phase input signals for 1；
The grid of 5th NMOS transistor receives rp input signal；
The draining of 4th NMOS transistor, the source electrode of the 6th NMOS transistor is connected；
The draining of 5th NMOS transistor, the source electrode of the 7th NMOS transistor is connected；
The grid of 6th NMOS transistor, the grid of the 7th NMOS transistor are connected with second voltage offset signal；
The draining of 6th NMOS transistor, the draining of first PMOS transistor, the leakage of the third PMOS transistor
Pole is connected；
The draining of 7th NMOS transistor, the draining of second PMOS transistor, the leakage of the 4th PMOS transistor
Pole is connected；
The draining of first PMOS transistor, the grid of the grid of first PMOS transistor, second PMOS transistor
Pole is connected；
The grid of the third PMOS transistor, the draining of the 4th PMOS transistor, the grid of the 4th PMOS transistor
Pole is connected；
The source of the source electrode of first PMOS transistor, the source electrode of second PMOS transistor, the third PMOS transistor
Pole, the 4th PMOS transistor source electrode be connected with supply voltage；
The drain electrode of 6th NMOS transistor exports the first In-phase output signal；
The drain electrode of 7th NMOS transistor exports the first reversed-phase output signal.
4. the high speed dynamic comparer of low imbalance low-power consumption, feature under a kind of low supply voltage according to claim 1
It is, the second level pre-amplification circuit, including：8th NMOS transistor, the 9th NMOS transistor, the tenth NMOS crystal
Pipe, the 11st NMOS transistor and the tenth bi-NMOS transistor, wherein
The grid of 8th NMOS transistor, grid, the tenth bi-NMOS transistor of the 11st NMOS transistor
Grid receive clock control signal；
The draining of 8th NMOS transistor, the source of the source electrode of the 9th NMOS transistor, the tenth NMOS transistor
Pole is connected；
The grid of 9th NMOS transistor receives the first reversed-phase output signal；
The grid of tenth NMOS transistor receives the first In-phase output signal；
The draining of 9th NMOS transistor, the source electrode of the 11st NMOS transistor is connected；
The draining of tenth NMOS transistor, the source electrode of the tenth bi-NMOS transistor is connected；
The source electrode of 8th NMOS transistor is connected to the ground；
The drain electrode of 11st NMOS transistor exports the second reversed-phase output signal；
The drain electrode of tenth bi-NMOS transistor exports the second In-phase output signal.
5. the high speed dynamic comparer of low imbalance low-power consumption, feature under a kind of low supply voltage according to claim 1
It is, the cmos latch device circuit, including：13rd NMOS transistor, the 14th NMOS transistor, the 15th NMOS are brilliant
Body pipe, the 16th NMOS transistor, the 17th NMOS transistor, the 18th NMOS transistor, the 19th NMOS transistor, the 5th
PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor, the 9th PMOS transistor and the tenth
PMOS transistor, wherein
19th NMOS transistor, the tenth PMOS transistor constitute the first phase inverter, the output of phase inverter and third
In-phase output signal is connected；
18th NMOS transistor, the 9th PMOS transistor constitute the second phase inverter, the output of phase inverter and third
Reversed-phase output signal is connected；
The 13rd NMOS transistor source electrode, the source electrode of the 14th NMOS transistor, the 15th NMOS transistor
Source electrode, the 16th NMOS transistor source electrode be connected to the ground；
The grid of 13rd NMOS transistor, grid, the 15th PMOS crystal of the 16th NMOS transistor
The grid and clock control signal phase of the grid of pipe, the grid of the 6th PMOS transistor, the 17th NMOS transistor
Connection；
The draining of 13rd NMOS transistor, the draining of the 14th NMOS transistor, the 15th NMOS crystal
The grid of pipe, the draining of the 5th PMOS transistor, the input of second phase inverter is connected；
The draining of 16th NMOS transistor, the draining of the 15th NMOS transistor, the 14th NMOS crystal
The grid of pipe, the draining of the 6th PMOS transistor, the input of first phase inverter is connected；
The source electrode of 5th PMOS transistor, the source electrode of the 17th NMOS transistor, the 7th PMOS transistor
It drains, the grid of the 8th PMOS transistor receives the second reversed-phase output signal；
The source electrode of 6th PMOS transistor, the draining of the 17th NMOS transistor, the 7th PMOS transistor
The drain electrode of grid, the 8th PMOS transistor receives the second In-phase output signal；
The source electrode of 7th PMOS transistor, the source electrode of the 8th PMOS transistor are connected with supply voltage.
6. the high speed dynamic comparer of low imbalance low-power consumption, feature under a kind of low supply voltage according to claim 1
It is, the set-reset flip-floop circuit, including：20th NMOS transistor, the 21st NMOS transistor, the 22nd NMOS
Transistor, the 23rd NMOS transistor, the 11st PMOS transistor, the 12nd PMOS transistor, the 13rd PMOS transistor
With the 14th PMOS transistor, wherein
The source electrode of 20th NMOS transistor, the source electrode of the 21st NMOS transistor are connected to the ground；
The grid of 20th NMOS transistor, the grid of the 11st PMOS transistor receive third with mutually output letter
Number；
The grid of 21st NMOS transistor, the grid of the 14th PMOS transistor receive third anti-phase output letter
Number；
The draining of 20th NMOS transistor, the source electrode of the 20th bi-NMOS transistor is connected；
The draining of 21st NMOS transistor, the source electrode of the 23rd NMOS transistor is connected；
The draining of 23rd NMOS transistor, the draining of the 13rd PMOS transistor, the 14th PMOS are brilliant
The draining of body pipe, the grid of the grid of the 12nd PMOS transistor, the 20th bi-NMOS transistor is connected and defeated
Go out In-phase output signal；
The draining of 20th bi-NMOS transistor, the draining of the 11st PMOS transistor, the 12nd PMOS are brilliant
The draining of body pipe, the grid of the grid of the 13rd PMOS transistor, the 23rd NMOS transistor is connected and defeated
Go out reversed-phase output signal；
The source electrode of 11st PMOS transistor, source electrode, the 13rd PMOS crystal of the 12nd PMOS transistor
The source electrode of pipe, the 14th PMOS transistor source electrode be connected with supply voltage.
7. the high speed dynamic ratio of low imbalance low-power consumption under a kind of low supply voltage according to any one of claim 1 to 6
Compared with device, which is characterized in that the body pole of all NMOS transistors is connected to the ground in circuit, all PMOS transistors in circuit
Body pole be connected with supply voltage.
8. the high speed dynamic comparer of low imbalance low-power consumption, feature under a kind of low supply voltage according to claim 1
It is, the high speed dynamic comparer passes through the reseting stage and ratio of comparator respectively under the control of clock control signal clk
Compared with the regeneration stage of device, compare to complete a data；By the tail current pipe in the pre-amplification circuit of the second level by clock control
Signal is controlled；When comparator is in regeneration stage, tail current pipe cut-off reduces current offset all the way, it is quiet to reduce circuit
State power consumption.
9. the high speed dynamic comparer of low imbalance low-power consumption, feature under a kind of low supply voltage according to claim 5
It is, comparator circuit undergoes reset and two stages of regeneration under the control of clock control signal；It is in circuit and resets rank
Duan Shi：
First, the 17th NMOS transistor enters conducting state, input signal of cmos latch device circuit is adjusted to flat with this
Weighing apparatus state；
Second, the 5th PMOS transistor and the 6th PMOS transistor enter off state, cmos latch device circuit is resulted in multiple
In the position stage, there is no DC channel between input terminal and ground wire；
Third, the 13rd NMOS transistor and the 16th NMOS transistor enter conducting state, thus by the 5th PMOS transistor
Drain electrode a at, the voltage at the drain electrode b of the 6th PMOS transistor be pulled to low level by force.
10. the high speed dynamic comparer of low imbalance low-power consumption, feature under a kind of low supply voltage according to claim 6
It is, it is 1.05V that the low supply voltage, which refers to voltage,.
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| CN110601695A (en) * | 2019-09-11 | 2019-12-20 | 成都锐成芯微科技股份有限公司 | High-precision dynamic comparator |
| CN111596866A (en) * | 2020-05-29 | 2020-08-28 | 西安紫光国芯半导体有限公司 | Long line driving circuit and method, and electronic device |
| CN112332818A (en) * | 2020-11-06 | 2021-02-05 | 海光信息技术股份有限公司 | Comparator, decision feedback equalizer, receiver, interface circuit, and electronic device |
| CN112910452A (en) * | 2021-03-02 | 2021-06-04 | 河南科技大学 | Low-offset low-power-consumption high-speed dynamic comparator and application thereof |
| CN112910447A (en) * | 2021-01-18 | 2021-06-04 | 电子科技大学 | Low-power-consumption comparator circuit with rail-to-rail input swing amplitude |
| CN113114181A (en) * | 2021-05-08 | 2021-07-13 | 东南大学 | High-speed dynamic comparator with metastable state inhibition technology |
| CN114325347A (en) * | 2022-01-12 | 2022-04-12 | 电子科技大学 | Metastable state detection circuit suitable for high-speed comparator |
| CN114337709A (en) * | 2021-12-31 | 2022-04-12 | 湖南国科微电子股份有限公司 | Differential signal receiver |
| CN114826223A (en) * | 2022-04-29 | 2022-07-29 | 灿芯半导体(上海)股份有限公司 | Comparator applied to low power supply voltage ADC |
| TWI835095B (en) * | 2022-03-21 | 2024-03-11 | 瑞昱半導體股份有限公司 | Low kickback noise comparator |
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| CN110601695B (en) * | 2019-09-11 | 2023-04-21 | 成都锐成芯微科技股份有限公司 | High-precision dynamic comparator |
| CN110601695A (en) * | 2019-09-11 | 2019-12-20 | 成都锐成芯微科技股份有限公司 | High-precision dynamic comparator |
| CN111596866A (en) * | 2020-05-29 | 2020-08-28 | 西安紫光国芯半导体有限公司 | Long line driving circuit and method, and electronic device |
| CN111596866B (en) * | 2020-05-29 | 2023-04-25 | 西安紫光国芯半导体有限公司 | Long line driving circuit and method and electronic equipment |
| CN112332818A (en) * | 2020-11-06 | 2021-02-05 | 海光信息技术股份有限公司 | Comparator, decision feedback equalizer, receiver, interface circuit, and electronic device |
| CN112910447A (en) * | 2021-01-18 | 2021-06-04 | 电子科技大学 | Low-power-consumption comparator circuit with rail-to-rail input swing amplitude |
| CN112910452A (en) * | 2021-03-02 | 2021-06-04 | 河南科技大学 | Low-offset low-power-consumption high-speed dynamic comparator and application thereof |
| CN113114181A (en) * | 2021-05-08 | 2021-07-13 | 东南大学 | High-speed dynamic comparator with metastable state inhibition technology |
| CN113114181B (en) * | 2021-05-08 | 2023-08-01 | 东南大学 | High-speed dynamic comparator with metastable state suppression technology |
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| CN114337709B (en) * | 2021-12-31 | 2023-07-14 | 湖南国科微电子股份有限公司 | Differential signal receiver |
| CN114325347A (en) * | 2022-01-12 | 2022-04-12 | 电子科技大学 | Metastable state detection circuit suitable for high-speed comparator |
| TWI835095B (en) * | 2022-03-21 | 2024-03-11 | 瑞昱半導體股份有限公司 | Low kickback noise comparator |
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