CN110350876A - Preamplifier, difference preamplifier and integrated circuit - Google Patents
Preamplifier, difference preamplifier and integrated circuit Download PDFInfo
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- CN110350876A CN110350876A CN201910689989.4A CN201910689989A CN110350876A CN 110350876 A CN110350876 A CN 110350876A CN 201910689989 A CN201910689989 A CN 201910689989A CN 110350876 A CN110350876 A CN 110350876A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/219—Follower transistors are added at the input of the amplifier, e.g. source or emitter followers
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
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Abstract
A kind of preamplifier, differential preamplifier and integrated circuit, preamplifier, including input buffer cell and multi-gain amplification unit, the input buffer cell includes main source follower and auxiliary source follower, and the auxiliary source follower is used to eliminate the channel-length modulation of main source follower；The first input end of the multi-gain amplification unit is connect with the output of the input buffer cell, second input terminal of the multi-gain amplification unit connects bias voltage, exports amplified signal after the signal gain amplification that the multi-gain amplification unit exports the input buffer cell based on the bias voltage.Auxiliary source follower can eliminate the channel-length modulation of main source follower to increase substantially the linearity and gain accuracy of preamplifier.
Description
Technical field
The application belongs to CMOS integrated device technology field more particularly to a kind of preamplifier, differential preamplifier
And integrated circuit.
Background technique
The key technical indexes of preamplifier includes: gain accuracy, noise, the linearity, input and output impedance, function
Consumption, and whether have the function of level shift etc..Ideal preamplifier has accurate constant gain, noiseless, no mistake
Very, no mismatch, input impedance is infinite, and output impedance is the characteristics such as 0, this is clearly impossible.In reality, preamplifier with
Other analog circuits are the same, it then follows " the octagon rule " of Analog Circuit Design, there are serious compromises between these indexs
(tradeoff).An extremely low noise, the high linearity are designed, while guaranteeing the preposition amplification that other aspects performance does not deteriorate
Device is an extremely difficult or even often impossible thing.
Currently used preamplifier architectures:
The first is to be connected into closed loop feedback structure based on operational amplifier.This structure only has level-one, both as input
Buffering, and amplify as gain.It has the advantages that input impedance is infinitely great, and output impedance is low, and gain is accurate, and the linearity is good,
Occur extensively on various occasions.However this structure is the problem is that input signal needs to provide suitable bias voltage, fortune
Putting could work, this bias voltage is often generated by chip, be exported by pin to sensor, by sensor generated
Bias voltage is superimposed on signal.This adds increased the complexity of scheme and unreliabilities.Some sensors at all can not even
Apply bias voltage (such as the voltage and current sensor in electric energy meter, bias voltage are naturally exactly 0V).
It is for second 2 level structures of standard.It is the source follower structure based on single metal-oxide-semiconductor that it, which inputs buffer stage,.It has
The advantages that input impedance is infinitely great, and circuit is simple.However this structure gain accuracy and the linearity are very general, by PVT (technique
Deviation, power-supply fluctuation, temperature) it influences greatly, and also bottleneck is to be primarily limited to channel-length modulation in input buffer stage.
The third is 2 level structures of standard.It is the source follower structure based on single PNP pipe that it, which inputs buffer stage,.Due to defeated
Enter buffer stage using triode, no channel-length modulation, therefore its gain accuracy and the linearity are very good, does not become bottle
Neck.In addition, this major problem is that input impedance is not infinitely great (this is the characteristic of BJT pipe, and base stage will walk electric current), causes
Impedance isolation effect is bad, and secondly it needs the support of BiCMOS special process.
Summary of the invention
The application's is designed to provide a kind of preamplifier, differential preamplifier and integrated circuit, it is intended to solve
Certainly traditional single PMOS tube is limited to channel-length modulation as the preamplifier of input buffer stage, gain accuracy and
The general problem of the linearity.
The first aspect of the embodiment of the present application provides a kind of preamplifier, including input buffer cell and gain amplification
Unit, the input buffer cell include in the same direction or first current source of the differential concatenation between power supply and common potential, by the
The first main source follower that one transistor is constituted and the first auxiliary source follower being made of at least one second transistor, it is described
The grid of the first transistor and the second transistor connects the input as preamplifier altogether, first current source and described
Output of the total contact as the input buffer cell between first main source follower, the first auxiliary source follower is for disappearing
Except the channel-length modulation of the described first main source follower；
The first input end of the multi-gain amplification unit is connect with the output of the input buffer cell, the gain amplification
Second input terminal of unit connects bias voltage, and the multi-gain amplification unit is based on the bias voltage and buffers list to the input
Amplified signal is exported after the signal gain amplification of member output.
The input buffer cell further includes moving for increasing the level of output level displacement in one of the embodiments,
Position module, in which:
The level shift module is connected between first current source and the first main source follower, the level
Output of the total contact as the input buffer cell between shift module and first current source；And/or
The level shift module is connected between the described first main source follower and the first auxiliary source follower.
The first transistor and the second transistor are PMOS tube in one of the embodiments, and described first is brilliant
The source electrode of body pipe connects power supply by first current source, is connected to after at least one described second transistor series aiding connection described
Between the drain electrode and common potential of the first transistor；Or
The first transistor and the second transistor are NMOS tube, and the source electrode of the first transistor passes through described the
One current source connects common potential, and the drain electrode of the first transistor is connected to after at least one described second transistor series aiding connection
Between power supply.
The first transistor and the second transistor work in saturation region in one of the embodiments,；It is described
The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.
The threshold voltage of the first transistor is greater than the threshold value electricity of the second transistor in one of the embodiments,
Pressure relationship are as follows: | Vth1 |-| Vth0 | >=| Vod0 |+margin；
Wherein, Vth1 is the threshold voltage of the first transistor, and Vth0 is the threshold voltage of the second transistor,
Vod0 is the overdrive voltage of the second transistor, and margin is voltage margin.
In one of the embodiments, the multi-gain amplification unit include the first operational amplifier, the first divider and
Second divider, first input end of the normal phase input end of first operational amplifier as the multi-gain amplification unit, institute
The one end for stating the first divider is connect with the output end of first operational amplifier, the other end connection of first divider
With the inverting input terminal of first operational amplifier and one end of second divider, the other end of second divider
As the second input terminal of the multi-gain amplification unit, the output end of first operational amplifier amplifies single as the gain
The output end of member.
The multi-gain amplification unit includes the first operational amplifier, first resistor and the in one of the embodiments,
Two resistance, first input end of the first end of the first resistor as the multi-gain amplification unit, the of the first resistor
Two ends connect the inverting input terminal of the operational amplifier, and the normal phase input end of the operational amplifier amplifies as the gain
Second input terminal of unit, the second resistance are connected between the inverting input terminal and output end of the operational amplifier, institute
State output end of the output end of operational amplifier as the multi-gain amplification unit.
It in one of the embodiments, further include that bias voltage generates unit, it includes same that the bias voltage, which generates unit,
To or second current source of the differential concatenation between power supply and common potential, the second main source follower for being made of third transistor
And the second auxiliary source follower and buffering drive circuit being made of at least one the 4th transistor；
The grid of the third transistor and the 4th transistor connects common potential altogether, second current source and described
Total contact between second main source follower connects the input terminal of the buffering drive circuit, the output of the buffering drive circuit
The output for generating unit as the bias voltage is held, the bias voltage is exported.
The second aspect of the embodiment of the present application provides another difference preamplifier, including two input buffer cells
With a multi-gain amplification unit, each input buffer cell includes in the same direction or differential concatenation is between power supply and common potential
The first current source, the first main source follower being made of the first transistor and be made of at least one second transistor
The grid of one auxiliary source follower, the first transistor and the second transistor is connect altogether as the defeated of difference preamplifier
Enter, output of the total contact between first current source and the first main source follower as the input buffer cell,
The first auxiliary source follower is used to eliminate the channel-length modulation of the first main source follower；The multi-gain amplification unit
First input end, the second input terminal are connect with the output of two input buffer cells respectively, the multi-gain amplification unit
Two output ends of two output ends respectively as difference preamplifier.
In one of the embodiments, the multi-gain amplification unit include the first operational amplifier, second operational amplifier,
First sectional pressure element, the second sectional pressure element and third sectional pressure element, the normal phase input end conduct of first operational amplifier
The first input end of the multi-gain amplification unit, the output of one end of first sectional pressure element and first operational amplifier
The inverting input terminal of end connection, the other end of first sectional pressure element and first operational amplifier, second partial pressure
One end of element connects, the inverting input terminal of the other end of second sectional pressure element and the second operational amplifier, described
One end of third sectional pressure element connects, the normal phase input end of the second operational amplifier as the multi-gain amplification unit the
The other end of two input terminals, the third sectional pressure element is connect with the output end of the second operational amplifier, first fortune
First output end of the output end of amplifier as the multi-gain amplification unit is calculated, the output end of the second operational amplifier is made
For the second output terminal of the multi-gain amplification unit.
The multi-gain amplification unit includes the first operational amplifier, the first sectional pressure element, the in one of the embodiments,
It is put as the gain one end of two sectional pressure elements, third sectional pressure element and the 4th sectional pressure element, first sectional pressure element
The normal phase input end of the first input end of big unit, the other end of first sectional pressure element and first operational amplifier connects
It connects, second input terminal of the one end of second sectional pressure element as the multi-gain amplification unit, second sectional pressure element
The other end is connect with the inverting input terminal of first operational amplifier, and the third sectional pressure element is connected to first operation
Between the normal phase input end and reversed-phase output of amplifier, the 4th sectional pressure element is connected to first operational amplifier
Between inverting input terminal and positive output end, the reversed-phase output of first operational amplifier, positive output end respectively as
First output end of the multi-gain amplification unit, second output terminal.
The third aspect of the embodiment of the present application provides a kind of integrated circuit, including preamplifier as described above.
First order input buffer stage in above-mentioned preamplifier constitutes two source followers using different crystal pipe,
In one be used as main source follower, as auxiliary source follower, the effect of auxiliary source follower is to eliminate main source follower for another
Channel-length modulation, to increase substantially the linearity and gain accuracy of preamplifier.
Detailed description of the invention
It in order to more clearly explain the technical solutions in the embodiments of the present application, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some of the application
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Figure 1A and 1B is respectively two kinds of structural schematic diagrams of preamplifier provided by the embodiments of the present application；
Fig. 2 is the exemplary circuit schematic diagram of preamplifier embodiment one shown in figure 1A；
Fig. 3 is the exemplary circuit schematic diagram of input buffer cell in preamplifier embodiment two shown in figure 1A；
Fig. 4 is the exemplary circuit schematic diagram of preamplifier embodiment three shown in Figure 1B；
Fig. 5 is the exemplary circuit schematic diagram of input buffer cell in preamplifier example IV shown in Figure 1B；
Fig. 6 is the exemplary circuit schematic diagram of preamplifier embodiment five shown in figure 1A；
Fig. 7 is the exemplary circuit schematic diagram of input buffer cell in preamplifier embodiment six shown in figure 1A；
Fig. 8 is the source follower structure preamplifier circuit schematic diagram that traditional single PMOS tube is constituted and its input/defeated
Signal waveforms out；
Fig. 9 is the circuit diagram and its input/output signal of the middle input buffer cell of preamplifier shown in Fig. 2
Waveform diagram；
Figure 10 is the exemplary circuit schematic diagram that bias voltage generates unit in preamplifier provided by the embodiments of the present application；
Figure 11 is the exemplary circuit schematic diagram of the first differential preamplifier provided by the embodiments of the present application；
Figure 12 is the exemplary circuit schematic diagram of second of differential preamplifier provided by the embodiments of the present application.
Specific embodiment
It is with reference to the accompanying drawings and embodiments, right in order to which the objects, technical solutions and advantages of the application are more clearly understood
The application is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the application, and
It is not used in restriction the application.
Figure 1A and Figure 1B are please referred to, preamplifier provided by the embodiments of the present application includes input buffer cell 10 and gain
Amplifying unit 20, input buffer cell 10 include series aiding connection (see Figure 1A) or differential concatenation (see Figure 1B) in power Vcc and public affairs
The first current source Iss between the Vss of common-battery position, the first main source follower 100 being made of the first transistor and by least one
The grid of the first auxiliary source follower 200 that a second transistor is constituted, the first transistor and second transistor is connect altogether as preposition
The input of amplifier, the total contact between the main source follower 100 of the first current source Iss and first is as input buffer cell 10
Output, the first auxiliary source follower 200 are used to eliminate the channel-length modulation of the first main source follower 100.Gain amplification is single
The first input end of member 20 is connect with the output of input buffer cell 10, and the second input terminal of multi-gain amplification unit 20 connects biasing
Voltage vbias, the output signal that multi-gain amplification unit 20 exports input buffer cell 10 based on bias voltage vbias
Amplified signal vout is exported after vbuffer gain amplification.
This programme be the composition of single metal-oxide-semiconductor input buffer cell 10 on the basis of improve, the first main source follower 100 is still
Single transistor, the first auxiliary source follower 200 are single or multiple concatenated transistors.And the first current source Iss, the first main source
Follower 100 and the first auxiliary source follower 200 are successively connected on power Vcc and common potential Vss (as greatly forward or backwards
Ground) between, it is p-type or N-type depending on transistor.Input buffer cell 10 constitutes two sources using different crystal pipe and follows
Device, one of to be used as main source follower, as auxiliary source follower, the effect of auxiliary source follower is to eliminate main source to follow for another
The channel-length modulation of device, to increase substantially the linearity and gain accuracy of preamplifier.
Embodiment about input buffer cell 10 is as follows:
Embodiment one:
Referring to Fig. 2, the first transistor and second transistor in input buffer cell 10 are PMOS tube, then the first electricity
Stream source Iss, the first main source follower 100 and the first auxiliary source follower 200 are sequentially connected in series in power Vcc and common potential Vss
Between, the source electrode of the first transistor connects power Vcc by the first current source Iss, after at least one second transistor series aiding connection
It is connected between the drain electrode of the first transistor and common potential Vss.Specifically, the first transistor is PMOS tube PM1, the second crystal
Pipe is PMOS tube PM0, and the substrate of PMOS tube PM0 connects its source electrode, PMOS tube PM0 grounded drain；The substrate of PMOS tube PM1 connects its source
Pole, the drain electrode of PMOS tube PM1 connect the source electrode of PMOS tube PM0.First current source Iss provides bias current, it is placed in power Vcc
Between the source electrode of PMOS tube PM1, bias current direction is to flow to PMOS tube PM1 from power Vcc.Input signal vin while quilt
It is applied on the input grid of PMOS tube PM0 and PMOS tube PM1, output signal vbuffer is derived from the source electrode of PMOS tube PM1.
Embodiment two:
Referring to Fig. 3, the input buffer cell 10 of the present embodiment is to expand to multiple PMOS on the basis of example 1
The cascaded structure of source follower, wherein the first transistor PMOS tube PM1 constitutes " master " source follower, remaining second transistor
PMOS tube PM_a0~PM_an constitutes the first auxiliary source follower 200 together, PMOS tube PM1 and PMOS tube PM_a0~PM_an's
Grid connects the input as preamplifier altogether, and output signal vbuffer is derived from the PMOS tube of the output as preamplifier
The source electrode of PM1.
Embodiment three:
Referring to Fig. 4, the first transistor and second transistor of input buffer cell 10 are NMOS tube, then the first auxiliary source
Follower 200, the first main source follower 100 and the first current source Iss be sequentially connected in series power Vcc and common potential Vss it
Between, the source electrode of the first transistor meets common potential Vss by the first current source Iss, at least one second transistor series aiding connection
It is connected between the drain electrode of the first transistor and power Vcc afterwards.Specifically, the first transistor is NMOS tube NM1, second transistor
NMOS tube NM0, the substrate of NMOS tube NM0 connect its source electrode, and NMOS tube NM0 drain electrode connects power Vcc；The substrate of NMOS tube NM1 connects it
Source electrode, the drain electrode of NMOS tube NM1 connect the source electrode of NMOS tube NM0.First current source Iss provides bias current, it is placed in public
Between current potential Vss and the source electrode of NMOS tube NM1, bias current direction is to flow to NMOS tube NM1 from power Vcc to flow to common potential
Vss.Input signal vin is applied on the input grid of NMOS tube NM0 and NMOS tube NM1 simultaneously, and output signal vbuffer takes
From the source electrode of NMOS tube NM1.In the present embodiment, the cascaded structure constituted using 2 NMOS source followers, 2 with embodiment one
A PMOS tube structure perfect duality.This when, the common mode electrical level of input signal vin can be very high, such as directly takes power supply electric
Pressure.
Example IV:
Referring to Fig. 5, the input buffer cell 10 of the present embodiment is to expand to multiple NMOS on the basis of embodiment three
The cascaded structure of source follower, wherein the first transistor NMOS tube NM1 constitutes " master " source follower, remaining second transistor NMOS
Pipe NM_a0~NM_an constitutes the first auxiliary source follower 200, the grid of NMOS tube NM1 and NMOS tube NM_a0~NM_an together
The input as preamplifier is connect altogether, and output signal vbuffer is derived from the NMOS tube NM1's of the output as preamplifier
Source electrode.The cascaded structure of multiple NMOS source followers of the present embodiment and connecting for multiple PMOS source followers in embodiment two
Structure perfect duality.
Embodiment five:
Referring to Fig. 6, the input buffer cell 10 of the present embodiment be embodiment one to four any one on the basis of expand
Open up the structure for increasing a DC level shift module 300.In the present embodiment, level shift module 300 is connected to the first electricity
Total contact conduct between the main source follower 100 of stream source Iss and first, between level shift module 300 and the first current source Iss
The output of preamplifier, level shift module 300 is for increasing output level displacement.Wherein, main, the first auxiliary source follower
200 are not limited to PMOS tube or NMOS tube, and the metal-oxide-semiconductor quantity of the first auxiliary source follower 200 is also unlimited.
In example shown in Fig. 6, DC level shift module 300 is resistance R0, is serially connected in output and follows with the first main source
Between the PMOS tube PM1 of device, be able to solve depend merely on PMOS tube PM1 pipe can make output level displacement not enough, this when increases
Level shift module 300 can further increase DC level displacement, while not influence signal quality.Sometimes, in order to allow
The multi-gain amplification unit 20 of second level works at comfortable bias voltage vbias, this level shift module 300 is necessary.
In other embodiments, resistance R0 could alternatively be a circuit module, regardless of the specific implementation of this circuit module, as long as
Its function is to increase DC level displacement, while not influencing signal quality, then being exactly the protection scope for belonging to this programme.
Embodiment six:
Referring to Fig. 7, the input buffer cell 10 of the present embodiment be embodiment one to four any one on the basis of expand
Open up the structure for increasing a DC level shift module 400.In the present embodiment, it is main that level shift module 400 is connected to first
Between source follower 100 and the first auxiliary source follower 200, level shift module 400 is for increasing output level displacement.Wherein,
Main, the first auxiliary source follower 200 is not limited to PMOS tube or NMOS tube, and the metal-oxide-semiconductor quantity of the first auxiliary source follower 200 is also unlimited.
In addition, the scheme in the present embodiment can be applied in combination with the scheme of embodiment five.
In example shown in Fig. 7, DC level shift module 400 is resistance R1, is serially connected in the first main source follower 100
Between the PMOS tube PM0 of the auxiliary source follower 200 of PMOS tube PM1 and first.It is able to solve and depends merely on PMOS tube PM1 pipe and can to export
Level shift is inadequate, and DC level displacement can be further increased by increasing level shift module 400 this when, while not influenced
Signal quality.In other embodiments, resistance could alternatively be a circuit module, regardless of the specific reality of this circuit module
It is existing, as long as its function is to increase DC level displacement, while not influencing signal quality, then being exactly the protection for belonging to this programme
Range.
It is and right although Fig. 6,7 being illustrated by taking 2 grades of MOS source follower cascaded structures as an example it must be noted that as above-mentioned
Be in multistage MOS source follower cascaded structure it is applicable, in these structures be inserted into level shift module, belong to protection model
It encloses.
Please continue to refer to Fig. 2, below by in input buffer cell 10 the first transistor and second transistor be PMOS
Pipe, and the first auxiliary source follower 200 be a PMOS tube for illustrate relative theory.Specifically, the core of preamplifier
Divide and uses 2 PMOS tube PM0 and PM1 and first current source Iss.Therefore structurally, the two PMOS tube PM0
It is all to constitute source follower, but its input is connected in parallel with PM1, output " series connection " is together.PMOS tube PM1 constitutes main source
Follower, PMOS tube PM0 constitute auxiliary source follower；The presence of PMOS tube PM0 has carried out linearization process to PMOS tube PM1, makes
The linearity for obtaining PMOS tube PM1 greatly improves, and output signal vbuffer is exactly generated by PMOS tube PM1.Just because of this
Cleverly connection relationship just greatly improves the linearity, and gain accuracy greatly improves, and other aspects performance is (as exported
Impedance, the consumption of noise, power consumption, voltage margin) it is suitable with common single PMOS tube source follower.This leads in Analog Circuit Design
It is very rare phenomenon in domain, because in Analog Circuit Design field, is filled with various compromises (tradeoff), usual one
Kind circuit framework when excellent performance, is often brought using sacrificing other aspects performance as cost in terms of certain than another kind.
In Fig. 2 structure, PMOS tube PM0 and PMOS tube PM1 need fine design and choose size, to guarantee to allow 2
MOS works in saturation region, and this is that effective basic demand is answered in the performance of this structure.PMOS tube PM0 work is allowed to be saturated
Area's very comfortable, difficult point be that PMOS tube PM1 is allowed to work in saturation region, it must satisfy:
|Vds1|≥(|Vgs1|-|Vth1|)+margin
Wherein, Vds1, Vgs1, Vth1, margin are respectively drain-source voltage, gate source voltage, the threshold value electricity of PMOS tube PM1
In general pressure, voltage margin, margin take 100~200mV or so.Assuming that the common mode electrical level of input signal vin is 0, above formula
Further it is written as:
vbuffer-vt≥vbuffer-|Vth1|+margin
Further are as follows:
|Vth1|≥Vt+margin
Due to vt=| Vgs0 |=| Vth0 |+Vod0, vt are that the drain electrode of PMOS tube PM1 and the source electrode of PMOS tube PM0 connect altogether
Point voltage, Vgs0, Vth0, Vod0 are gate source voltage, threshold voltage, the overdrive voltage of PMOS tube PM0,Therefore, above formula is further written as:
|Vth1|-|Vth0|≥Vod0+margin≈Vod0+100mV
This means that the threshold voltage of PMOS tube PM1 must be Vod0+margin bigger than the threshold voltage of PMOS tube PM0, i.e.,
At least in 100mV or more.In order to realize this target, at least 2 kinds of feasible solutions:
The first: technique can generally provide the option of a variety of threshold mos pipes.Can choose PM1 is high threshold pipe metal-oxide-semiconductor,
PM0 is Low threshold pipe metal-oxide-semiconductor, this can easily realize target.
Second: passing through fine and cleverly size design realization.Allow PMOS tube PM0 W/L (W be conducting channel width
Degree, L are the length of conducting channel) it is sufficiently large, make its work in subthreshold region, at this moment Vod0 can be very small (such as 50mV).
Allow the L of PMOS tube PM0 that the minimum length under current process is taken (such as 0.35um CMOS technology, to take L=simultaneously
0.35um), and the minimum usually band of L has also carried out lesser threshold voltage.In addition, making the W/L of PMOS tube PM1 as small as possible, while L
It takes (such as 0.35um CMOS technology, taking L=4um) as big as possible under current process, the Vod1 foot of such PMOS tube PM1
Enough big, the channel-length modulation of itself is sufficiently small, and the linearity is also as well as possible.And the biggish L of PMOS tube PM1 generally also band
Biggish threshold voltage is carried out.Like this, by allowing | Vth1 | it is as big as possible, allow | Vth0 | it is as small as possible, allow Vod0 as far as possible
It is small, so that above formula meets, this programme structure bring effect is then played, has further made the linearity more preferable.
Next further analysis, why the proposed structure of this programme can increase substantially the linearity and gain is accurate
Degree, needs to investigate this problem by comparative analysis.
Fig. 8 is the input buffer cell 10 for the source follower structure that traditional single PMOS tube is constituted, and substrate connects source electrode.Its is defeated
Enter the gain to output are as follows:
Wherein gm is the mutual conductance of PMOS tube PM1, and gds is the intrinsic admittance of output of PMOS tube PM1.Gm/gds is known as metal-oxide-semiconductor
Intrinsic gain, this usual value is 100 or so, that is to say, that gds ≈ gm/100 usually can be ignored compared to gm, because
This Av is approximately equal to 1.If for the occasion of high-precision and high linearity, the influence of gds cannot be had ignored.Gds influences characterization
Be channel-length modulation, in this structure, gds determines the precision and the linearity of gain completely.Notice gds's
Definition:
Therefore gds is the function of vds (drain-source voltage of metal-oxide-semiconductor).For the source follower of Fig. 8, due to vds=
Vbuffer-0 ≈ vin, so while the influence of gds, gain A v is actually still the minorant of input signal:
Here it is non-linear, then harmonic distortion is just produced.Design and simulation result are shown on typical CMOS processes,
The component of 10,2 subharmonic of input buffer cell of the source follower structure that this traditional single PMOS tube is constituted and 3 subharmonic is very
For hardly possible lower than < -80dBc, this means that the measuring system based on this single PMOS tube source follower structure input buffer cell 10,
Number of significant digit (precision index is defined as ENOB=(SNDR-1.76)/6.02) is at most in 13bits or so, and this is for high-precision
It spends for application, is far from being enough.
By the analysis to Fig. 8, it is understood that bottleneck is gds.It is proposed that patent formula exactly almost
Eliminate the influence of gds.
As shown in figure 9, input signal vin by 2 source followers, generates vbuffer and vt respectively.We are PMOS tube
PM1 is known as the first main source follower 100, and PMOS tube PM0 is known as the first auxiliary source follower 200.Vbuffer and vt are nearly all accurate
Equal to input signal vin, the magnitude of error is exactly harmonic component (in a ten thousandth of -80dBc or so, that is, signal itself
Left and right).
It is further noted that PMOS tube PM1,
Vds=vbuffer-vt ≈ vin+o (vin)-[vin+o (vin)]=o (vin) ≈ 0
Mathematically mark is employed herein, small o indicates " being much smaller than ", such as o (vin) indicates the amount for being much smaller than vin.Cause
This, the source electrode and drain electrode of PMOS tube PM1 is to synchronize to follow input wobble signal, but for its difference, almost 0 (is fluctuated
It is exactly a ten thousandth or so in input signal), therefore the variation of imperceptible vds.Since the variation of imperceptible vds, that
The gds of PMOS tube PM1 pipe is also just no better than 0.Therefore, for the circuit structure of the application:
Nonlinear component substantially reduces, therefore significantly reduces harmonic distortion.It is designed in same CMOS technology and imitative
Very the results show that using 10,2 subharmonic of input buffer cell for the new source follower structure of the application proposed and 3 times
The component of harmonic wave can accomplish < -120dBc, it is meant that the measuring system of the input buffer cell 10 based on this source follower,
Number of significant digit highest can achieve the level close to 20bits, for high-precision applications occasion, enough (usual 16bits or so
It is relatively common).
On the other hand the index to be considered is gain accuracy, this is equally to Guan Chong for high precision measuring system
It wants.In practice, every level-one in signal processing link (buffering isolation, amplification, filtering, analog-to-digital conversion ...) can all introduce increasing
Benefit, and the gain of every level-one can all be influenced by PVT (process deviation, power-supply fluctuation, temperature), it is often extremely complex or even difficult
Accurately to portray.In the influence of PVT:
The influence of usual power-supply fluctuation V can be by being designed to deal with, such as is placed in LDO (Low Dropout
Regulator, low pressure difference linear voltage regulator) under allow V to keep constant.
The influence of usual process deviation P is solved by the calibration link before chip/complete machine factory.So-called calibration is exactly
Yield value Av0 before chip/complete machine factory is write down, is stored in the nonvolatile memory of chip, referred to as demarcates.Normally make
Used time calibrates actual gain Av with Av0.In this way, the process variations between piece and piece are eliminated；
And the influence of temperature T, it must be become pair by outstanding design level and cleverly circuit structure by the gain of circuit
Temperature-insensitive.
For the source follower structure input buffer cell 10 that traditional single PMOS tube shown in Fig. 8 is constituted, increase
Benefit are as follows:
Wherein
Gds (PVT) and gm (PVT) be all with high temperature change amount, DEG C range from -40 DEG C to+85, gds (PVT)/
Gm (PVT) variable quantity is often as high as 2 times or more.As before, it is about 0.99 that the representative value of gds/gm, which is about 1%, Av representative value,；
But if Av variation with temperature is up to 1% or more, and this results in very big measurements in view of after the varying with temperature of gds/gm
Error, so that high precision measuring system becomes no longer accurate.Since gds (PVT)/gm (PVT) not only has relationship with T, also have with P
Relationship, it means that for each chips, gds (PVT)/gm (PVT) temperature curve may be all different, so that considering to do
The idea of temperature-compensating becomes not implementable (needing to do temperature-compensating to each, cost is extremely expensive).
But for the patent formula that the application proposes, gain are as follows:
Wherein
Assuming that the value of x itself is about 1%, variation is also about 1% within the scope of total temperature.As before, o (x) is one
The amount of 40dB also smaller than x or so (about 100 times), therefore the value of o (x) itself is about 0.01%, and become within the scope of total temperature
Change is also about 0.01% magnitude, is converted to about 8ppm/ DEG C of temperature coefficient, in terms of the document that can be found at present, this
Belong to most top level, meets the application of most high precision measuring systems.
The source follower that the application constitutes 2 metal-oxide-semiconductors, input terminal are connected in parallel, and output end " series connection " is together.Its
In a metal-oxide-semiconductor as the first main source follower 100, another or multiple metal-oxide-semiconductors are as the first auxiliary source follower 200, output
It is derived from the first main source follower 100.The effect of first auxiliary source follower 200 is to eliminate the ditch road length of the first main source follower 100
Mudulation effect is spent, to increase substantially the linearity and gain accuracy of input buffer cell 10.
In order to allow the metal-oxide-semiconductor of main, the first auxiliary source follower 200 all to work in saturation region, the design method of use: one is
Using the design method of multi-threshold pipe；The second is using the pipe sizing choosing method more rich in skill.Both methods exists
Front has a detailed description.
The input buffer cell 10 of the application and integrated circuit linearity degree are fabulous, and gain is extremely accurate；Input signal is not required to
Additional bias voltage vbias (sensor can be used as common-mode signal with directly taking) is provided；Circuit is extremely simple, and and CMOS
Technique is completely compatible, is not necessarily to particular device；Impedance isolation (input is high impedance, is exported as Low ESR)；Other aspects performance is (such as
The consumption of noise, power consumption, voltage margin) it is suitable with common single metal-oxide-semiconductor source follower structure.This right and wrong in circuit design field
Often rare phenomenon.In circuit design field, various compromises (tradeoff) are filled with, a kind of circuit framework ratio is another to exist
Certain aspect excellent performance, is often brought using sacrificing other aspects performance as cost.
Embodiment about multi-gain amplification unit 20 is as follows:
The first embodiment:
Please refer to Fig. 2 and Fig. 4, multi-gain amplification unit 20 includes the first operational amplifier A0, the first divider R11 and the
Two divider R12, first input end of the normal phase input end of the first operational amplifier A0 as multi-gain amplification unit 20, first point
One end of depressor R11 is connect with the output end of the first operational amplifier A0, other end connection and the first fortune of the first divider R11
The inverting input terminal of amplifier A0 and one end of the second divider R12 are calculated, the other end of the second divider R12 amplifies as gain
Second input terminal of unit 20, output end of the output end of the first operational amplifier A0 as multi-gain amplification unit 20.
In the present embodiment, the gain of entire preamplifier are as follows:
Pass through the ratio for changing divider R11 and R12, it can realize desired gain, divider R11 and R12 can be with
The circuit constituted at least one of resistance, capacitor, inductance, semiconductor transistor.
In the present embodiment, second level gain stage is due to the form using amplifier closed loop feedback, the linearity and increasing
Strengthening the essence degree is preferable.As long as the open-loop gain of amplifier A1 is done sufficiently high, then the linearity of gain stage and gain accuracy are ok
That does is very good.
Second of embodiment:
Referring to Fig. 6, multi-gain amplification unit 20 includes operational amplifier A1, first resistor R13 and second resistance R14,
The R13 second end of first input end of the first end of first resistor R13 as multi-gain amplification unit 20, first resistor connects operation
The inverting input terminal of amplifier A1, second input terminal of the normal phase input end of operational amplifier A1 as multi-gain amplification unit 20,
Second resistance R14 is connected between the inverting input terminal and output end of operational amplifier A1, and the output end of operational amplifier A1 is made
For the output end of multi-gain amplification unit 20.
In the present embodiment, gain stage is changed to reverse phase proportional amplifier, the gain formula of this structure are as follows:
In addition, the bias voltage vbias that present invention also provides a kind of for generating above-mentioned bias voltage vbias generates list
Member 30.It can be used for providing bias voltage vbias for the preamplifier of foregoing individual embodiments.
Referring to Fig. 10, bias voltage vbias is generated, unit 30 includes in the same direction or differential concatenation is in power supply and common potential
Between the second current source Iss1, the second main source follower 301 for being made of third transistor PM1s and by least one
The the second auxiliary source follower 302 and buffering drive circuit A2 that four transistor PM0s are constituted；Third transistor PM1s and the 4th is brilliant
The grid of body pipe PM0s meets common potential Vss altogether, and the total contact between the main source follower 301 of the second current source Iss1 and second connects
The input terminal of buffering drive circuit A2 is connect, the output end of buffering drive circuit A2 generates unit 30 as bias voltage vbias
Output exports bias voltage vbias.It can thus be seen that bias voltage vbias generate unit 30 in the second current source Iss1,
The subcircuits structure that second main source follower 301, the second auxiliary source follower 302 are constituted is the electricity with input buffer cell 10
Line structure is identical, then the specific embodiment that bias voltage vbias generates unit 30 can be directly used such as above-mentioned input
The identical various embodiments of buffer cell 10, and the device size of two units then depends on actual demand.Moreover, same
In a preamplifier circuit, bias voltage vbias, which generates unit 30 and input buffer cell 10, can use same circuit
Structure is implemented, and can also be implemented using different circuit structures.
In the present embodiment, the branch that is made of the second current source Iss1, third transistor PM1s, the 4th transistor PM0s
1 generates initial bias vbias_src, this voltage is that do not have driving capability without buffering.Again by initial bias
Buffering drive circuit A2 of the voltage vbias_src by a unit gain generates bias voltage vbias.By the second current source
The branch 1 that Iss1, third transistor PM1s, the 4th transistor PM0s are constituted, type of attachment with by the first current source Iss,
The branch 2 that the first transistor PM1, figure transistor PM0 are constituted is just the same, but its correspondingly-sized is only merely the 1/N of branch 2
(N is positive integer, such as N=4).It should be noted that the present embodiment in third transistor PM1s, the 4th transistor PM0s it is defeated
Enter and terminate 0V, that is, (if do not done specified otherwise, assumes input signal vin herein as the common mode electrical level of input signal vin
Common mode electrical level be 0V).Therefore in the case where not considering mismatch, the level value of initial bias vbias_src and output
The common mode electrical level of signal vbuffer is just the same, so that second level gain stage only amplifies the exchange point of output signal vbuffer
Amount, the DC component without amplifying output signal vbuffer, this working condition right and wrong for the amplifier A0 of second level gain stage
It is often advantageous.In circuit design field, this design tactics are known as " self-replication " technology.
Figure 11 and Figure 12 are please referred to, disclosed herein as well is a kind of difference preamplifier, including two input bufferings are single
Member 10 and a multi-gain amplification unit 20, each input buffer cell 10 includes in the same direction or differential concatenation is in power supply and common potential
Between the first current source Iss, the first main source follower 100 for being made of the first transistor PM1 and by least one second
The grid of the first auxiliary source follower 200 that transistor PM1 is constituted, the first transistor PM1 and second transistor PM1 are connect altogether as preceding
The total contact between the main source follower 100 of input vip/vin, the first current source Iss and first of difference amplifier is set as defeated
Enter the output of buffer cell 10, the first auxiliary source follower 200 is used to eliminate the channel length modulation effect of the first main source follower 100
It answers；The first input end vbf_p of multi-gain amplification unit 20, the second input terminal vbf_n respectively with two input buffer cells 10
Output connects, the two output end vop/von of two output ends of multi-gain amplification unit 20 respectively as difference preamplifier.
The specific embodiment of two input buffer cells 10 is referred to above-described embodiment one to six and its relative theory
Illustrate, which is not described herein again.
Figure 11 is please referred to, multi-gain amplification unit 20 includes the first operational amplifier A3, second in one of the embodiments
Operational amplifier A4, the first sectional pressure element R21, the second sectional pressure element R22 and third sectional pressure element R23, the first operation amplifier
First input end vbf_p of the normal phase input end of device A3 as multi-gain amplification unit 20, one end of the first sectional pressure element R21 and the
The output end of one operational amplifier A3 connects, and the other end of the first sectional pressure element R21 and the reverse phase of the first operational amplifier A3 are defeated
Enter one end connection at end, the second sectional pressure element R22, the other end of the second sectional pressure element R22 is anti-with second operational amplifier A4's
One end connection of phase input terminal, third sectional pressure element R23, the normal phase input end of second operational amplifier A4 amplify single as gain
Second input terminal vbf_n of member 20, the other end of third sectional pressure element R23 are connect with the output end of second operational amplifier A4,
First output end vop of the output end of first operational amplifier A3 as multi-gain amplification unit 20, second operational amplifier A4's
Second output terminal von of the output end as multi-gain amplification unit 20.
In the present embodiment, difference preamplifier is the differential configuration constituted on the basis of Fig. 2 related embodiment, difference
Circuit has symmetry, innately has rejection ability to even-order harmonic, therefore have more extensive use, in practical application absolutely
Most of amplifier circuit is that occur in the form of difference (or pseudo-differential).Multi-gain amplification unit 20 in Figure 11 is not aforementioned
The simple copy of multi-gain amplification unit 20 the first embodiment (i.e. Fig. 2,4 shown in structure) doubles, but is merged, by two
A divider R12 merges into a sectional pressure element R22, and bias voltage is omitted.Exactly because this, the gain of this structure is public
Also the first embodiment is different with multi-gain amplification unit 20 for formula, are as follows:
Figure 12 is please referred to, multi-gain amplification unit 20 includes operational amplifier A5, the first partial pressure in one of the embodiments
Element R31, the second sectional pressure element R32, third sectional pressure element R33 and the 4th sectional pressure element R34, first sectional pressure element
First input end vbf_p of the one end of R31 as multi-gain amplification unit 20, the other end of the first sectional pressure element R31 are put with operation
The normal phase input end connection of big device A5, second input terminal of the one end of the second sectional pressure element R32 as multi-gain amplification unit 20
The other end of vbf_n, the second sectional pressure element R32 are connect with the inverting input terminal of operational amplifier A5, and third sectional pressure element R33 connects
It connects between the normal phase input end and reversed-phase output of operational amplifier A5, the 4th sectional pressure element R34 is connected to operational amplifier
Between the inverting input terminal and positive output end of A5, the reversed-phase output of operational amplifier A5, positive output end are respectively as increasing
The first output end von, the second output terminal vop of beneficial amplifying unit 20.
In the present embodiment, difference preamplifier is in the input buffer cell 10 and Fig. 6 embodiment in Fig. 2 embodiment
Multi-gain amplification unit 20 on the basis of the differential configuration that constitutes, wherein multi-gain amplification unit 20 is that the reverse phase ratio of differential configuration is put
Big device, this is also not 20 structure of multi-gain amplification unit in the input buffer cell 10 and Fig. 6 embodiment in Fig. 2 embodiment
Simple copy doubles, but is constituted based on the operational amplifier A5 of single fully differential input and output, and bias voltage is omitted.
It must be noted that although two input buffer cells 10 of above-mentioned difference preamplifier are connected with 2 grades of PMOS
Illustrate for structure, in practice for all structures of including but not limited to embodiment one to six, may be constructed difference channel,
These belong to the protection scope of the application.In addition, the sectional pressure element can be for resistance, capacitor, inductance, transistor etc. extremely
A kind of circuit of few composition.
Present invention also provides a kind of integrated circuits including above-mentioned preamplifier 10.The application uses above-mentioned
Input buffer structure, is greatly improved the linearity and gain accuracy.Design and simulation result are aobvious on typical CMOS processes
Show, the source follower structure input buffer that traditional single PMOS tube is constituted, the component of 2 subharmonic and 3 subharmonic is difficult to be lower than
The variation of < -80dBc, gain with temperature are up to ± 1%, this is far from being enough for high-precision applications occasion.And it adopts
With this input buffer structure in the application, the component of 2 subharmonic and 3 subharmonic can accomplish < -120dBc, gain with
The variation of temperature is enough for most High Definition Systems down to ± 0.01%.Most of all, this is in pure CMOS work
It is realized in skill, is not necessarily to any particular device, the support without expensive BiCMOS technique.
The foregoing is merely the preferred embodiments of the application, not to limit the application, all essences in the application
Made any modifications, equivalent replacements, and improvements etc., should be included within the scope of protection of this application within mind and principle.
Claims (12)
1. a kind of preamplifier, including input buffer cell and multi-gain amplification unit, it is characterised in that:
The input buffer cell include in the same direction or first current source of the differential concatenation between power supply and common potential, by first
The first main source follower that transistor is constituted and the first auxiliary source follower for being made of at least one second transistor, described the
The grid of one transistor and the second transistor connects the input as preamplifier, first current source and described altogether
Output of the total contact as the input buffer cell between one main source follower, the first auxiliary source follower is for eliminating
The channel-length modulation of the first main source follower；
The first input end of the multi-gain amplification unit is connect with the output of the input buffer cell, the multi-gain amplification unit
The second input terminal connect bias voltage, the multi-gain amplification unit be based on the bias voltage it is defeated to the input buffer cell
Amplified signal is exported after signal gain amplification out.
2. preamplifier as described in claim 1, which is characterized in that the input buffer cell further includes defeated for increasing
The level shift module of level shift out, in which:
The level shift module is connected between first current source and the first main source follower, the level shift
Output of the total contact as the input buffer cell between module and first current source；And/or
The level shift module is connected between the described first main source follower and the first auxiliary source follower.
3. preamplifier as described in claim 1, which is characterized in that the first transistor and the second transistor are
The source electrode of PMOS tube, the first transistor connects power supply by first current source, at least one described second transistor is same
It is connected to after to series connection between the drain electrode and common potential of the first transistor；Or
The first transistor and the second transistor are NMOS tube, and the source electrode of the first transistor passes through first electricity
Stream source connects common potential, and drain electrode and the electricity of the first transistor are connected to after at least one described second transistor series aiding connection
Between source.
4. preamplifier as described in any one of claims 1 to 3, which is characterized in that the first transistor and described
Two-transistor works in saturation region；The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.
5. preamplifier as claimed in claim 4, which is characterized in that the threshold voltage of the first transistor is greater than described
The threshold voltage relationship of second transistor are as follows: | Vth1 |-| Vth0 | >=| Vod0 |+margin；
Wherein, Vth1 is the threshold voltage of the first transistor, and Vth0 is the threshold voltage of the second transistor, and Vod0 is
The overdrive voltage of the second transistor, margin are voltage margin.
6. preamplifier as described in claim 1, which is characterized in that the multi-gain amplification unit includes the first operation amplifier
Device, the first divider and the second divider, the normal phase input end of first operational amplifier amplify single as the gain
The first input end of member, one end of first divider are connect with the output end of first operational amplifier, and described first
The other end of divider is connected to the inverting input terminal of first operational amplifier and one end of second divider, described
Second input terminal of the other end of second divider as the multi-gain amplification unit, the output end of first operational amplifier
Output end as the multi-gain amplification unit.
7. preamplifier as described in claim 1, which is characterized in that the multi-gain amplification unit includes the first operation amplifier
Device, first resistor and second resistance, first input end of the first end of the first resistor as the multi-gain amplification unit,
The second end of the first resistor connects the inverting input terminal of the operational amplifier, the normal phase input end of the operational amplifier
As the second input terminal of the multi-gain amplification unit, the second resistance is connected to the inverting input terminal of the operational amplifier
Between output end, output end of the output end of the operational amplifier as the multi-gain amplification unit.
8. the preamplifier as described in claim 1,6 or 7, which is characterized in that it further include that bias voltage generates unit, it is described
Bias voltage generate unit include in the same direction or second current source of the differential concatenation between power supply and common potential, by third crystal
The second main source follower that pipe is constituted and the second auxiliary source follower being made of at least one the 4th transistor, and buffering are driven
Dynamic circuit；
The grid of the third transistor and the 4th transistor connects common potential, second current source and described second altogether
Total contact between main source follower connects the input terminal of the buffering drive circuit, and the output end of the buffering drive circuit is made
The output that unit is generated for the bias voltage, exports the bias voltage.
9. a kind of difference preamplifier, which is characterized in that including two input buffer cells and a multi-gain amplification unit, often
A input buffer cell include in the same direction or first current source of the differential concatenation between power supply and common potential, by the first transistor
The the first main source follower constituted and the first auxiliary source follower being made of at least one second transistor, the first crystal
The grid of pipe and the second transistor connects the input as difference preamplifier, first current source and described first altogether
Output of the total contact as the input buffer cell between main source follower, the first auxiliary source follower is for eliminating the
The channel-length modulation of one main source follower；The first input end of the multi-gain amplification unit, the second input terminal respectively with
The output connection of two input buffer cells, two output ends of the multi-gain amplification unit are put respectively as preposition difference
Two output ends of big device.
10. difference preamplifier as claimed in claim 9, which is characterized in that the multi-gain amplification unit includes the first fortune
Calculate amplifier, second operational amplifier, the first sectional pressure element, the second sectional pressure element and third sectional pressure element, first fortune
Calculate first input end of the normal phase input end as the multi-gain amplification unit of amplifier, one end of first sectional pressure element with
The output end of first operational amplifier connects, the other end of first sectional pressure element and first operational amplifier
One end connection of inverting input terminal, second sectional pressure element, the other end of second sectional pressure element and second operation
One end connection of the inverting input terminal of amplifier, the third sectional pressure element, the normal phase input end of the second operational amplifier
As the second input terminal of the multi-gain amplification unit, the other end of the third sectional pressure element and the second operational amplifier
Output end connection, first output end of the output end of first operational amplifier as the multi-gain amplification unit be described
Second output terminal of the output end of second operational amplifier as the multi-gain amplification unit.
11. difference preamplifier as claimed in claim 9, which is characterized in that the multi-gain amplification unit includes the first fortune
Calculate amplifier, the first sectional pressure element, the second sectional pressure element, third sectional pressure element and the 4th sectional pressure element, first partial pressure
First input end of the one end of element as the multi-gain amplification unit, the other end of first sectional pressure element and described first
The normal phase input end of operational amplifier connects, and one end of second sectional pressure element is second defeated as the multi-gain amplification unit
Enter end, the other end of second sectional pressure element is connect with the inverting input terminal of first operational amplifier, the third point
Pressure element is connected between the normal phase input end and reversed-phase output of first operational amplifier, and the 4th sectional pressure element connects
It connects between the inverting input terminal and positive output end of first operational amplifier, the reverse phase of first operational amplifier is defeated
Outlet, positive output end are respectively as the first output end of the multi-gain amplification unit, second output terminal.
12. a kind of integrated circuit, which is characterized in that including preamplifier as claimed in any one of claims 1 to 8.
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| CN117389371A (en) * | 2023-12-12 | 2024-01-12 | 江苏帝奥微电子股份有限公司 | Dual-loop frequency compensation circuit suitable for LDO and compensation method thereof |
| CN117389371B (en) * | 2023-12-12 | 2024-02-23 | 江苏帝奥微电子股份有限公司 | Dual-loop frequency compensation circuit suitable for LDO and compensation method thereof |
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