CN210431360U

CN210431360U - Chopping preamplifier and integrated circuit

Info

Publication number: CN210431360U
Application number: CN201921221681.9U
Authority: CN
Inventors: 苗书立; 许建超; 夏书香
Original assignee: SHENZHEN RENERGY TECHNOLOGY CO LTD
Current assignee: SHENZHEN RENERGY TECHNOLOGY CO LTD
Priority date: 2019-07-29
Filing date: 2019-07-29
Publication date: 2020-04-28
Anticipated expiration: 2029-07-29

Abstract

The utility model provides a chopper preamplifier and integrated circuit, includes a pair of chopper switch to and the input buffer stage, gain amplifier stage, the output filter stage that connect gradually, one of them chopper switch sets up before the input buffer stage, and another sets up behind the input buffer stage, and gain amplifier circuit inside adopts chopper operational amplifier moreover to "disperse" the chopping, make the chopping only handle little difference signal, avoid making a round trip to exchange big difference signal, thereby avoid big state change. This greatly simplifies the recovery difficulty and recovery time after the signal is disturbed, with very little loss to the integrity of the signal.

Description

Chopping preamplifier and integrated circuit

Technical Field

The application belongs to the technical field of CMOS (complementary metal oxide semiconductor) integrated devices, and particularly relates to a chopping preamplifier and an integrated circuit.

Background

The chopping technique is briefly described as follows: a pair of chopping switches is used, and a differential circuit is placed between the pair of chopping switches. The chopping switches realize the continuous switching of the same phase and the opposite phase of the differential signals. Functionally, the input side switch performs a modulation function (modulator) on the input signal, and the output side switch performs a demodulation function (de-modulator) on the output signal. The final effect is: there is no effect on the signal spectrum (two spectrum shifts occur back and forth, but finally return to the origin), but for the noise of the differential circuit between the two chopping switches, only one spectrum shift occurs because of only one demodulation process, and the low-frequency 1/f noise and offset are shifted to the high frequency and finally filtered by the subsequent low-pass filter. Although the chopping technology can eliminate the detuning and the 1/f noise, because the chopping clock is introduced, the periodical overturning and disturbance to the precise analog circuit exist, and therefore, the non-ideal factors of clock feed-through, charge injection, signal disturbance and signal recovery and the like are inevitably introduced. These problems, if handled poorly, can severely degrade linearity and gain accuracy.

The preamplifier structure with the chopping function commonly used at present comprises: the chopper switches are generally arranged at two ends of the gain amplification stage, or the input side switch is arranged at the front end of the input buffer stage, and the output side switch is arranged at the rear end of the gain amplification stage. The chopping switch of the output side switch has a large signal, and the chopping process causes great state change, so that the integrity problem of the signal is caused, and the linearity and the gain precision are influenced. In addition, due to the problems of input impedance, process requirements, gain accuracy and linearity of the current input buffer stage structure, the performance of the whole preamplifier is also affected

Disclosure of Invention

The application aims to provide a chopping preamplifier and an integrated circuit, and aims to solve the problems that the chopping preamplifier commonly used at present has a large signal at a chopping switch of an output side switch, and the signal integrity, the linearity and the gain precision can be influenced due to the large state change of the signal caused by the chopping process.

A first aspect of an embodiment of the present application provides a chopping preamplifier, including:

the two input ends of the first chopping switch are respectively connected with two input signals, and the first chopping switch is used for modulating the two input signals and then outputting the modulated two input signals;

two input ends of the input buffer circuit are connected with two output ends of the first chopping switch, and the input buffer circuit adopts a source follower structure and provides impedance isolation for the input signal and then outputs the input signal;

two input ends of the second chopping switch are respectively connected with two output ends of the input buffer circuit, and the second chopping switch is used for outputting an output signal of the input buffer circuit after being modulated;

two input ends of the gain amplifying circuit are connected with two output ends of the second chopping switch, and the gain amplifying circuit adopts a chopping operational amplifier capable of eliminating detuning and noise and is used for amplifying the gain of the output signal after being modulated, and outputting an amplified signal after the detuning and the noise are eliminated;

and two input ends of the output filter circuit are connected with the output end of the gain amplification circuit, and the output filter circuit is used for filtering and outputting the amplified signal.

In one embodiment, the input buffer circuit comprises two input buffer units, each of the input buffer units comprises a first current source connected in series in the same direction or in reverse direction between a power supply and a common potential, a first main source follower formed by a first transistor and a first auxiliary source follower formed by at least one second transistor, the gates of the first transistor and the second transistor are connected in common to serve as the input end of the input buffer circuit, the common point between the first current source and the first main source follower serves as the output end of the input buffer circuit, and the first auxiliary source follower is used for eliminating the channel length modulation effect of the first main source follower.

In one embodiment, the input buffer unit further comprises a level shift module for increasing an output level shift, wherein:

the level shift module is connected between the first current source and the first main source follower, and a common junction point between the level shift module and the first current source is used as the output of the input buffer unit.

In one embodiment, the level shifting module is connected between the first primary source follower and the first secondary source follower.

In one embodiment, the first transistor and the second transistor are PMOS tubes, the source electrode of the first transistor is connected with a power supply through the first current source, and at least one second transistor is connected between the drain electrode of the first transistor and a common potential after being connected in series in the same direction; or

The first transistor and the second transistor are NMOS transistors, the source electrode of the first transistor is connected with a common potential through the first current source, and at least one second transistor is connected in series in the same direction and then connected between the drain electrode of the first transistor and a power supply.

In one embodiment, the first transistor and the second transistor are both operated in a saturation region; the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

In one embodiment, the relationship that the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor is: | Vth1| - | Vth0| ≧ Vod0| + margin;

wherein Vth1 is a threshold voltage of the first transistor, Vth0 is a threshold voltage of the second transistor, Vod0 is an overdrive voltage of the second transistor, and margin is a voltage margin.

In one embodiment, the gain amplifying circuit includes a first chopping operational amplifier, a second chopping operational amplifier, a first voltage dividing element, a second voltage dividing element and a third voltage dividing element, a positive input terminal of the first chopping operational amplifier serves as a first input terminal of the gain amplifying circuit, one end of the first voltage dividing element is connected to an output terminal of the first chopping operational amplifier, the other end of the first voltage dividing element is connected to a negative input terminal of the first chopping operational amplifier and one end of the second voltage dividing element, the other end of the second voltage dividing element is connected to a negative input terminal of the second chopping operational amplifier and one end of the third voltage dividing element, a positive input terminal of the second chopping operational amplifier serves as a second input terminal of the gain amplifying circuit, and the other end of the third voltage dividing element is connected to an output terminal of the second chopping operational amplifier, the output end of the first chopping operational amplifier is used as the first output end of the gain amplification circuit, and the output end of the second chopping operational amplifier is used as the second output end of the gain amplification circuit.

In one embodiment, the output filter circuit includes a first resistor, a second resistor, and a filter capacitor, one end of the first resistor and one end of the second resistor are respectively used as two input ends of the output filter circuit, the filter capacitor is connected in series between the other end of the first resistor and the other end of the second resistor, and the other end of the first resistor and the other end of the second resistor are respectively used as two output ends of the output filter circuit.

A second aspect of embodiments of the present application provides an integrated circuit comprising a chopping preamplifier as described above.

The input buffer stage in the chopping preamplifier adopts a source follower structure, so that the linearity performance and the gain precision performance can be greatly improved, and the bottleneck of performance of the input buffer stage is avoided; acting on the chopping respectively in first order input buffer to and inside the operational amplifier of second grade gain amplifier stage, thereby with the chopping decentralization, the chopping only handles little difference signal, avoids making a round trip to exchange big difference signal, thereby avoids big state change, and this has simplified the signal greatly and has been disturbed the back recovery degree of difficulty and recovery time, and is very little to the loss of the integrality of signal.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a chopping preamplifier provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a typical chopper switch and a schematic circuit diagram;

FIGS. 3A and 3B are schematic diagrams of two input buffer circuits in the chopper preamplifier of FIG. 1, respectively;

FIG. 4 is a schematic diagram of an exemplary input buffer circuit according to a first embodiment of the input buffer circuit shown in FIG. 3A;

FIG. 5 is a schematic diagram of an exemplary circuit of a second embodiment of the input buffer circuit shown in FIG. 3A;

FIG. 6 is a schematic diagram of an exemplary third embodiment of the input buffer circuit shown in FIG. 3B;

FIG. 7 is a schematic diagram of an exemplary input buffer circuit according to a fourth embodiment of the input buffer circuit shown in FIG. 3B;

FIG. 8 is a schematic diagram of an exemplary circuit of an embodiment of the input buffer circuit shown in FIG. 3A;

FIG. 9 is a schematic diagram of an exemplary circuit of a sixth embodiment of the input buffer circuit shown in FIG. 3A;

FIG. 10 is a schematic circuit diagram of a source follower structure input buffer circuit formed by a conventional single PMOS transistor and an input/output signal waveform thereof;

FIG. 11 is a schematic circuit diagram of the input buffer circuit shown in FIG. 4 and input/output signal waveforms thereof;

fig. 12 is an exemplary circuit schematic diagram of a first chopping preamplifier provided in an embodiment of the present application;

fig. 13 is an exemplary circuit schematic diagram of a second chopping preamplifier provided in an embodiment of the present application;

fig. 14 is an exemplary circuit schematic of a typical chopping operational amplifier.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Referring to fig. 1, a chopping preamplifier provided in the present application can be used in an integrated circuit. The chopper circuit comprises a first chopper switch 01, an input buffer circuit 02, a second chopper switch 03, a gain amplification circuit 04, and an output filter circuit 05.

Two input ends of a first chopping switch 01 are used as two input ends vin and vip of a chopping preamplifier to be respectively connected into two input signals, and the first chopping switch 01 is used for modulating the two input signals and then outputting the modulated two input signals; two input ends of the input buffer circuit 02 are connected with two output ends of the first chopping switch 01, and the input buffer circuit 02 adopts a source follower structure and provides impedance isolation for input signals and then outputs the signals; two input ends of the second chopping switch 03 are respectively connected with two output ends vbf _ n and vbf _ p of the input buffer circuit 02, and the second chopping switch 03 is used for outputting an output signal of the input buffer circuit 02 after being modulated; two input ends of the gain amplifying circuit 04 are connected with two output ends of the second chopping switch 03, and the gain amplifying circuit 04 adopts a chopping operational amplifier capable of eliminating detuning and noise and is used for amplifying the gain of the demodulated output signal and outputting an amplified signal after the detuning and the noise are eliminated; two input ends of the output filter circuit 05 are connected with the output ends vop _ f and von _ f of the gain amplifying circuit 04, and the output filter circuit 05 is used for filtering the amplified signal and outputting the filtered signal.

The chopping scheme of the chopping preamplifier comprises the following steps: chopping individually for the input buffer stage; chopping is placed in the operational amplifier aiming at the gain amplification stage, and only the operational amplifier is chopped. This localizes and narrows chopping. Through the dispersion of the traditional 'whole' chopping scheme arranged at the front end of the input buffer stage and the rear end of the gain amplification stage and a plurality of local chopping schemes, the chopping is only used for processing small differential signals, large differential signals are prevented from being exchanged back and forth, large state change is avoided, the recovery difficulty and recovery time of the signals after being disturbed are greatly simplified, and the loss of the integrity of the signals is very small.

Fig. 2 is a typical circuit diagram of a chopper switch, wherein the first chopper switch 01 and the second chopper switch 03 are identical, each having 4 ports, which are sequentially identified as a pair of input terminal in + and output terminal out +, and another pair of input terminal in-and output terminal out-, the two pairs of ports are completely symmetrical without any difference.

The input buffer circuit 02 includes two input buffer units 10, each of the input buffer units 10 includes a first current source Iss connected in series in the same direction (see fig. 3A) or in series in the reverse direction (see fig. 3B) between a power supply Vcc and a common potential Vss, a first main source follower 100 formed of a first transistor, and a first auxiliary source follower 200 formed of at least one second transistor, gates of the first transistor and the second transistor are connected in common as an input terminal of the input buffer circuit 02, a common point between the first current source Iss and the first main source follower 100 is connected as an input terminal of the input buffer circuit 02, and the first auxiliary source follower 200 is used to cancel a channel length modulation effect of the first main source follower 100.

The scheme is an improvement on the basis of an input buffer unit 10 formed by a single MOS tube, wherein the first main source follower 100 is also a single transistor, and the first auxiliary source follower 200 is a single or a plurality of transistors connected in series. And the first current source Iss, the first primary source follower 100 and the first secondary source follower 200 are connected in series in sequence, either forward or reverse, between the power supply Vcc and a common potential Vss (e.g., ground), depending on whether the transistor is P-type or N-type. The input buffer unit 10 uses different transistors to form two source followers, one of which is used as a main source follower, and the other is used as an auxiliary source follower, and the auxiliary source follower is used for eliminating the channel length modulation effect of the main source follower, so that the linearity and the gain precision of the preamplifier are greatly improved.

Regarding the embodiment of the input buffer unit 10, since two input buffer units 10 are required to be the same, without loss of generality, taking one input buffer unit 10 as an example:

the first embodiment is as follows:

referring to fig. 4, the first transistor and the second transistor in the input buffer unit 10 are PMOS transistors, and then the first current source Iss, the first main source follower 100 and the first auxiliary source follower 200 are sequentially connected in series between the power supply Vcc and the common potential Vss, the source of the first transistor is connected to the power supply Vcc through the first current source Iss, and at least one second transistor is connected in series in the same direction and then connected between the drain of the first transistor and the common potential Vss. Specifically, the first transistor is a PMOS transistor PM1, the second transistor is a PMOS transistor PM0, the substrate of the PMOS transistor PM0 is connected to the source thereof, and the drain of the PMOS transistor PM0 is grounded; the substrate of the PMOS transistor PM1 is connected with the source electrode thereof, and the drain electrode of the PMOS transistor PM1 is connected with the source electrode of the PMOS transistor PM 0. The first current source Iss provides a bias current, which is placed between the power supply Vcc and the source of the PMOS transistor PM1, in the direction from the power supply Vcc to the PMOS transistor PM 1. The input signal vin is applied to the input gates of the PMOS transistor PM0 and the PMOS transistor PM1, and the output signal vbf _ n is taken from the source of the PMOS transistor PM 1.

Example two:

referring to fig. 5, the input buffer unit 10 of the present embodiment is extended to a series structure of a plurality of PMOS source followers based on the first embodiment, wherein the first transistor PMOS transistor PM1 forms a "main" source follower, the remaining second transistors PMOS transistors PM _ a0 to PM _ an together form a first auxiliary source follower 200, the gates of the PMOS transistor PM1 and the PMOS transistors PM _ a0 to PM _ an are connected in common as the input of the preamplifier, and the output signal vbf _ n is taken from the source of the PMOS transistor PM1 as the output of the preamplifier.

Example three:

referring to fig. 6, the first transistor and the second transistor of the input buffer unit 10 are NMOS transistors, the first auxiliary source follower 200, the first main source follower 100, and the first current source Iss are sequentially connected in series between the power supply Vcc and the common potential Vss, the source of the first transistor is connected to the common potential Vss through the first current source Iss, and at least one second transistor is connected in series in the same direction between the drain of the first transistor and the power supply Vcc. Specifically, the first transistor is an NMOS transistor NM1, the second transistor is an NMOS transistor NM0, the substrate of the NMOS transistor NM0 is connected to the source thereof, and the drain of the NMOS transistor NM0 is connected to the power supply Vcc; the substrate of the NMOS transistor NM1 is connected to the source thereof, and the drain of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM 0. The first current source Iss supplies a bias current, which is placed between the common potential Vss and the source of the NMOS transistor NM1, in a direction from the power supply Vcc to the NMOS transistor NM1 to the common potential Vss. The input signal vin is simultaneously applied to the input gates of the NMOS transistor NM0 and the NMOS transistor NM1, and the output signal vbf — n is taken from the source of the NMOS transistor NM 1. In this embodiment, a series structure formed by 2 NMOS source followers is completely dual to the 2 PMOS transistor structures of the first embodiment. The common mode level of the input signal vin may be high at this time, for example, directly from the supply voltage.

Example four:

referring to fig. 7, the input buffer unit 10 of the present embodiment is extended to a series structure of a plurality of NMOS source followers based on the third embodiment, wherein the first transistor NMOS 1 constitutes a "main" source follower, the remaining second transistors NMOS _ a0 to NM _ an together constitute a first auxiliary source follower 200, the gates of the NMOS NM1 and NMOS NM _ a0 to NM _ an are connected in common as the input of the preamplifier, and the output signal vbf _ n is taken from the source of the NMOS NM1 as the output of the preamplifier. The series structure of the NMOS source followers in this embodiment is completely dual to the series structure of the PMOS source followers in the second embodiment.

Example five:

referring to fig. 8, the input buffer unit 10 of the present embodiment is extended to add a dc level shift module 300 on the basis of any one of the first to fourth embodiments. In this embodiment, the level shift module 300 is connected between the first current source Iss and the first master follower 100, a common node between the level shift module 300 and the first current source Iss is used as an output of the preamplifier, and the level shift module 300 is used to increase output level shift. The main and first auxiliary source followers 200 are not limited to PMOS transistors or NMOS transistors, and the number of MOS transistors of the first auxiliary source follower 200 is also not limited.

In the example shown in fig. 8, the dc level shifting module 300 is a resistor R0 serially connected between the output and the PMOS transistor PM1 of the first master follower, which can solve the problem that the output level shift is not enough due to the PMOS transistor PM1 alone, and at this time, the addition of the level shifting module 300 can further increase the dc level shift without affecting the signal quality. Sometimes, this level shifting module 300 is necessary for the gain amplifier circuit 04 of the second stage to operate at a comfortable bias voltage vbias. In other embodiments, the resistor R0 may be replaced by a circuit module, and regardless of the specific implementation of the circuit module, it is within the scope of the present disclosure as long as its function is to increase the dc level shift without affecting the signal quality.

Example six:

referring to fig. 9, the input buffer unit 10 of the present embodiment is extended to add a dc level shift module 400 based on any one of the first to fourth embodiments. In this embodiment, the level shift module 400 is connected between the first main source follower 100 and the first auxiliary source follower 200, and the level shift module 400 is used to increase the output level shift. The main and first auxiliary source followers 200 are not limited to PMOS transistors or NMOS transistors, and the number of MOS transistors of the first auxiliary source follower 200 is also not limited. In addition, the scheme in the present embodiment may be used in combination with the scheme in the fifth embodiment.

In the example shown in fig. 9, the dc level shifting block 400 is a resistor R1, and is connected in series between the PMOS transistor PM1 of the first main source follower 100 and the PMOS transistor PM0 of the first auxiliary source follower 200. The problem that the output level shift is insufficient due to the PMOS transistor PM1 alone can be solved, and the addition of the level shift module 400 can further increase the dc level shift without affecting the signal quality. In other embodiments, the resistor may be replaced by a circuit module, and regardless of the specific implementation of the circuit module, it is within the protection scope of the present solution as long as its function is to increase the dc level shift without affecting the signal quality.

It should be noted that, although fig. 8 and 9 illustrate a 2-stage MOS source follower series structure, they are applicable to a multi-stage MOS source follower series structure, and the insertion of a level shift module in these structures falls within the protection scope.

Referring to fig. 4, the first transistor and the second transistor in the input buffer unit 10 are PMOS transistors, and the first slave follower 200 is a PMOS transistor, for example, to explain the related principle. Specifically, the core part of the preamplifier adopts 2 PMOS tubes PM0 and PM1 and a first current source Iss. Therefore, from the structural point of view, the two PMOS transistors PM0 and PM1 both form a source follower, but their inputs are connected in parallel and their outputs are connected "in series". The PMOS pipe PM1 forms a main source follower, and the PMOS pipe PM0 forms an auxiliary source follower; the existence of the PMOS pipe PM0 carries out linearization processing on the PMOS pipe PM1, so that the linearity of the PMOS pipe PM1 is greatly improved, and the output signal vbuffer is generated by the PMOS pipe PM 1. Due to the ingenious connection relation, the linearity is greatly improved, the gain accuracy is greatly improved, and the performances in other aspects (such as the consumption of output impedance, noise, power consumption and voltage margin) are equivalent to those of a common single PMOS tube source follower. This is a very rare phenomenon in the field of analog circuit design, because in the field of analog circuit design, various trade-offs (tradeoff) are filled, and usually one circuit architecture is superior to another in performance in some respect, often at the expense of performance in other respect.

In the structure of fig. 4, PMOS transistor PM0 and PMOS transistor PM1 need to be carefully designed and dimensioned to ensure that 2 MOS transistors are operated in the saturation region, which is the basic requirement for this structure to function effectively. The difficulty of making the PMOS transistor PM0 work in the saturation region is that it must satisfy the following conditions:

|Vds1|≥(|Vgs1|-|Vth1|)+margin

vds1, Vgs1, Vth1 and margin are respectively the drain-source voltage, gate-source voltage, threshold voltage and voltage margin of a PMOS tube PM1, and margin is generally about 100-200 mV. Assuming that the common mode level of the input signal vin is 0, the above equation is further written as:

vbf_n-vt≥vbf_n-|Vth1|+margin

further comprises the following steps:

|Vth1|≥Vt+margin

due to the fact thatvt is | Vgs0| Vth0| + Vod0, vt is the drain of PMOS transistor PM1 and the source common junction voltage of PMOS transistor PM0, Vgs0, Vth0, Vod0 are the gate-source voltage, threshold voltage, overdrive voltage of PMOS transistor PM0,

thus, the above equation is further written as:

|Vth1|-|Vth0|≥Vod0+margin≈Vod0+100mV

this means that the threshold voltage of PMOS transistor PM1 must be larger than the threshold voltage of PMOS transistor PM0 by Vod0+ margin, i.e., at least over 100 mV. To achieve this goal, there are at least 2 possible solutions:

the first method comprises the following steps: the process will generally provide a variety of threshold MOS transistor options. The PM1 can be selected as a high-threshold transistor MOS and the PM0 as a low-threshold transistor MOS, which can easily achieve the goal.

And the second method comprises the following steps: by fine and smart sizing. When the W/L (W is the width of the conductive channel and L is the length of the conductive channel) of the PMOS transistor PM0 is large enough to operate in the subthreshold region, Vod0 is very small (e.g., 50 mV). Meanwhile, let L of the PMOS transistor PM0 be the minimum length in the current process (for example, for a 0.35um CMOS process, L is 0.35um), and the smaller threshold voltage is usually brought about by the lrin. In addition, the W/L of the PMOS transistor PM1 is made as small as possible, and L is made as large as possible under the current process (for example, for a 0.35um CMOS process, L is made 4um), so that Vod1 of the PMOS transistor PM1 is large enough, the channel length modulation effect of the PMOS transistor PM1 is small enough, and the linearity is good as possible. And a larger L for the PMOS transistor PM1 generally results in a larger threshold voltage. In this way, by making | Vth1| as large as possible, | Vth0| as small as possible, and Vod0 as small as possible, the above equation is satisfied, and the effect of the structure of the present scheme is exerted, and the linearity is further improved.

As a further analysis follows, the proposed structure of the solution can greatly improve the linearity and gain accuracy, and it is necessary to examine the problem through a comparative analysis.

Fig. 10 shows an input buffer cell 10 of a source follower structure formed of a conventional single PMOS transistor, with a substrate connected to a source. The gain from input to output is:

wherein gm is transconductance of the PMOS transistor PM1, and gds is output intrinsic admittance of the PMOS transistor PM 1. gm/gds is called the intrinsic gain of the MOS transistor, and usually this value is around 100, i.e. gds ≈ gm/100, which is usually negligible compared to gm, so that Av is approximately equal to 1. If used in high precision and high linearity applications, the effect of gds cannot be ignored. gds influences what characterizes the channel length modulation effect, and in this structure gds determines the accuracy and linearity of the gain completely. Note the definition of gds:

gds is therefore a function of vds (drain-source voltage of the MOS transistor). For the source follower of fig. 8, since vds vbf — n-0 ≈ vin, the gain Av is still actually a weak function of the input signal due to the influence of gds:

this is nonlinear and harmonic distortion is generated. Design and simulation results on a typical CMOS process show that the components of the 2 nd harmonic and the 3 rd harmonic of the input buffer unit 10 of the source follower structure formed by the traditional single PMOS tube are difficult to be lower than-80 dBc, which means that the effective digit (precision index, defined as ENOB ═ SNDR-1.76)/6.02) of a measurement system based on the input buffer unit 10 of the source follower structure of the single PMOS tube is at most about 13bits, and the input buffer unit is far from enough for high-precision application.

From an analysis of fig. 10, we know that the bottleneck is gds. It is the proposal of our patent that almost completely eliminates the effect of gds.

As shown in fig. 11, the input signal vin passes through 2 source followers, which generate vbf _ n and vt, respectively. We call PMOS transistor PM1 first master source follower 100 and PMOS transistor PM0 first slave source follower 200. vbf _ n and vt are almost exactly equal to the input signal vin, the magnitude of the error is the harmonic component (around-80 dBc, i.e. around ten thousandth of the signal itself).

Further, note the PMOS transistor PM1, which

vds＝vbf_n-vt≈vin+o(vin)-[vin+o(vin)]＝o(vin)≈0

Where mathematical notation is used, a small o means "much less than", e.g. o (vin) means a quantity much less than vin. Therefore, the source and drain of the PMOS transistor PM1 synchronously follow the input signal swing, but are almost 0 (fluctuation is about ten-thousandth of the input signal) in terms of their difference, so that the change in vds is not felt. Since vds is not sensed, gds of the PMOS transistor PM1 is also almost equal to 0. Thus, for the circuit structure of the present application:

the nonlinear components are greatly reduced, and therefore harmonic distortion is greatly reduced. Design and simulation results on the same CMOS process show that components of 2 th harmonic and 3 rd harmonic of the input buffer unit 10 adopting the new source follower structure provided by the application can be less than-120 dBc, which means that the highest effective digit of a measurement system of the input buffer unit 10 based on the source follower can reach a level close to 20bits, and the measurement system is enough for high-precision application occasions (generally, about 16bits is common).

On the other hand, the gain accuracy is an indicator to be considered, which is also crucial for high-accuracy measurement systems. In practice, each stage (buffer isolation, amplification, filtering, analog-to-digital conversion ….) in the signal processing chain introduces a gain, and the gain of each stage is affected by PVT (process variation, power supply fluctuation, temperature), and is often very complicated or even difficult to accurately depict. In the influence of PVT:

usually the influence of the supply ripple V can be solved by design, for example by placing it under LDO (Low dropout linear regulator) to keep V constant.

The influence of the process deviation P is usually solved by a calibration link before the chip/complete machine leaves a factory. The calibration is to record the gain value Av0 before the chip/complete machine leaves the factory and store it in the nonvolatile memory of the chip, which is called calibration. In normal use, the actual gain Av is calibrated with Av 0. In this way, sheet-to-sheet process variation is eliminated;

the influence of the temperature T is to make the gain of the circuit insensitive to the temperature through an excellent design level and a smart circuit structure.

For the source follower structure input buffer unit 10 formed by the conventional single PMOS transistor shown in fig. 8, the gain is:

wherein

gds (PVT) and gm (PVT) are both strongly temperature dependent, ranging from-40 ℃ to +85 ℃, with gds (PVT)/gm (PVT) variations often being more than 2 times higher. As before, a typical value for gds/gm is approximately 1%, and a typical value for Av is approximately 0.99; however, if considering the temperature variation of gds/gm, the variation of Av with temperature is as high as 1% or more, which brings a large measurement error, so that the high-precision measurement system becomes inaccurate. Since gds (pvt)/gm (pvt) is not only related to T but also to P, this means that the temperature curves of gds (pvt)/gm (pvt) may be different for each chip, making the idea of considering temperature compensation impractical (requiring temperature compensation for each, which is extremely expensive).

However, for the patent scheme proposed in the present application, the gain is:

wherein

Assuming that x itself has a value of about 1%, the variation over the full temperature range is also about 1%. As before, o (x) is an amount that is about 40dB (about 100 times) smaller than x, so that o (x) itself has a value of about 0.01%, and changes in the whole temperature range are also about 0.01% in order of magnitude, which translates to a temperature coefficient of about 8 ppm/c, which is the top level from the literature currently available, and meets the application of most high-precision measurement systems.

This application is with the source follower that 2 MOS pipes constitute, and the input is parallelly connected together, and the output "is established ties" together. One of the MOS transistors serves as a first main source follower 100, and the other or more MOS transistors serve as a first auxiliary source follower 200, and the output is taken from the first main source follower 100. The first auxiliary source follower 200 functions to eliminate the channel length modulation effect of the first main source follower 100, thereby greatly improving the linearity and gain accuracy of the input buffer unit 10.

In order to make the MOS transistors of the main and first auxiliary source followers 200 work in the saturation region, the design method adopted is as follows: one is to adopt a design method of a multi-threshold tube; and the other method adopts a more skillful tube size selection method. Both of these methods are described in detail above.

The input buffer unit 10 and the integrated circuit have excellent linearity and extremely accurate gain; the input signal does not need to provide an additional bias voltage vbias (the sensor can directly take ground as a common-mode signal); the circuit is extremely simple, is completely compatible with a CMOS (complementary metal oxide semiconductor) process, and does not need special devices; impedance isolation (high impedance input, low impedance output); other performances (such as noise, power consumption and consumption of voltage margin) are equivalent to those of the common single MOS tube source follower structure. This is a very rare phenomenon in the field of circuit design. In the field of circuit design, various trade-offs (tradeoff) are filled, and one circuit architecture has better performance than another in some aspects, often at the expense of performance in other aspects.

Referring to fig. 12 and 13, in one embodiment, the gain amplifying circuit 04 includes a first chopping operational amplifier a0, a second chopping operational amplifier a0_, a first voltage dividing element R21, a second voltage dividing element R22, and a third voltage dividing element R23, a positive phase input terminal of the first chopping operational amplifier a0 is used as a first input terminal of the gain amplifying circuit 04, one end of the first voltage dividing element R21 is connected to an output terminal of the first chopping operational amplifier a0, the other end of the first voltage dividing element R21 is connected to an inverting input terminal of the first chopping operational amplifier a0 and one end of the second voltage dividing element R22, the other end of the second voltage dividing element R22 is connected to an inverting input terminal of the second chopping operational amplifier a0_ and one end of the third voltage dividing element R23, a positive phase input terminal of the second operational amplifier a0_ is used as a second input terminal of the gain amplifying circuit 04, and the other end of the third voltage dividing element R23 is connected to an output terminal of the second chopping operational amplifier a0_ 0, the output terminal of the first chopping operational amplifier a0 serves as the first output terminal von of the gain amplifying circuit 04, and the output terminal of the second chopping operational amplifier a0_ serves as the second output terminal vop of the gain amplifying circuit 04.

Referring to fig. 12 and fig. 13, in one embodiment, the output filter circuit 05 includes a first resistor Rf, a second resistor Rf _ and a filter capacitor, one end of the first resistor Rf and one end of the second resistor Rf _ are respectively used as two input ends of the output filter circuit 05, the filter capacitor Cf is connected in series between the other end of the first resistor Rf and the other end of the second resistor Rf _ and the other ends of the first resistor Rf and the second resistor Rf _ are respectively used as two output ends of the output filter circuit 05, that is, as two outputs vop _ f and von _ f of the chopper preamplifier.

In this embodiment, the chopped pre-differential amplifier is a differential structure formed on the basis of the embodiment shown in fig. 4, the differential circuit has symmetry, and the natural ability of suppressing even harmonics is provided, so that the differential circuit is widely used, and most of the amplifier circuits in practical application appear in a differential (or pseudo-differential) manner.

It should be noted that, although the two input buffer units 10 of the chopping front differential amplifier are illustrated as 2-stage PMOS series structures, in fact, a differential circuit can be formed for all structures including, but not limited to, embodiments one to six, which belong to the protection scope of the present application. The voltage dividing element may be a passive circuit including at least one of a resistor, a capacitor, an inductor, and a transistor.

Functionally, the first chopping switch 01 performs a modulation function on the input signals vip, vin, and the second chopping switch 03 performs a demodulation function on the output signals vbf _ p, vbf _ n of the input buffer circuit 02. The final effect is that the signal has no effect (from vip, vin → vbf _ p, vbf _ n), but the noise of the differential input buffer circuit 02 between the first chopper switch 01 and the second chopper switch 03 undergoes only one demodulation process, and therefore, a spectrum shift occurs, and the low-frequency 1/f noise is shifted to a high frequency and finally filtered by a filter in the subsequent stage.

The gain amplifying circuit 04 is composed of two operational amplifiers (a0 and a0_) and 3 voltage dividing elements (R21, R22 and R23), wherein a0 and a0_ are identical operational amplifiers, and the gain amplifying circuit 04 is also an identical differential structure. Operational amplifiers a0 and a0 are internally provided with a chopping function, and fig. 14 shows a chopping implementation of a typical differential input single-ended output type operational amplifier. The output filter circuit 05 mainly filters high-frequency noise of the circuit, and has a cutoff frequency much higher than the signal frequency, so that it is all-pass to the signal (the gain is 1 in the signal band).

One improvement of the present application is with respect to the input buffer stage and another improvement is with respect to the chopping scheme.

The input buffer stage adopts a very special structure, and is a source follower structure with high input impedance, enhanced linearity and accurate gain. And the performances (such as output impedance, noise, power consumption and consumption of voltage margin) of other aspects are equivalent to that of a common single MOS tube source follower.

The gain of the whole chopping preamplifier is:

by varying the proportions of R21, R22, and R23, the desired gain can be achieved.

Because the second-stage gain stage adopts the closed-loop feedback mode of the operational amplifier, the linearity and the gain precision of the gain stage can be very good as long as the open-loop gain of the operational amplifier is high enough.

The input buffer circuit structure greatly improves linearity and gain precision. Design and simulation results on a typical CMOS process show that components of 2 th harmonic and 3 rd harmonic of a source follower structure input buffer formed by a traditional single MOS tube are difficult to be < -80dBc, and the variation of gain with temperature is as high as +/-1%, which is far from enough for high-precision application. By adopting the input buffer structure in the application, the components of the 2 nd harmonic and the 3 rd harmonic can be < -120dBc, the gain changes with the temperature as low as +/-0.01 percent, and the input buffer structure is enough for most high-precision systems. Most importantly, this is achieved on a pure CMOS process without any special devices and without the support of an expensive BiCMOS process.

For the input buffer stage, chopping is placed at its input and output. Because the gain of the input buffer stage is 1, the signal is not amplified, so that small differential signals are processed at the first chopping switch 01 and the second chopping switch 03, the caused disturbance and recovery time are very small, and the loss of the integrity of the signal is very small.

For gain amplifier stages, chopping is placed inside the op-amp. Chopping is located on the input of the op-amp and the differential path of the current signal. It is known that when the operational amplifier operates in a closed loop state, a differential signal processed by the operational amplifier is a very small error signal, so that a chopper switch operating inside the operational amplifier causes very little disturbance and very little loss of signal integrity.

And in the stage gain amplification stage, chopping is arranged in 2 operational amplifiers, namely only the operational amplifiers are chopped, and no chopping is performed on voltage division elements. If the voltage dividing element has mismatch or 1/f noise, it will be directly presented at the output. If the voltage dividing element adopts a passive device, 1/f noise does not exist; through reasonable design, the matching precision can be extremely high.

The practical design test result shows that by adopting the scheme provided by the application, the 1/f noise inflection point frequency of the whole chopping preamplifier can be as low as <1Hz, and the detuning is <10 uV. If high-level system-level chopping is matched, the offset can be further reduced to <1 uV. Because the signal integrity loss caused by chopping is greatly reduced, and the use of a high-linearity input buffer is matched, the components of 2-order harmonic and 3-order harmonic of the whole chopping preamplifier can be less than-120 dBc, the variation of gain along with temperature is as low as +/-0.01 percent, and the chopping preamplifier has high-precision property.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A chopping preamplifier, comprising:

2. The chopped preamplifier of claim 1, wherein said input buffer circuit comprises two input buffer cells, each of said input buffer cells comprising a first current source connected in series in either a series in-or-reverse direction between a power supply and a common potential, a first main source follower formed of a first transistor, and a first auxiliary source follower formed of at least one second transistor, the gates of said first and second transistors being commonly connected as an input to said input buffer circuit, the common connection between said first current source and said first main source follower being an output of said input buffer circuit, said first auxiliary source follower being operative to cancel the channel length modulation effects of said first main source follower.

3. The chopping preamplifier of claim 2, wherein the input buffer unit further comprises a level shifting module for increasing an output level shift, wherein:

4. The chopped preamplifier of claim 3, wherein said level shifting module is connected between said first main source follower and said first auxiliary source follower.

5. The chopping preamplifier of claim 2, wherein said first and second transistors are PMOS transistors, the source of said first transistor being connected to a power supply via said first current source, at least one of said second transistors being connected in series with one another in the same direction between the drain of said first transistor and a common potential; or

6. The chopped preamplifier of any one of claims 2 to 5, wherein said first transistor and said second transistor are both operated in the saturation region; the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

7. The chopping preamplifier of claim 6, wherein the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor is in a relationship of: | Vth1| - | Vth0| ≧ Vod0| + margin;

8. The chopping preamplifier of claim 1, wherein the gain amplification circuit comprises a first chopping operational amplifier, a second chopping operational amplifier, a first voltage dividing element, a second voltage dividing element, and a third voltage dividing element, wherein a positive phase input terminal of the first chopping operational amplifier serves as a first input terminal of the gain amplification circuit, one end of the first voltage dividing element is connected to an output terminal of the first chopping operational amplifier, the other end of the first voltage dividing element is connected to an inverting input terminal of the first chopping operational amplifier and one end of the second voltage dividing element, the other end of the second voltage dividing element is connected to an inverting input terminal of the second chopping operational amplifier and one end of the third voltage dividing element, and a positive phase input terminal of the second chopping operational amplifier serves as a second input terminal of the gain amplification circuit, the other end of the third voltage division element is connected with the output end of the second chopping operational amplifier, the output end of the first chopping operational amplifier serves as the first output end of the gain amplification circuit, and the output end of the second chopping operational amplifier serves as the second output end of the gain amplification circuit.

9. The chopper preamplifier according to claim 1, wherein the output filter circuit includes a first resistor, a second resistor, and a filter capacitor, one end of the first resistor and one end of the second resistor respectively serve as two input terminals of the output filter circuit, the filter capacitor is connected in series between the other end of the first resistor and the other end of the second resistor, and the other end of the first resistor and the other end of the second resistor respectively serve as two output terminals of the output filter circuit.

10. An integrated circuit comprising a chopping preamplifier as claimed in any one of claims 1 to 9.