CN111384940B - High-linearity wide-swing CMOS voltage follower - Google Patents
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Abstract
The invention discloses a high-linearity wide-swing CMOS voltage follower, when the input voltage is as low as 0V, all MOS tubes can fully work in a saturation region, so that the voltage follower can be ensured to work normally; along with the increase of the input voltage, the drain voltage of the PMOS transistor P9 approaches the power supply voltage VDD, and at this time, the PMOS transistor P9 enters the linear region, so that the gate voltage of the PMOS transistor P9 drops sharply, but as long as the voltage does not drop to force the NMOS transistor N3 to enter the linear region, the voltage follower can still work normally. Therefore, the gate voltage of the PMOS tube P9 can be lower than 2Vdsat, and the gate voltage of the PMOS tube P9 allows the swing amplitude to be greatly expanded.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a high-linearity wide-swing CMOS voltage follower.
Background
Source followers are the basic implementation of CMOS voltage followers. A conventional super source follower circuit is shown in FIG. 1, wherein the input terminal is MOS transistor gate (high input impedance) and the output resistance is equal toDue to the negative feedback introduced by the P2 tube, the equivalent transconductance of the input tube P1 is amplified, thus providing a lower output resistance. The Thevenin equivalent model of this super source follower is shown in FIG. 2, which shows that the voltage gain is equal to/>For a voltage follower, we want the output resistance Rout to be smaller the better so that the voltage gain Av approaches 1.
The power supply voltage under advanced CMOS technology is lower and lower, the voltage margin is very tight for analog circuits, and for analog circuits requiring a large voltage output swing, such as voltage followers, it is more difficult to ensure that each MOS transistor always works fully in the saturation region.
As shown in fig. 1, when the input voltage increases, the drain voltage (i.e., the output voltage) of the P2 tube approaches the power supply voltage, and the P2 tube easily enters the linear region, resulting in a decrease in g m2; at the same time, the gate voltage of the P2 tube drops sharply, the current source IB enters the linear region, causing r oB to decrease and the output resistance Rout to increase under the superposition effect. According to the voltage gain formula, av is reduced, and the voltage following effect is poor. From another perspective, IB enters the linear region and no longer provides a constant current, and then the gate-source voltage of the P1 tube no longer remains constant, and therefore the effect of the P1 tube source voltage (i.e., output voltage) following the gate voltage (i.e., input voltage) is poor.
The advancement of CMOS process nodes forces us to make full use of the linear region to obtain more voltage space, namely: after the P2 pipe enters the linear region, the condition that the voltage follower can still work normally can be maintained for a long time.
From the above analysis, it can be seen that: (1) P1, P2 and IB are in a saturation region, g m2 is constant, r oB is almost unchanged, and a voltage following effect can be realized naturally. (2) As the input voltage increases, the P2 tube starts to enter the linear region, g m2 is no longer constant, and decreases linearly with increasing input voltage (i.e., increasing output voltage) (linear region g m2＝βVDS), so the output impedance does not increase significantly immediately, i.e.: the voltage follower effect of the super source follower does not vanish immediately. (3) The effect of stage (2) is that the drop in P2 tube gate voltage will cause IB to enter the linear region, thus r oB drops sharply, which will cause the output impedance to rise sharply, and the super source follower will lose voltage follower.
Thus, it is known that the voltage following action of the super source follower is ensured by the constant current source IB, that is: the higher the upper input voltage limit of the super source follower, if the P2 pipe gate has a wider allowed voltage swing. However, there is an inherent conflict with the structure shown in fig. 1: to expand the allowed swing of the P2 gate voltage, it is desirable that the P2 gate (i.e., P1 drain) be biased at a higher voltage; but to ensure that the input pipe P1 always operates in the saturation region, the P2 gate (i.e., P1 drain) is required to be biased at a lower voltage.
The prior art adopts the super source electrode follower with the structure shown in the figure 3 to realize the voltage follower, so that the inherent contradiction can be solved. Compared with fig. 1, the source follower formed by IB2 and P3 tubes is added, so that each MOS tube is ensured to operate in the saturation region, but the voltage follower with such a structure sacrifices the allowable voltage range of the gate of the P2 tube, because the minimum allowable voltage of the gate of the P2 tube is Vdsat (IB 1) +vgs (P3). In summary, it is difficult for conventional structures to expand the voltage swing by utilizing the P2 tube to initially enter the phase of the linear region.
Disclosure of Invention
The invention aims to provide a high-linearity wide-swing CMOS voltage follower structure which can accurately realize voltage following in a wider input voltage range and can ensure higher linearity in a wider voltage input range compared with a traditional structure.
The technical scheme of the invention is as follows: the high-linearity wide-swing CMOS voltage follower is characterized by comprising a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a PMOS tube P5, a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, a PMOS tube P10, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, a reference current source Iref, a resistor R1, a resistor R2, a capacitor C1, a bias voltage Vb and a voltage source VDD;
One end of the reference current source Iref is respectively connected to one end of the resistor R1, the grid electrode of the PMOS tube P5, the grid electrode of the PMOS tube P6, the grid electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P8; the other end of the resistor R1 is respectively connected to the grid electrode of the PMOS tube P1, the grid electrode of the PMOS tube P2, the grid electrode of the PMOS tube P3, the grid electrode of the PMOS tube P4 and the drain electrode of the PMOS tube P5; the voltage source VDD is respectively connected to the source of the PMOS tube P1, the source of the PMOS tube P2, the source of the PMOS tube P3, the source of the PMOS tube P4 and the source of the PMOS tube P9; the drain electrode of the PMOS tube P1 is connected to the source electrode of the PMOS tube P5; the drain electrode of the PMOS tube P2 is connected to the source electrode of the PMOS tube P6; the drain electrode of the PMOS tube P3 is connected to the source electrode of the PMOS tube P7; the drain electrode of the PMOS tube P4 is connected to the source electrode of the PMOS tube P8; the drain electrode of the PMOS tube P6 is respectively connected to the drain electrode of the NMOS tube N4, the grid electrode of the NMOS tube N1 and the grid electrode of the NMOS tube N2; the drain electrode of the PMOS tube P7 is respectively connected to the grid electrode of the NMOS tube N4, the drain electrode of the NMOS tube N5 and the grid electrode of the NMOS tube N5; the drain electrode of the PMOS tube P8 is respectively connected to the grid electrode of the PMOS tube P9, the drain electrode of the NMOS tube N3 and one end of the resistor R2; the drain electrode of the PMOS tube P9 is respectively connected to the source electrode of the PMOS tube P10 and one end of the capacitor C1 and is used as a voltage output end Vout, and the other end of the capacitor C1 is connected with the other end of the resistor R2; the drain electrode of the PMOS tube P10 is respectively connected to the drain electrode of the NMOS tube N2, the source electrode of the NMOS tube N3 and the source electrode of the NMOS tube N5; the grid electrode of the PMOS tube P10 is connected to the voltage input end Vin, and the drain electrode of the NMOS tube N1 is connected to the source electrode of the NMOS tube N4; the bias voltage Vb is connected to the grid electrode of the NMOS tube N3; meanwhile, the source electrode of the NMOS transistor N1, the source electrode of the NMOS transistor N2, and the other end of the reference current source Iref are all grounded.
As a preferable technical solution, the size ratio of the NMOS transistor N1 to the NMOS transistor N2 is 1: m+1, and the dimensions match each other.
As a preferable technical scheme, the size ratio of the NMOS tube N4 to the NMOS tube N5 is 1:1, and the sizes are matched with each other.
The invention has the advantages that:
1. the high-linearity wide-swing CMOS voltage follower structure provided by the invention can accurately realize voltage following in a wider input voltage range, and can ensure higher linearity in a wider voltage input range compared with a traditional structure.
Drawings
The invention is further described below with reference to the accompanying drawings and examples:
FIG. 1 is a schematic diagram of a low power consumption super source follower structure;
FIG. 2 is a diagram of a Thevenin equivalent model;
FIG. 3 is a schematic diagram of a super source follower structure commonly employed to overcome the inherent contradiction;
FIG. 4 is a schematic diagram of a high linearity wide swing CMOS voltage follower according to the present invention;
FIG. 5 is a simulated plot of the relationship between voltage gain at 10MHz and input common mode voltage for the present and conventional structures;
FIG. 6 is a simulated plot of Total Harmonic Distortion (THD) versus input signal power for a 10MHz sinusoidal voltage signal for the present invention and conventional constructions;
FIG. 7 is a graph showing the comparison of simulation results of the double tone test (frequency points of 11MHz and 12 MHz) of the present invention and the conventional structure.
Detailed Description
Examples: referring to fig. 4, a high linearity wide swing CMOS voltage follower is characterized by comprising a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, a PMOS transistor P4, a PMOS transistor P5, a PMOS transistor P6, a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, a PMOS transistor P10, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, a reference current source Iref, a resistor R1, a resistor R2, a capacitor C1, a bias voltage Vb, and a voltage source VDD; one end of the reference current source Iref is respectively connected to one end of the resistor R1, the grid electrode of the PMOS tube P5, the grid electrode of the PMOS tube P6, the grid electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P8; the other end of the resistor R1 is respectively connected to the grid electrode of the PMOS tube P1, the grid electrode of the PMOS tube P2, the grid electrode of the PMOS tube P3, the grid electrode of the PMOS tube P4 and the drain electrode of the PMOS tube P5; the voltage source VDD is respectively connected to the source of the PMOS tube P1, the source of the PMOS tube P2, the source of the PMOS tube P3, the source of the PMOS tube P4 and the source of the PMOS tube P9; the drain electrode of the PMOS tube P1 is connected to the source electrode of the PMOS tube P5; the drain electrode of the PMOS tube P2 is connected to the source electrode of the PMOS tube P6; the drain electrode of the PMOS tube P3 is connected to the source electrode of the PMOS tube P7; the drain electrode of the PMOS tube P4 is connected to the source electrode of the PMOS tube P8; the drain electrode of the PMOS tube P6 is respectively connected to the drain electrode of the NMOS tube N4, the grid electrode of the NMOS tube N1 and the grid electrode of the NMOS tube N2; the drain electrode of the PMOS tube P7 is respectively connected to the grid electrode of the NMOS tube N4, the drain electrode of the NMOS tube N5 and the grid electrode of the NMOS tube N5; the drain electrode of the PMOS tube P8 is respectively connected to the grid electrode of the PMOS tube P9, the drain electrode of the NMOS tube N3 and one end of the resistor R2; the drain electrode of the PMOS tube P9 is respectively connected to the source electrode of the PMOS tube P10 and one end of the capacitor C1 and is used as a voltage output end Vout, and the other end of the capacitor C1 is connected with the other end of the resistor R2; the drain electrode of the PMOS tube P10 is respectively connected to the drain electrode of the NMOS tube N2, the source electrode of the NMOS tube N3 and the source electrode of the NMOS tube N5; the grid electrode of the PMOS tube P10 is connected to the voltage input end Vin, and the drain electrode of the NMOS tube N1 is connected to the source electrode of the NMOS tube N4; the bias voltage Vb is connected to the grid electrode of the NMOS tube N3; meanwhile, the source electrode of the NMOS transistor N1, the source electrode of the NMOS transistor N2, and the other end of the reference current source Iref are all grounded.
The bias voltage Vb of the NMOS transistor N3 is designed at a lower value, so that the NMOS transistor N2 is biased at the edge of the saturation region. The embodiment is built under the 40nm CMOS process and the 1.2V power supply voltage, the drain-source voltage bias of the NMOS tube N2 is about 150mV, so that the more sufficient drain-source voltage of the input tube (the PMOS tube P10) can be ensured, and meanwhile, the better linearity performance of the invention is ensured by the sufficient drain-source voltage of the PMOS tube P10.
The working principle of the invention is as follows: the reference current is mirrored into two paths of currents through the low-voltage cascode current mirror, and flows into a mirrored current source formed by an NMOS tube N1, an NMOS tube N2, an NMOS tube N4 and an NMOS tube N5 through a PMOS tube P6 and a PMOS tube P7. The size ratio of the NMOS transistor N4 to the NMOS transistor N5 is 1:1 and the sizes are matched with each other, so that the source voltage of the NMOS transistor N4 is equal to the source voltage of the NMOS transistor N5, i.e., the drain voltage of the NMOS transistor N1 is equal to the drain voltage of the NMOS transistor N2; the size ratio of the NMOS tube N1 to the NMOS tube N2 is 1: m+1 and the sizes are mutually matched, so that a good current mirror relationship between the NMOS transistor N1 and the NMOS transistor N2 can be realized. The output current is approximately equal to M times the reference current, which provides a constant bias current for the following voltage follower. Importantly, the constant current source is still able to maintain a high output impedance when the NMOS transistor N2 enters the linear region. Because the circuit can ensure that the drain voltages of the NMOS tube N1 and the NMOS tube N2 are approximately equal as long as the NMOS tube N4 and the NMOS tube N5 work in the saturation region and the gate voltages of the NMOS tube N1 and the NMOS tube N2 do not rise to force the common-source common-gate current source formed by the PMOS tube P2 and the PMOS tube P6 to enter the linear region, and the proportional relation between the output current of the NMOS tube N2 and the reference current flowing into the NMOS tube N1 is not changed, the constant current (namely high output impedance) can be maintained at lower voltage. Further, the gate voltage Vb of the NMOS transistor N3 in the voltage follower body circuit may be low enough to bias the NMOS transistor N2 (while the NMOS transistor N1) in a shallow linear region (e.g., the drain-source voltage is 100-150 mV), at which time the NMOS transistor N2 is still able to provide a constant bias current to the voltage follower.
When the input voltage is as low as 0V, all MOS tubes can fully work in a saturation region, so that the voltage follower can be ensured to work normally; along with the increase of the input voltage, the drain voltage of the PMOS transistor P9 approaches the power supply voltage VDD, and at this time, the PMOS transistor P9 enters the linear region, so that the gate voltage of the PMOS transistor P9 drops sharply, but as long as the voltage does not drop to force the NMOS transistor N3 to enter the linear region, the voltage follower can still work normally. Therefore, the gate voltage of the PMOS transistor P9 can be as low as VdsatN + VdsatN =2vdsat, and the gate voltage of the PMOS transistor P9 allows the swing to be greatly expanded.
The NMOS tube N2 does not need to take a larger channel length, and only a good size matching relation of the NMOS tube N1 and the NMOS tube N2 is ensured; the PMOS transistor P9 may take a smaller channel length value and a larger width to length ratio to maintain a larger transconductance value. Therefore, the invention has better high-frequency response.
The implementation case and the traditional structure of the invention are built under the 40nm CMOS technology and the voltage of 1.2V, and the driving load capacitance is 5pF. As can be seen from fig. 5, the present invention can maintain a stable voltage gain over a wider voltage range, i.e., maintain a voltage follower action. As can be seen from fig. 6, the present invention is able to maintain lower nonlinear distortion when the input signal power is higher than in the conventional structure. As can be seen from fig. 7, the 1dB compression point of the output voltage of the present invention is higher, the third order intermodulation product (IM 3) is significantly lower than that of the conventional structure, the third order output intermodulation product (OIP 3) of the present invention is 28.76dBm, and the OIP3 of the conventional structure is 24.78dBm, which is improved by about 4dB.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (3)
1. The high-linearity wide-swing CMOS voltage follower is characterized by comprising a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a PMOS tube P5, a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, a PMOS tube P10, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, a reference current source Iref, a resistor R1, a resistor R2, a capacitor C1, a bias voltage Vb and a voltage source VDD;
One end of the reference current source Iref is respectively connected to one end of the resistor R1, the grid electrode of the PMOS tube P5, the grid electrode of the PMOS tube P6, the grid electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P8; the other end of the resistor R1 is respectively connected to the grid electrode of the PMOS tube P1, the grid electrode of the PMOS tube P2, the grid electrode of the PMOS tube P3, the grid electrode of the PMOS tube P4 and the drain electrode of the PMOS tube P5; the voltage source VDD is respectively connected to the source of the PMOS tube P1, the source of the PMOS tube P2, the source of the PMOS tube P3, the source of the PMOS tube P4 and the source of the PMOS tube P9; the drain electrode of the PMOS tube P1 is connected to the source electrode of the PMOS tube P5; the drain electrode of the PMOS tube P2 is connected to the source electrode of the PMOS tube P6; the drain electrode of the PMOS tube P3 is connected to the source electrode of the PMOS tube P7; the drain electrode of the PMOS tube P4 is connected to the source electrode of the PMOS tube P8; the drain electrode of the PMOS tube P6 is respectively connected to the drain electrode of the NMOS tube N4, the grid electrode of the NMOS tube N1 and the grid electrode of the NMOS tube N2; the drain electrode of the PMOS tube P7 is respectively connected to the grid electrode of the NMOS tube N4, the drain electrode of the NMOS tube N5 and the grid electrode of the NMOS tube N5; the drain electrode of the PMOS tube P8 is respectively connected to the grid electrode of the PMOS tube P9, the drain electrode of the NMOS tube N3 and one end of the resistor R2; the drain electrode of the PMOS tube P9 is respectively connected to the source electrode of the PMOS tube P10 and one end of the capacitor C1 and is used as a voltage output end Vout, and the other end of the capacitor C1 is connected with the other end of the resistor R2; the drain electrode of the PMOS tube P10 is respectively connected to the drain electrode of the NMOS tube N2, the source electrode of the NMOS tube N3 and the source electrode of the NMOS tube N5; the grid electrode of the PMOS tube P10 is connected to the voltage input end Vin, and the drain electrode of the NMOS tube N1 is connected to the source electrode of the NMOS tube N4; the bias voltage Vb is connected to the grid electrode of the NMOS tube N3; meanwhile, the source electrode of the NMOS transistor N1, the source electrode of the NMOS transistor N2, and the other end of the reference current source Iref are all grounded.
2. The high linearity, wide swing CMOS voltage follower of claim 1, wherein the size ratio of the NMOS transistor N1 to the NMOS transistor N2 is 1: m+1, and the dimensions match each other.
3. The high linearity wide swing CMOS voltage follower of claim 1, wherein the size ratio of the NMOS transistor N4 to the NMOS transistor N5 is 1:1 and the sizes are matched to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911290130.2A CN111384940B (en) | 2019-12-16 | High-linearity wide-swing CMOS voltage follower |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911290130.2A CN111384940B (en) | 2019-12-16 | High-linearity wide-swing CMOS voltage follower |
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| Publication Number | Publication Date |
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| CN111384940A CN111384940A (en) | 2020-07-07 |
| CN111384940B true CN111384940B (en) | 2024-06-04 |
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