CN108540134A - A kind of input buffer applied in A/D converter with high speed and high precision - Google Patents
A kind of input buffer applied in A/D converter with high speed and high precision Download PDFInfo
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- CN108540134A CN108540134A CN201810226505.8A CN201810226505A CN108540134A CN 108540134 A CN108540134 A CN 108540134A CN 201810226505 A CN201810226505 A CN 201810226505A CN 108540134 A CN108540134 A CN 108540134A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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Abstract
The invention belongs to technical field of integrated circuits, and in particular to a kind of input buffer applied in A/D converter with high speed and high precision.It includes source follower, auxiliary operation amplifier, level shift pipe with compensating electric capacity.Sampling capacitance capacitance is big in A/D converter with high speed and high precision, need to be inserted into input buffer when in use between signal source and analog-digital converter drive sampling capacitance in A/D converter with high speed and high precision, be isolated analog-digital converter core circuit with piece external signal source, the parasitic inductance of analog-digital converter core circuit and chip package is isolated.Traditional integrated analog digit converter input buffer is realized that the input and output that the structure is difficult to reach more than 14 are linearly spent by source follower.The present invention passes through in traditional source follower with compensating electric capacity（Emitter follower）On the basis of increase auxiliary operation amplifier, realize operational amplifier auxiliary input buffer, significantly improve the linearity of integrated analog digit converter input buffer.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to the input buffering in A/D converter with high speed and high precision
Device.
Background technology
With the rapid development of IT industry, internet just gradually changes to Internet of Things, as Internet of Things key skill
The new generation of wireless communication technology, information sensing and the treatment technology of art are all highly dependent on the analog-to-digital conversion in high-speed, high precision.Mesh
Preceding A/D converter with high speed and high precision is in mobile communication equipment, communication base station, all kinds of analog signals sensing and converting system
In play irreplaceable role, with the continuous development of Internet of Things, A/D converter with high speed and high precision will also have more wide
Wealthy application scenarios, while the development of Internet of Things also will be to propositions such as the speed of analog-digital converter, precision, power consumption, costs more
High requirement.
Analog-digital converter core circuit for a long time be always industrial quarters, academia research hotspot, by many decades
Development, the performance of analog-digital converter core circuit are greatly improved.Especially since last decade, researcher constantly carries
Various novel analog-digital converter core circuit frameworks are gone out, constantly the modules in analog-digital converter core circuit have been carried out
Optimization, the performances such as speed, precision, power consumption of analog-digital converter core circuit all increase substantially.Although in the past many decades
The research of high speed high-precision adc core circuit achieves breakthrough, but to analog-digital converter core circuit
Supplementary module, such as input buffer, Voltage Reference Buffer etc. research it is few.With analog-digital converter core circuit performance
Continuous improvement, the bottleneck that limitation analog-to-digital conversion rate, precision etc. further increase is just gradually from analog-digital converter core circuit
It is changed into other circuit modules of submodule converter core circuit work, it is anticipated that with input buffer, reference voltage
Buffer is that the A/D converter with high speed and high precision core circuit auxiliary circuit module of representative will be as following research hotspot.
In A/D converter with high speed and high precision core circuit supplementary module, input buffer plays driving analog-digital converter
Isolation analog-digital converter core circuit and piece external signal source, analog-digital converter core circuit and chip package is isolated in sampling capacitance
Parasitic inductance effect.Fig. 1 illustrates the analog-digital converter sampling network without input buffer, the signal source of chip exterior
101 are connected to chip interior by chip package, and sampled switch 103 drives the sampling capacitance 104 in number converter, chip envelope
Harness has certain parasitic inductance 102.As shown in Fig. 2, analog-digital converter is in clock φ（201）Under control alternately sampling with
Conversion, due to maintaining the charge that last time samples on sampling capacitance, is protected in the sampling phase starting stage on sampling capacitance
The charge held can recalcitrate（kick-back）To signal source, lead to input signal VinGenerate burr（202、203）.Analog-digital converter
Precision is higher, and required sampling capacitance is bigger, and burr is bigger caused by recalcitrating, and being recalcitrated in high-precision adc will be serious
Influence the quality of input signal.Input signal will be restored to the voltage of signal source after a period of time in the burr caused by recalcitrate,
The speed of recovery is mainly influenced by the size of signal source driving capability and sampling capacitance, and signal source driving capability is stronger, restores to get over
Quickly, and sampling capacitance is bigger, restore it is slower.In A/D converter with high speed and high precision, the sampling time is short, sampling capacitance
Greatly, normal signal source is difficult in time restore after being recalcitrated influence, therefore, as shown in figure 3, A/D converter with high speed and high precision
Input buffer is needed to drive big sampling capacitance, input buffer output signal to follow input signal, and isolation input signal
Source and sampling capacitance.Simultaneously if it is considered that the parasitic inductance of encapsulation, when sampling beginning, sampling network impedance changes, and adopts
It will appear damped oscillation ring on sample signal, input signal quality caused to decline, input buffer, which is added, can also reduce ring.
However the input-output of input buffer is not ideal linear relationship, the output signal of input buffer（
That is the input signal of analog-digital converter core circuit）The input signal of input buffer is not followed strictly（Namely signal source letter
Number）, therefore the addition of input buffer can reduce the quality for the signal that analog-digital converter core circuit samples.Traditional input
Buffer is realized using the source follower with compensating electric capacity or emitter follower, illustrates to input by taking source follower as an example below
The nonlinear problem that buffer introduces, emitter follower are similar.
Fig. 4 is the source follower with compensating electric capacity, and NMOS tube 401,402 forms source follower tail current source, NMOS
Pipe 104 follows pipe, input signal V as source electrodein, output signal Vout, source follower input, output signal direct current
Position is different, but output signal alternating component follows input signal alternating component.As input buffer, source follower is flowed through
Electric current is larger, to provide enough driving capabilities.Fig. 4 increases compensating electric capacity 405 on the basis of traditional source follower, mends
Repaying capacitance should be suitable with analog-digital converter sampling capacitance capacitance, in sampling phase, is adopted when there is transient current to flow into analog-digital converter
When sample capacitance, there is comparable transient current to flow to source electrode by compensating electric capacity stream 405 and NMOS tube 403 and follow pipe 404, compensation electricity
The addition of appearance makes source electrode that the curent change of pipe be followed to reduce, and improves the linearity of source follower.Source electrode follows pipe 404
Drain electrode is connected to fixed power supply, and when input signal changes, source electrode follows the gate-source of pipe 404, gate-drain voltage to believe with input
Number variation and significantly change, due to the influence of the factors such as parasitic capacitance is non-linear, channel-length modulation, with input signal
Changing and the gate-source of significantly change, gate-drain voltage introduce non-linear.Further improved source follower such as Fig. 5 institutes
Show, Fig. 5 has increased switched-capacitor level shifter 506 and level shift pipe 505 newly on the basis of Fig. 4, in turning for analog-digital converter
Commutation position（）Switched-capacitor level shifter 506 is resetted and is charged by bias voltage Vb4, Vb5, in adopting for analog-digital converter
Sample phase（φ）, switched-capacitor level shifter is by input signal VinIt boots to V1So that V1DC level is higher than Vin, and V1
AC compounent follows input signal Vin。V1V is moved down into using level shift pipe 5052So that V2DC level is less than V1, and V2
AC compounent follows V1AC compounent, therefore V2AC compounent follows input signal VinAC compounent.Source electrode follows the leakage of pipe 504
Pole tension is with input signal VinVariation, the amplitude that gate-source, gate-drain voltage change and convert with input signal is small, improves source
The pole follower linearity.However due to 510 parasitic capacitance of node（Main includes 505 parasitic capacitance of NMOS tube, switch and capacitance
Parasitic capacitance）, 506 memory effect of switched-capacitor level shifter, the factors such as 505 channel-length modulation of NMOS tube shadow
It rings, the input buffer in Fig. 5 is still difficult to reach more than 14 linearities, it is difficult to meet and be higher than 14 analog-digital converter cores
Requirement of the electrocardio road to input buffer.
Invention content
It is an object of the invention to propose that a kind of high-gain, high bandwidth, high phase place nargin are applied to high-speed, high precision mould
Input buffer structure in number converter.
Input buffer structure proposed by the present invention applied in A/D converter with high speed and high precision uses operation and puts
The source follower or emitter follower with compensating electric capacity of big device auxiliary, are suitable for high speed and resolution ratio is more than or equal to 14
High-precision adc.The source follower with compensating electric capacity of operational amplifier auxiliary is as shown in fig. 6, operational amplifier is auxiliary
The emitter follower with compensating electric capacity helped is as shown in Figure 7.Analog-digital converter input signal is mostly fully differential signal in practice, because
This input buffer also should be difference form, easy for description, hereafter be illustrated by taking single ended input buffer as an example.
The source follower with compensating electric capacity of the operational amplifier auxiliary, including：Source electrode with compensating electric capacity follows
Device 610, auxiliary operation amplifier 606, level shift pipe 605；Input buffer passes through the sampling switch 608 in analog-digital converter
Drive the sampling capacitance 609 in analog-digital converter；Wherein：
Source follower 610 with compensating electric capacity follows NMOS tube 604, the tail that NMOS tube 601, NMOS tube 602 are constituted by source electrode
Current source and compensating electric capacity 607 form, input signal VinIt is moved to analog-digital converter sampling switch by NMOS tube 604
The output end V of front end, that is, input bufferout, VoutRelative to VinDC potential reduces but VoutSignal follows Vin；Big biasing
Electric current makes 604 mutual conductance of NMOS tube low, therefore input buffer has low output impedance, is capable of providing high driving ability；Compensation
607 capacitance of capacitance is suitable with analog-digital converter sampling capacitance capacitance, when analog-digital converter samples, has alternating current to pass through sampling
Switch 608 flows to analog-digital converter sampling capacitance 609, has at this time and flows to the comparable electric current of sampling capacitance electric current and flows through compensation electricity
Hold 607 so that source electrode follows the bias current of pipe 604 to be basically unchanged；
Input signal DC level is raised to V by operational amplifier1, V1V is dropped to using level shifter NMOS tube 6052,
Since there is level shift pipe the signal gain for being similar to 1, operational amplifier 606 to collectively form unit gain with level shift pipe
Negative-feedback；Unit gain feedback loop forces V1With V2Signal follow input Vin；Operational amplifier 606 and level shifter
The loop of composition makes the drain electrode that source electrode follows pipe 604 that grid signal be followed to change, and the input-for significantly improving input buffer is defeated
Cutting edge aligned degree.
The emitter follower with compensating electric capacity of operational amplifier auxiliary in Fig. 7, with above-mentioned source follower principle class
Seemingly.Specifically, including：Emitter follower 710, auxiliary operation amplifier 706, level shift pipe 705 with compensating electric capacity；It is defeated
Enter buffer and passes through the sampling capacitance 709 in the driving analog-digital converter of sampling switch 708 in analog-digital converter.Wherein：
For emitter follower 710 with compensating electric capacity by emitter follower NPN pipes 704, the tail that NPN pipes 701, NPN 702 are constituted is electric
Stream source and compensating electric capacity 707 form, input signal VinIt is moved to analog-digital converter sampling switch front end by NPN pipes 704（
That is the output end V of input bufferout）, VoutRelative to VinDC potential reduces but VoutSignal follows Vin.Big bias current
So that 704 mutual conductance of NPN pipes is low, therefore input buffer has low output impedance, is capable of providing high driving ability.Compensating electric capacity
707 capacitances are suitable with analog-digital converter sampling capacitance capacitance, when analog-digital converter samples, have alternating current to pass through sampling switch
708 flow to analog-digital converter sampling capacitance 709, have at this time and flow to the comparable electric current of sampling capacitance electric current and flow through compensating electric capacity
707 so that the bias current of emitter following pipe 704 is basically unchanged.
Input signal DC level is raised to V by operational amplifier1, V1It is dropped to using level shifter NPN pipes 705
V2, since there is level shift pipe the signal gain for being similar to 1, operational amplifier 706 to collectively form unit with level shift pipe
Gain negative feedback；Unit gain feedback loop forces V1With V2Signal follow input Vin；Operational amplifier 706 is moved with level
The loop that position device is constituted makes the drain electrode of emitter following pipe 704 that grid signal be followed to change, and significantly improves the defeated of input buffer
Enter-output linearity degree.
The present invention uses operational amplifier by input voltage VinIt is moved to V1, compared to switched-capacitor circuit, operation amplifier
Device is active device, is capable of the parasitic capacitance of drive output, therefore signal VinWith V1Between the linearity not by V1Place is parasitic
The decaying of capacitance.Compared to traditional structure, VinWith V1The linearity effectively improved.
Switched-capacitor level shifter itself has memory effect, in each sampling phase, switched-capacitor level shift
The level movement value of device is related with all input signals of sampling phase in the past, therefore the level of switched-capacitor level shifter
Movement value is influenced by input signal and this is influenced is time-varying, therefore realizes V using switched-capacitor level shifterinTo V1's
Movement is difficult to ensure the higher linearity.The present invention, instead of switched-capacitor circuit, is inherently eliminated using operational amplifier
Memory effect, compared to traditional structure, VinWith V1The linearity effectively improved.
V in traditional input buffer circuit1It is moved to V by level shift pipe 5052, by 505 raceway groove of level shift pipe
The influence of the effect of the length, V1With V2Between the linearity it is poor.The present invention input buffer in, level shift pipe 605 with
Operational amplifier 606 constitutes feedback control loop, and it is non-linear that feedback control loop inhibits level shift pipe to introduce.
In circuit shown in fig. 5, the sampling/conversion of switch in switched-capacitor level shifter 506 in analog-digital converter
Change on off operating mode when Phase-switching, analog-digital converter signal input network impedance is caused constantly to change, due to the parasitic electricity of encapsulation
The presence of sense, voltage when impedance variations in input network the ring of damped oscillation will occur, influence analog-digital converter sampling letter
Number quality.In the present invention, as shown in fig. 6, operational amplifier is continuous in timely by input signal VinIt is moved to V1, in modulus
Parallel operation is filled in sampling/conversion Phase-switching, it is almost unchanged that signal inputs network impedance, compared to traditional input buffer, by
Oscillation caused by package parasitic inductance reduces.
The performance of auxiliary operation amplifier in the present invention has a significant impact to the performance of entire input buffer, auxiliary fortune
Calculating amplifier should have the characteristics that：
（1）Common mode input range can cover the dynamic range of input buffer input signal：The input of operational amplifier is total
Mode voltage range is sufficiently large, and ensures input common mode voltage operational amplifier in the dynamic range of input buffer input signal
It can work normally；
（2）Output voltage swing covers the dynamic range of input buffer input signal：It is high that operational amplifier exports DC level
In input signal DC level, alternating voltage follows input signal, the output voltage swing of operational amplifier that must cover signal
Dynamic range just can guarantee that arrival source electrode follows the voltage swing of pipe drain electrode 612 that can cover defeated after level shift pipe 605
Enter signal swing；
（3）High-gain：Operational amplifier 606 together constitutes with unit gain negative-feedback with level shift pipe 605, operational amplifier
Gain is higher, and the error between operational amplifier in-phase input end, inverting input is smaller, and the linearity of input buffer is got over
It is high；
（4）High bandwidth：Operational amplifier 606 together constitutes with unit gain negative-feedback with level shift pipe 605, and closed-loop bandwidth is expanded
To close to operational amplifier open loop unity gain bandwidth.When to avoid frequency input signal high closed loop gain occur being decreased obviously into
And so that the input buffer linearity declines, the open loop unity gain bandwidth of auxiliary operation amplifier should be input signal bandwidth 10
Times or more；
（5）Enough phase margins：Phase margin deficiency is connecing the amplitude-versus-frequency curve for leading to unit gain feedback loop
There is spike at nearly closed-loop bandwidth so that the V in Fig. 6 when frequency input signal is close to closed-loop bandwidth2、V1Signal swing is more than defeated
Enter signal VinThe amplitude of oscillation, the input buffer linearity deteriorate.The phase margin of auxiliary operation amplifier should be not less than 60 degree.
Foregoing teachings substantially describe the feature and technological merit of the present invention, hereafter will be with 100MS/s sample rates, 14 moulds
It is example that the input buffer of number converter, which is applied, illustrates the thought of the present invention more apparently.Any ordinary skill
Personnel are it will be understood that realization phase of the present invention can be changed or be designed according to disclosed idea and specific embodiment
With the framework of purpose, such same framework is without departing from spirit and scope defined in appended claims of the present invention.
Description of the drawings
Fig. 1 is analog-digital converter sampling network schematic diagram.
Fig. 2 is to recalcitrate to influence schematic diagram to input signal when analog-digital converter samples.
Fig. 3 is the analog-digital converter sampling network schematic diagram with input buffer.
Fig. 4 is the source follower structure figure of conventional belt compensating electric capacity.
Fig. 5 is the source follower structure figure of conventional belt compensating electric capacity and level shift circuit.
Fig. 6 is the source follower structure figure with compensating electric capacity of operational amplifier auxiliary.
Fig. 7 is the emitter follower structure chart with compensating electric capacity of operational amplifier auxiliary.
Figure label：101 be the input signal source of analog-digital converter, and 102 be the parasitic inductance of chip package, and 103 be to adopt
Sample switchs, and 104 be the sampling capacitance of analog-digital converter core circuit；201 be the sequence diagram of analog-digital converter, and 202,203 are back
Input signal burr caused by kicking；301 be analog-digital converter input signal source, 302 be chip package parasitic inductance, 303
It is the sampling capacitance of analog-digital converter core circuit for sampling switch, 304,305 be input buffer；401 ~ 402 for source electrode with
With the tail current source of device, 403 be NMOS tube, and 404 follow NMOS tube for source electrode, and 405 be compensating electric capacity, and 406 be sampling switch,
407 be the sampling capacitance of analog-digital converter core circuit；501 ~ 502 be the tail current source of source follower, and 503 be NMOS tube,
504 follow NMOS tube for source electrode, and 505 be level shift NMOS tube, and 506 be switched-capacitor level shifter, and 507 be compensation electricity
Hold, 508 be sampling switch, and 509 be the sampling capacitance of analog-digital converter core circuit；601 ~ 602 is electric for the tail of source follower
Stream source, 603 be NMOS tube, and 604 follow NMOS tube for source electrode, and 605 be level shift NMOS tube, and 606 be auxiliary operational amplifier,
607 be compensating electric capacity, and 608 be sampling switch, and 609 be the sampling capacitance of analog-digital converter core circuit, and 610 follow for source electrode
Device, 611 be operational amplifier output node（Node voltage V1）, 612 be operational amplifier anti-phase input end node（Node voltage
V2）；701 ~ 702 be the tail current source of emitter follower, and 603 manage for NPN, and 604 be emitter following NPN pipes, and 605 move for level
Position NPN pipes, 606 be auxiliary operational amplifier, and 607 be compensating electric capacity, and 608 be sampling switch, and 609 be analog-digital converter core electricity
The sampling capacitance on road, 610 be emitter follower, and 611 be operational amplifier output node（Node voltage V1）, 612 put for operation
Big device anti-phase input end node（Node voltage V2）.
Specific implementation mode
The input buffer being applied in A/D converter with high speed and high precision proposed in the present invention is illustrated below.
It is worth noting that, input buffer provided by the invention can be there are many realization method of different index and performance, this
The input buffer of operational amplifier auxiliary in invention can also be there are many application scenarios.Below with the operation amplifier in Fig. 6
It is further illustrated the present invention for the source follower with compensating electric capacity of device auxiliary, is not limited to the present invention.
The source follower with compensating electric capacity of operational amplifier auxiliary, by the source follower 610 with compensating electric capacity, auxiliary
Operational amplifier 606, level shift pipe 605 is helped to form.Operational amplifier in-phase input end is connected to the input of input buffer
End, inverting input are connected to node 612, and operational amplifier output terminal is connected to node 611, are provided for level shift pipe 605
Direct current biasing.Level shift pipe 605 have be approximately 1 alternating voltage gain, therefore operational amplifier 606 and level shift pipe
605 component unit gain negative feedback loops, unit gain feedback loop force the voltage V of node 6111, node 612 voltage
V2AC compounent follow input signal VinAC compounent.V1DC level is higher than VinDC level, V2DC level is less than V1
DC level.Source follower uses larger bias current, provides enough driving capabilities.The present invention is buffered with traditional input
Device can have the ability for driving big sampling capacitance, and sampling capacitance and input signal source, package parasitic inductance can be isolated, this
Design has better input-output linear degree compared to traditional input buffer.
Input buffer provided by the invention, target are applied to 100MS/s sample rates, the analog-to-digital conversion of 14 bit resolutions
In device, realized using the source follower of operational amplifier auxiliary.Input signal bandwidth 50MHz, common-mode voltage 0.6V, input are poor
Sub-signal peak-to-peak value is -1V ~+1V, and the analog-digital converter core circuit in the example uses the supply voltage of 1.2V, input slow
Rush the supply voltage that device uses 2.5V.
In sampling phase, input signal input enters chip interior by chip package first, then proposes through the invention
Input buffer and sampling switch drive analog-digital converter sampling capacitance.
In the application example of the present invention, the analog-digital converter core circuit sampling time is 2.5ns, and single-ended sampling capacitance holds
Value is 5.6pF.For the driving capability for providing enough, it is 16mA to flow through source electrode to follow the electric current of pipe 604.In view of input signal is dynamic
State range, designs the common-mode input voltage range of the operational amplifier used as 0.7V ~ 1.7V, output voltage swing be 1.1V ~
2.1V.Operational amplifier open-loop gain is 60dB, it is contemplated that signal bandwidth 50MHz, therefore operational amplifier open loop unit increases
Beneficial bandwidth should be higher than that 500MHz, reach the operational amplifier of 2GHz in actual design using open loop unity gain bandwidth.Loop phase
Position nargin is about 70 degree.
The emitter follower with compensating electric capacity of operational amplifier auxiliary, as shown in fig. 7, with above-mentioned source follower principle
It is similar.
Although present disclosure and advantage disclose as above in detail, it should be noted that, the scope of the present invention is simultaneously
The specific embodiments such as method and step described in this description are not only restricted to, without departing from the spirit and scope of the present invention,
Any those of ordinary skill in the art all can make many deformations and modification according to disclosed content, these should also be regarded
For protection scope of the present invention.
Claims (1)
1. a kind of input buffer applied to the operational amplifier auxiliary in A/D converter with high speed and high precision, feature exists
In, the source follower with compensating electric capacity assisted using operational amplifier, or the band compensation electricity using operational amplifier auxiliary
The emitter follower of appearance；Wherein：
The source follower with compensating electric capacity of the operational amplifier auxiliary, including：Source follower with compensating electric capacity
610, auxiliary operation amplifier 606, level shift pipe 605；Input buffer is driven by the sampling switch 608 in analog-digital converter
Sampling capacitance 609 in dynamic model number converter；Wherein：
Source follower 610 with compensating electric capacity follows NMOS tube 604, the tail that NMOS tube 601, NMOS tube 602 are constituted by source electrode
Current source and compensating electric capacity 607 form, input signal VinIt is moved to analog-digital converter sampling switch by NMOS tube 604
The output end V of front end, that is, input bufferout, VoutRelative to VinDC potential reduces but VoutSignal follows Vin；Big biasing
Electric current makes 604 mutual conductance of NMOS tube low, therefore input buffer has low output impedance, is capable of providing high driving ability；Compensation
607 capacitance of capacitance is suitable with analog-digital converter sampling capacitance capacitance, when analog-digital converter samples, has alternating current to pass through sampling
Switch 608 flows to analog-digital converter sampling capacitance 609, has at this time and flows to the comparable electric current of sampling capacitance electric current and flows through compensation electricity
Hold 607 so that source electrode follows the bias current of pipe 604 to be basically unchanged；
Input signal DC level is raised to V by operational amplifier1, V1V is dropped to using level shifter NMOS tube 6052,
Since there is level shift pipe the signal gain for being similar to 1, operational amplifier 606 to collectively form unit gain with level shift pipe
Negative-feedback；Unit gain feedback loop forces V1With V2Signal follow input Vin；Operational amplifier 606 and level shifter
The loop of composition makes the drain electrode that source electrode follows pipe 604 that grid signal be followed to change, and the input-for significantly improving input buffer is defeated
Cutting edge aligned degree；
The emitter follower with compensating electric capacity of the operational amplifier auxiliary, including：Emitter follower with compensating electric capacity
710, auxiliary operation amplifier 706, level shift pipe 705；Input buffer is driven by the sampling switch 708 in analog-digital converter
Sampling capacitance 709 in dynamic model number converter；Wherein：
For emitter follower 710 with compensating electric capacity by emitter follower NPN pipes 704, the tail that NPN pipes 701, NPN 702 are constituted is electric
Stream source and compensating electric capacity 707 form, input signal VinIt is moved to analog-digital converter sampling switch front end i.e. by NPN pipes 704
The output end V of input bufferout, VoutRelative to VinDC potential reduces but VoutSignal follows Vin.Big bias current makes
It is low to obtain 704 mutual conductance of NPN pipes, therefore input buffer has low output impedance, is capable of providing high driving ability；Compensating electric capacity 707
Capacitance is suitable with analog-digital converter sampling capacitance capacitance, when analog-digital converter samples, has alternating current to pass through sampling switch 708
Analog-digital converter sampling capacitance 709 is flowed to, has at this time and flows to the comparable electric current of sampling capacitance electric current and flow through compensating electric capacity 707,
So that the bias current of emitter following pipe 704 is basically unchanged；
Input signal DC level is raised to V by operational amplifier1, V1V is dropped to using level shifter NPN pipes 7052, by
There is the signal gain for being similar to 1, operational amplifier 706 to collectively form unit gain with level shift pipe and bear in level shift pipe
Feedback；Unit gain feedback loop forces V1With V2Signal follow input Vin；Operational amplifier 706 and level shifter structure
At loop make the drain electrode of emitter following pipe 704 that grid signal be followed to change, significantly improve the input-output of input buffer
The linearity.
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| CN110221240A (en) * | 2019-06-28 | 2019-09-10 | 深圳市锐能微科技有限公司 | The detection circuit and electric energy computation chip of bleeder circuit parameter |
| CN110350876A (en) * | 2019-07-29 | 2019-10-18 | 深圳市锐能微科技有限公司 | Preamplifier, difference preamplifier and integrated circuit |
| CN111162790A (en) * | 2020-01-06 | 2020-05-15 | 西安电子科技大学 | Buffer based on inductance frequency expansion and sampling front-end circuit thereof |
| CN111294047A (en) * | 2020-03-11 | 2020-06-16 | 电子科技大学 | High-speed high-linearity input buffer |
| CN111431517A (en) * | 2020-05-07 | 2020-07-17 | 西安交通大学 | Ultra-high-speed bootstrap switch circuit with embedded input buffer |
| CN112104372A (en) * | 2020-08-25 | 2020-12-18 | 复旦大学 | Reference voltage buffer applied to high-speed high-precision analog-to-digital converter |
| CN112104365A (en) * | 2020-08-25 | 2020-12-18 | 复旦大学 | Residue amplifier applied to high-speed high-precision analog-to-digital converter |
| CN113300708A (en) * | 2021-04-09 | 2021-08-24 | 西安电子科技大学 | Broadband input signal buffer applied to ultra-high-speed analog-to-digital converter |
| CN113872602A (en) * | 2021-11-19 | 2021-12-31 | 中国电子科技集团公司第二十四研究所 | Front-end sampling circuit with buffer |
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| CN111162790A (en) * | 2020-01-06 | 2020-05-15 | 西安电子科技大学 | Buffer based on inductance frequency expansion and sampling front-end circuit thereof |
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| CN112104365A (en) * | 2020-08-25 | 2020-12-18 | 复旦大学 | Residue amplifier applied to high-speed high-precision analog-to-digital converter |
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| CN112104372B (en) * | 2020-08-25 | 2024-03-08 | 复旦大学 | Reference voltage buffer applied to high-speed high-precision analog-to-digital converter |
| CN113300708A (en) * | 2021-04-09 | 2021-08-24 | 西安电子科技大学 | Broadband input signal buffer applied to ultra-high-speed analog-to-digital converter |
| CN113300708B (en) * | 2021-04-09 | 2023-03-21 | 西安电子科技大学 | Broadband input signal buffer applied to ultra-high-speed analog-to-digital converter |
| CN113872602A (en) * | 2021-11-19 | 2021-12-31 | 中国电子科技集团公司第二十四研究所 | Front-end sampling circuit with buffer |
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Application publication date: 20180914 |