CN107967041A - A kind of power on configuration control method of more FPGA - Google Patents

A kind of power on configuration control method of more FPGA Download PDF

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Publication number
CN107967041A
CN107967041A CN201711265491.2A CN201711265491A CN107967041A CN 107967041 A CN107967041 A CN 107967041A CN 201711265491 A CN201711265491 A CN 201711265491A CN 107967041 A CN107967041 A CN 107967041A
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fpga
power
power supply
configuration
ldo
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CN107967041B (en
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余达
刘金国
周怀得
马庆军
陈佳豫
张博研
浦前帅
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/189—Power distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)

Abstract

A kind of power on configuration control method of more FPGA, it is related to a kind of power on configuration control method of more FPGA, existing more FPGA are solved when insufficient there are power supply during power on configuration, cause some or all of FPGA configuration failures, when the powerful power supply of use, the problems such as causing the wasting of resources, including FPGA power on configuration control systems, the FPGA power on configuration control system include DC/DC power supplys, external circuit, FPGA IO power supply LDO, FPGA kernel power supply LDO and RC delay circuits；The voltage of DC/DC power supplys output is powered to external circuit, the IO of FPGA and kernel respectively through transmission cable and each LDO；RC delay circuits are used to control the program_b of the IO power supply LDO output voltages of FPGA, kernel power supply LDO output voltages and FPGA to enable；By staggering for each FPGA load time, the size of DC/DC output total currents can be reduced, improves the utilization ratio of power supply.

Description

A kind of power on configuration control method of more FPGA
Technical field
The present invention relates to a kind of power on configuration control method of more FPGA, and in particular to a kind of based on the more of AEROSPACE APPLICATION The power on configuration control method of FPGA.
Background technology
FPGA is during power on configuration, it is necessary to larger configuration peak point current；If several FPGA are supplied using same power supply Electricity, and several FPGA interior carry out power on configuration at the same time, then the several times electric current for needing monolithic to configure, if power supply is defeated The electric current or undertension gone out, then there are some or all of FPGA configuration failures.A kind of solution is using high-power Power supply, and required power consumption is smaller after configuration successful, serious waste of resources.
The content of the invention
The present invention to solve existing more FPGA when insufficient there are power supply during power on configuration, cause part or Whole FPGA configuration failures, when using powerful power supply, the problems such as causing the wasting of resources, there is provided a kind of more FPGA's is upper Electric configuration control method.
A kind of power on configuration control method of more FPGA, including FPGA power on configuration control systems, the FPGA, which is powered on, to be matched somebody with somebody Put control system include DC/DC power supplys, external circuit, FPGA IO power supply LDO, FPGA kernel power supply LDO and RC delay electricity Road；The voltage of the DC/DC power supplys output is powered to external circuit, the IO of FPGA and kernel respectively through transmission cable and each LDO； The RC delay circuits are used to control the IO power supply LDO output voltages of FPGA, kernel power supply LDO output voltages and FPGA Program_b is enabled；During power on configuration control, using time-sharing power, specifically powering on configuration control method is：
Step 1: external circuit powers on；LDO, which is in, exports normal enabled state, and LDO is opened after DC/DC electric power output voltages Beginning output voltage；
Step 2: the IO power supply LDO outputs of FPGA are enabled；
IO powers LDO by the control of RC delay circuits, is opened when the voltage of RC delay circuits rises to threshold voltage IO power supplies LDO Beginning output voltage, the IO power supply LDO of multiple FPGA are enabled in identical delay time output, and the delay time is 0.02tconfig；T in formulaconfigFor the maximum power supply rise time of FPGA configurations；
Step 3: the kernel power supply LDO outputs of FPGA are enabled；
Kernel power supply LDO outputs are controlled by RC delay circuits, interior after the voltage of RC delay circuits rises to threshold voltage Core power supply LDO starts output voltage；
N piece FPGA are set, then the core power of n pieces FPGA enabled interval time is 0.6tconfig/n；That is first FPGA Configuration initial time be 0.2tconfig+0.6tconfigThe configuration initial time of/n, second FPGA are 0.2tconfig+ 0.6tconfigThe configuration initial time of × 2/n, n-th FPGA are 0.2tconfig+0.6tconfig×n/n；
Step 4: the program_b of FPGA enables startup configuration, program_b is enabled to be controlled by RC delay circuits, works as RC Program_ outputs are enabled after the voltage of delay circuit rises to threshold voltage；Specifically control method is：
The program_b of the Done controls FPGA of FPGA；
Set the configuration space time of each FPGA as the configuration deadline of monolithic；The Done connections of first FPGA The program_b of two FPGA, the program_b of the Done connection three pieces FPGA of second FPGA, until completing last The connection of piece FPGA；
The total length T of the setup time of multiple FPGAtotalFor：T in formulaiFor the configuration of i-th Time, TdelayFor the RC delay times of the program_b of first FPGA；
It is describedThe total length of l configuration datas in formula, m are the bit wide that data are read from PROM, fcclkFor the clock frequency read from PROM, Tdelay_iFor the non-time for reading data in configuration process.
Beneficial effects of the present invention：More FPGA power on configuration control methods of the present invention, one, reduce DC/DC moulds The quantity of block, while reduce the quantity of transmission cable and the quantity of connector；2nd, the timesharing to each several part power supply is passed through It is enabled, the surge current of DC/DC power supplys generation can be reduced；3rd, staggering by each FPGA load time, DC/DC can be reduced The size of total current is exported, improves the utilization ratio of power supply.
Brief description of the drawings
Fig. 1 is more serial power on configuration control system block diagrams of FPGA of the present invention；
More FPGA time-sharing powers that Fig. 2 is the present invention configure control system block diagram；
Fig. 3 is the RC delay circuit figures that the present invention combines comparator.
Embodiment
Embodiment one, illustrate present embodiment, a kind of power on configuration controlling party of more FPGA with reference to Fig. 1 to Fig. 3 Method, including FPGA power on configuration control systems, the FPGA power on configuration control system include DC/DC power supplys, transmission cable, outer Portion's circuit, multiple FPGA, the IO power supplies LDO of multiple FPGA, the kernel power supply LDO and RC delay circuits of multiple FPGA.DC/DC electricity The voltage of source output is powered to external circuit, the IO of FPGA and kernel respectively through transmission cable and each LDO.In power on configuration process In, each several part uses time-sharing power, and detailed process is：
(1) FPGA external circuits power on：The LDO of this part power supply, which is in, exports normal enabled state, starts to export in DC/DC Then LDO starts to export afterwards.
(2) the IO power supply LDO outputs of FPGA are enabled：The LDO outputs of this part power supply are controlled by RC delay circuits, when RC electricity The voltage on road rises to threshold voltage rear and starts to export, and the IO power supply LDO of multiple FPGA make in identical delay time output Can, the delay time is 0.02tconfig；T in formulaconfigFor the maximum power supply rise time of FPGA configurations；
(3) the kernel power supply LDO outputs of FPGA are enabled：The LDO outputs of this part power supply are controlled by RC delay circuits, work as RC The voltage of circuit rises to threshold voltage rear and starts to export.For n piece FPGA, then the core power of n pieces enables interval time For 0.6tconfig/n；The configuration initial time of i.e. first is 0.2tconfig+0.6tconfig/ n, second is 0.2tconfig+ 0.6tconfig× 2/n, n-th is 0.2tconfig+0.6tconfig×n/n.T in formulaconfigThe maximum power supply allowed for FPGA configurations Rise time.
(4) program_b of FPGA enables startup configuration：The output of this part is controlled by RC delay circuits, when RC circuits Voltage rises to threshold voltage rear and starts to enable.Specifically control method is：
The Done controls program_b of FPGA；As shown in Figure 1, the configuration space time of each FPGA is the configuration of monolithic Deadline；The program_b of the Done connections second of first, the program_b of the Done connection three pieces of second, And so on, it is to the last a piece of.
The total length T of multiple FPGA setup timetotalFor：T in formulaiFor the configuration of i-th when Between, TdelayFor the RC retardation ratio time of the program_b of first FPGA.L configuration datas in formula Total length, m be from PROM read data bit wide, fcclkFor the clock frequency read from PROM, Tdelay_iFor configuration process In it is non-read data time.
In present embodiment, in the program_b of FPGA is enabled and started configuration process, program_b outputs are prolonged by RC When circuit control, program_b side starts to enable after the voltage of RC circuits rises to threshold voltage, its control method can be with Realized using following manner：
With reference to Fig. 2, it is delayed using the RC for combining comparator：It is delayed by the RC for combining comparator, can control different FPGA The IO power supplies enabled time for starting to be changed into high level to corresponding program_b and start configuration；With reference to Fig. 3, can not only lead to Cross setting RC parameters and carry out delay adjustment, by bleeder circuit threshold level can also be set to carry out delay adjustment.
The power supplies of IO described in present embodiment are enabled start to corresponding program_b be changed into high level start configuration when Betweenτ is the charging interval coefficient of the RC circuits of I O power supply power supply in formula, and k is the bleeder circuit of I O power supply power supply Partial pressure coefficient, that is, the ratio of threshold voltage and supply voltage, 0 ＜ k ＜ 1.Multiple FPGA configuration depends on total time The setup time of most long that piece FPGA of configuration.
The output voltage requirement of DC/DC power supplys described in present embodiment is not less than：IO supply voltages+the LDO's of FPGA The peak point current of the output cord of resistance × configuration process of pressure difference+output cord.
The output current of the DC/DC power supplys is not less than the 120% of configuration process peak point current.
FPGA in present embodiment is the FPGA such as XQ2V3000 of the series of virtex 2；LDO uses MSK5101；DC/DC Power supply uses the DC/DC modules of VPT companies.

Claims (4)

1. a kind of power on configuration control method of more FPGA, it is characterized in that；Including FPGA power on configuration control systems, the FPGA Power on configuration control system include DC/DC power supplys, external circuit, FPGA IO power supply LDO, FPGA kernel power supply LDO and RC Delay circuit；
The voltage of the DC/DC power supplys output is supplied to external circuit, the IO of FPGA and kernel respectively through transmission cable and each LDO Electricity；The RC delay circuits are used for IO power supply LDO output voltages, kernel power supply LDO output voltages and the FPGA for controlling FPGA Program_b enable；During power on configuration control, using time-sharing power, specifically powering on configuration control method is：
Step 1: external circuit powers on；LDO, which is in, exports normal enabled state, and LDO starts defeated after DC/DC electric power output voltages Go out voltage；
Step 2: the IO power supply LDO outputs of FPGA are enabled；
IO power LDO by RC delay circuits control, when the voltage of RC delay circuits rise to threshold voltage IO power supply LDO start it is defeated Go out voltage, the IO power supply LDO of multiple FPGA are enabled in identical delay time output, and the delay time is 0.02tconfig；Formula Middle tconfigFor the maximum power supply rise time of FPGA configurations；
Step 3: the kernel power supply LDO outputs of FPGA are enabled；
Kernel power supply LDO outputs are controlled by RC delay circuits, and kernel supplies after the voltage of RC delay circuits rises to threshold voltage Electric LDO starts output voltage；
N piece FPGA are set, then the core power of n pieces FPGA enabled interval time is 0.6tconfig/n；That is first FPGA's matches somebody with somebody It is 0.2t to put initial timeconfig+0.6tconfigThe configuration initial time of/n, second FPGA are 0.2tconfig+0.6tconfig× The configuration initial time of 2/n, n-th FPGA are 0.2tconfig+0.6tconfig×n/n；
Step 4: the program_b of FPGA enables startup configuration, program_b is enabled to be controlled by RC delay circuits, when RC is delayed Program_ outputs are enabled after the voltage of circuit rises to threshold voltage；Specifically control method is：
The program_b of the Done controls FPGA of FPGA；
Set the configuration space time of each FPGA as the configuration deadline of monolithic；The Done connections second of first FPGA The program_b of FPGA, the program_b of the Done connection three pieces FPGA of second FPGA, it is last a piece of until completing The connection of FPGA；
The total length T of the setup time of multiple FPGAtotalFor：T in formulaiFor the setup time of i-th, TdelayFor the RC delay times of the program_b of first FPGA；
It is describedThe total length of l configuration datas in formula, m be from PROM read data bit wide, fcclk For the clock frequency read from PROM, Tdelay_iFor the non-time for reading data in configuration process.
A kind of 2. power on configuration control method of more FPGA according to claim 1, it is characterised in that；In step 4, The program_b of FPGA is enabled to be controlled by RC delay circuits, after the voltage of RC delay circuits rises to threshold voltage Program_ is enabled；Another control method is further included, is specially：
Set independent between each FPGA, the program_b of FPGA is carried out using the RC delay circuits respectively in connection with comparator Control：By combining the RC delay circuits of comparator, control the IO power supplies of different FPGA are enabled to start to corresponding FPGA's Program_b is changed into the time that high level starts configuration.
A kind of 3. power on configuration control method of more FPGA according to claim 2, it is characterised in that；The IO power supplies make The program_b pins that can start to corresponding FPGA are changed into the time that high level starts configurationτ is IO in formula The charging interval coefficient of the RC circuits of power supply power supply, k are the partial pressure coefficient of the bleeder circuit of IO power supplies, and the scope of the k is：0 ＜ k ＜ 1.
A kind of 4. power on configuration control method of more FPGA according to claim 1, it is characterised in that；The DC/DC electricity The pressure difference+resistance of transmission cable × of IO power supply LDO output voltage+LDO of the output voltage requirement in source more than or equal to FPGA is matched somebody with somebody Put the peak point current on the transmission cable of process.
CN201711265491.2A 2017-12-05 2017-12-05 Multi-FPGA power-on configuration control method Active CN107967041B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110196781A (en) * 2019-06-11 2019-09-03 中国科学院长春光学精密机械与物理研究所 Allocation problem inspection method is loaded based on a FPGA for load
CN110221935A (en) * 2019-06-11 2019-09-10 中国科学院长春光学精密机械与物理研究所 FPGA based on LDO loads allocation problem inspection method

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CN102495568A (en) * 2011-12-05 2012-06-13 南京大学 Development board of network multi-core processor on test board based on four field programmable gate arrays (FPGA)
US9425794B1 (en) * 2014-07-11 2016-08-23 Google Inc. Testing system for power delivery network
WO2016201607A1 (en) * 2015-06-15 2016-12-22 京微雅格（北京）科技有限公司 Chip power supply method and chip
CN106919734A (en) * 2017-01-10 2017-07-04 北京中科睿芯科技有限公司 Electric method of automatic configuration on a kind of many FPGA

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102495568A (en) * 2011-12-05 2012-06-13 南京大学 Development board of network multi-core processor on test board based on four field programmable gate arrays (FPGA)
US9425794B1 (en) * 2014-07-11 2016-08-23 Google Inc. Testing system for power delivery network
WO2016201607A1 (en) * 2015-06-15 2016-12-22 京微雅格（北京）科技有限公司 Chip power supply method and chip
CN106919734A (en) * 2017-01-10 2017-07-04 北京中科睿芯科技有限公司 Electric method of automatic configuration on a kind of many FPGA

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110196781A (en) * 2019-06-11 2019-09-03 中国科学院长春光学精密机械与物理研究所 Allocation problem inspection method is loaded based on a FPGA for load
CN110221935A (en) * 2019-06-11 2019-09-10 中国科学院长春光学精密机械与物理研究所 FPGA based on LDO loads allocation problem inspection method
CN110196781B (en) * 2019-06-11 2021-04-02 中国科学院长春光学精密机械与物理研究所 FPGA loading configuration problem checking method based on point load

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