CN110139309B - Power detection and regulation system, power detection method and power regulation method - Google Patents
Power detection and regulation system, power detection method and power regulation method Download PDFInfo
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- CN110139309B CN110139309B CN201910354874.XA CN201910354874A CN110139309B CN 110139309 B CN110139309 B CN 110139309B CN 201910354874 A CN201910354874 A CN 201910354874A CN 110139309 B CN110139309 B CN 110139309B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/04—TPC
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Abstract
The embodiment of the invention provides a power detection and regulation system, a power detection method and a power regulation method, wherein the system comprises: the system comprises a programmable gate array FPGA, a first radio frequency transceiver, a second radio frequency transceiver, a power divider, a power amplifier PA, a duplexer, an attenuator and an antenna; the FPGA is respectively connected with the first radio frequency transceiver and the second radio frequency transceiver; the transmitting end of the first radio frequency transceiver is connected with the input end of the power divider; the output end of the power divider is respectively connected with the input end of the PA and the input end of the attenuator; the output end of the attenuator is connected with the second radio frequency transceiver; the output end of the PA is connected with the input end of the duplexer, and the duplexer is connected with the antenna. The embodiment of the invention provides a power detection and adjustment system, a power detection method and a power adjustment method, which are based on a forward link and a reverse link formed by double radio frequency transceivers and realize real-time detection and real-time adjustment of power through data real-time operation of an FPGA.
Description
Technical Field
The embodiment of the invention relates to the technical field of wireless communication, in particular to a power detection and regulation system, a power detection method and a power regulation method.
Background
There are many functions in a system of a mobile wireless communication device such as a repeater that require detection of output power, such as ALC (Auto Level Control), standing-wave ratio detection, and the like. The accurate power detection and power control are key technical indexes of the repeater system, and not only are the efficient and reliable work of the system ensured, but also the problem of quick positioning when the system fails is facilitated, and the system development and maintenance are facilitated.
The existing output power detection is mainly used for detecting the power of a digital signal, is completed before the digital signal is processed, cannot detect the power of the signal after DA, and cannot adjust and control the power of the digital signal in real time.
Therefore, a new power detection and regulation system is needed to solve the above problems.
Disclosure of Invention
In order to solve the above problems, embodiments of the present invention provide a power detection and regulation system, a power detection method, and a power regulation method that overcome the above problems or at least partially solve the above problems.
In a first aspect, an embodiment of the present invention provides a power detection and adjustment system, including:
the system comprises a programmable gate array FPGA, a first radio frequency transceiver, a second radio frequency transceiver, a power divider, a power amplifier PA, a duplexer, an attenuator and an antenna;
the FPGA is respectively connected with the first radio frequency transceiver and the second radio frequency transceiver;
the transmitting end of the first radio frequency transceiver is connected with the input end of the power divider;
the output end of the power divider is respectively connected with the input end of the PA and the input end of the attenuator;
the output end of the attenuator is connected with the second radio frequency transceiver;
the output end of the PA is connected with the input end of the duplexer, and the duplexer is connected with the antenna.
A second aspect of the present invention provides a power detection method, including:
obtaining forward link gain GFReverse link gain of GBThe parallel digital signal is obtained by digitizing the output signal of the attenuator by the second radio frequency transceiver;
processing and operating the parallel digital signals to obtain statistical real-time power PTrans form；
Forward link gain GFReverse link gain of GBAnd counting the real-time power PInverse directionSumming to obtain real-time output power PFruit of Chinese wolfberry。
In a third aspect, an embodiment of the present invention provides a power adjustment method, including:
obtaining target output power P and real-time output power PFruit of Chinese wolfberry；
Calculating the target output power P and the real-time output power PFruit of Chinese wolfberryReal-time difference value P betweenDifference between；
According to the real-time difference value PDifference (D)Determining the first radio frequencyDegree of adjustment of the transceiver downstream attenuation value.
The embodiment of the invention provides a power detection and adjustment system, a power detection method and a power adjustment method, which are based on a forward link and a reverse link formed by double radio frequency transceivers and realize real-time detection and real-time adjustment of power through data real-time operation of an FPGA.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a power detection and regulation system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of basic components of a near-remote end of a fiber-optic digital repeater according to an embodiment of the present invention;
FIG. 3 is a flow chart of a power detection method according to an embodiment of the present invention;
FIG. 4 is a flow chart of a power adjustment method according to an embodiment of the present invention;
fig. 5 is a schematic diagram of real-time adjustment of downlink output power according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments, but not all embodiments, of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a power detection and regulation system according to an embodiment of the present invention, as shown in fig. 1, including:
the system comprises a programmable gate array FPGA1, a first radio frequency transceiver 2, a second radio frequency transceiver 3, a power divider 4, a power amplifier PA5, a duplexer 6, an attenuator 7 and an antenna 8;
the FPGA1 is connected to the first radio frequency transceiver 2 and the second radio frequency transceiver 3 respectively;
the transmitting end of the first radio frequency transceiver 2 is connected with the input end of the power divider 4;
the output end of the power divider 4 is connected to the input end of the PA5 and the input end of the attenuator 7 respectively;
the output end of the attenuator 7 is connected with the second radio frequency transceiver 3;
the output end of the PA5 is connected with the input end of the duplexer 6, and the duplexer 6 is connected with the antenna 8.
It should be noted that the power detection and adjustment system provided in the embodiment of the present invention is applied to automatic power detection and adjustment in a mobile wireless communication device system, an optical fiber digital repeater is taken as an example in the embodiment of the present invention, and other mobile wireless communication device systems refer to the application of the optical fiber digital repeater, which is not described again in the embodiment of the present invention.
Fig. 2 is a schematic diagram of basic components of a near-far-end unit of an optical fiber digital repeater according to an embodiment of the present invention, as shown in fig. 2, in a downlink, the near-end unit couples a base station signal through a radio frequency port, the coupled signal passes through a duplexer, a frequency converter, an ADC, and an optical module after digital down-conversion performs electro-optical conversion, and is transmitted to the far-end unit through an optical fiber, the optical module of the far-end unit performs photoelectric conversion, and after digital up-conversion, the DAC, and the frequency converter, the signal enters a radio frequency power amplifier for amplification, and the amplified radio frequency signal is subjected to radiation coverage through an antenna; for the uplink, the same processing is performed as for the downlink.
It will be appreciated that fig. 1, which is a power detection and regulation system of the remote unit arrangement shown in the embodiment of the present invention, enables real-time detection and regulation of power.
Specifically, in the embodiment of the present invention, the FPGA1 sends a baseband signal to the first radio frequency transceiver 2, the first radio frequency transceiver 2 performs frame decoding on the baseband signal to complete digital up-conversion, so as to convert the baseband signal into a radio frequency analog signal, then the first radio frequency transceiver 2 sends the radio frequency analog signal to the power divider 4 from the sending end TX, and the signal power dividing function of the power divider 4 divides the radio frequency analog signal into two paths of radio frequency signals, so as to form a forward link and a reverse link in the embodiment of the present invention.
The forward link is transmitted to PA5 by power divider 4, amplified by PA5 and transmitted to duplexer 6, duplexer 6 is connected to antenna 8, and the forward link is completed by antenna radiation coverage. The reverse link is transmitted to the attenuator 7 by the power divider 4, the attenuator 7 attenuates the power and transmits the attenuated power to the second rf transceiver 2, and the second rf transceiver digitizes the data and transmits the digitized data to the FPGA1, thereby completing the transmission of the reverse link.
It can be understood that the power detection and adjustment system designed in the embodiment of the present invention provides a forward link and a reverse link formed by dual radio frequency transceivers, which are capable of acquiring the forward link gain G in real time during signal transmissionFReverse link gain GBAnd the statistic real-time power is PInverse directionThen summing the three to obtain the real-time output power PFruit of Chinese wolfberryThen P isFruit of Chinese wolfberry＝PInverse direction+GB+GF。
Furthermore, the embodiment of the invention can obtain the real-time output power PFruit of Chinese wolfberryThe target output power and the real-time output power can be calculated and obtained by real-time adjustment through the FPGA1, specifically, the target output power is set to be PFruit of Chinese wolfberryReal-time difference value P ofDifference (D)The FPGA1 can then calculate the real-time difference value PDifference betweenAnd controlling the downlink attenuation value of the first radio frequency transceiver 2 to complete real-time adjustment.
The power detection and adjustment system provided by the embodiment of the invention is based on the forward link and the reverse link formed by the double radio frequency transceivers, and realizes real-time detection and real-time adjustment of power through the data real-time operation of the FPGA.
On the basis of the above embodiment, the power detection and regulation system further includes:
a low noise amplifier LNA9, an input of the LNA9 being connected to an output of the duplexer; the output end of the LNA9 is connected to the receiving end of the first radio frequency transceiver.
As shown in fig. 1, it can be understood that the power detection and adjustment system provided by the embodiment of the present invention has downlink transmission and uplink transmission at the same time. Preferably, in uplink transmission, the embodiment of the present invention employs an LNA9, and an input terminal of the LNA9 is connected to an output terminal of the duplexer; the output end of the LNA9 is connected to the receiving end of the first rf transceiver, and the LNA is an amplifier with a very low noise figure, which can reduce noise interference as much as possible.
On the basis of the foregoing embodiment, the power divider is an active one-to-two power divider, and the power divider divides the downlink radio frequency signal transmitted by the first radio frequency transceiver into a forward link radio frequency signal and a reverse link radio frequency signal.
As can be seen from the above description, the embodiments of the present invention provide a power divider for dividing a signal into a forward link signal and a reverse link signal.
Preferably, the power divider adopted in the embodiment of the present invention is an active one-to-two power divider, and the one-to-two power divider is adopted because only two paths of signals need to be divided in the embodiment of the present invention. The active power divider has the advantages that the active power divider can have gain and high isolation, and the passive power divider is too large in loss and is not suitable for long-term use.
On the basis of the above embodiment, the attenuator is a fixed value attenuator.
As can be seen from the above description, the embodiment of the present invention needs to perform power attenuation on the reverse link signal delivered by the power divider. The device used in attenuation is an attenuator, and preferably, the attenuator used in the embodiment of the present invention is a fixed value attenuator, which can attenuate a fixed gain dB.
On the basis of the above embodiment, the FPGA is configured to control the downlink attenuation value of the first radio frequency transceiver through an SPI bus.
As can be seen from the above description, the embodiment of the present invention provides that the FPGA controls the downlink attenuation value of the first radio frequency transceiver to complete real-time adjustment. Specifically, the control is performed through an SPI bus in the adjusting process. It can be understood that the SPI bus is a synchronous serial port for performing communication between the processing control unit, i.e., the FPGA in the embodiment of the present invention, and the peripheral device, i.e., the first radio frequency transceiver in the embodiment of the present invention, and then the FPGA can send a control command to control the downlink attenuation of the first radio frequency transceiver through the SPI bus.
Fig. 3 is a schematic flow chart of a power detection method according to an embodiment of the present invention, as shown in fig. 3, including:
301. obtaining forward link gain GFReverse link gain of GBThe parallel digital signal is obtained by digitizing the output signal of the attenuator by the second radio frequency transceiver;
302. processing and operating the parallel digital signals to obtain statistical real-time power PInverse direction；
303. Forward link gain GFReverse link gain of GBAnd counting the real-time power PInverse directionSumming to obtain real-time output power PFruit of Chinese wolfberry。
It should be noted that the execution subject of the embodiment of the present invention is an FPGA, and the method provided by the embodiment of the present invention is applied to real-time power detection of a mobile wireless communication device.
Specifically, in step 301, the FPGA can obtain the forward link gain G generated in the power detection and adjustment systemFReverse link gain of GBAnd the parallel digital signal is a parallel digital signal obtained by converting the S signal into a digital signal after the receiving end of the second radio frequency transceiver receives the signal S output by the attenuator.
Further, in step 302, the FPGA processes and calculates the parallel digital signal to obtain the statistical real-time power P of the systemInverse direction。
Finally, in step 303, the real-time power P is countedTrans formForward link gain GFReverse link gain of GBSumming to obtain final real-time output power PFruit of Chinese wolfberryI.e. PFruit of Chinese wolfberry＝PInverse direction+GB+GF。
Fig. 4 is a schematic flow chart of a power adjustment method according to an embodiment of the present invention, as shown in fig. 4, including:
401. obtaining target output power P and real-time output power PFruit of Chinese wolfberry；
402. Calculating the target output power P and the real-time output power PFruit of Chinese wolfberryReal-time difference value P betweenDifference (D)；
403. According to the real-time difference value PDifference (D)Determining the degree of adjustment of the downlink attenuation value of the first radio frequency transceiver.
It should be noted that the execution subject of the embodiment of the present invention is an FPGA, and the application environment of the method provided by the embodiment of the present invention is real-time power adjustment for a mobile wireless communication device.
Fig. 5 is a schematic diagram of real-time adjustment of downlink output power according to an embodiment of the present invention, and with reference to fig. 5, in step 401, the FPGA first obtains a target output power P and a real-time output power PFruit of Chinese wolfberryThe target output power P refers to the output power P preset by the mobile wireless communication equipment and the real-time output power PFruit of Chinese wolfberryIs obtained by FPGA real-time detection, preferably, P can be adoptedFruit of Chinese wolfberry＝PInverse direction+GB+GFIs calculated to obtain, wherein, PInverse directionFor counting real-time power, GFFor forward link gain, GBFor reverse link gain, PTrans formThe calculation of (c) is shown with reference to fig. 5.
Further, in step 402, the target output power P and the real-time output power P are usedFruit of Chinese wolfberryThe real-time power difference value P of each moment can be calculatedDifference (D)。
Finally, in step 403, the real-time power difference P is determined according to the real-time power differenceDifference (D)And the FPGA can determine the adjustment degree of the downlink attenuation value of the first radio frequency transceiver, namely the adjustment amplitude required to be carried out, so that real-time adjustment is completed.
On the basis of the above embodiment, the method further comprises:
and controlling the first radio frequency transceiver to regulate power through the SPI bus according to the regulation degree of the downlink attenuation value of the first radio frequency transceiver.
As can be seen from the above description, in the embodiments of the present invention, the adjustment degree of the downlink attenuation value of the first rf transceiver is determined, and then the first rf transceiver is controlled to perform power adjustment. Specifically, the FPGA controls the downlink attenuation value of the first rf transceiver through the SPI bus to complete the real-time adjustment of the power.
On the basis of the above embodiment, the adjustment precision of the adjustment degree of the downlink attenuation value of the first radio frequency transceiver is 0.25 dB.
Preferably, in the embodiment of the present invention, the adjustment precision of the FPGA on the downlink attenuation value of the first radio frequency transceiver is 0.25 dB.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to each embodiment or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (7)
1. A power detection regulation system, comprising:
the system comprises a programmable gate array FPGA, a first radio frequency transceiver, a second radio frequency transceiver, a power divider, a power amplifier PA, a duplexer, an attenuator and an antenna;
the FPGA is respectively connected with the first radio frequency transceiver and the second radio frequency transceiver;
the transmitting end of the first radio frequency transceiver is connected with the input end of the power divider;
the output end of the power divider is respectively connected with the input end of the PA and the input end of the attenuator;
the output end of the attenuator is connected with the second radio frequency transceiver;
the output end of the PA is connected with the input end of the duplexer, and the duplexer is connected with the antenna;
the power detection regulation system further comprises:
the input end of the LNA is connected with the output end of the duplexer; the output end of the LNA is connected with the receiving end of the first radio frequency transceiver;
the power divider is an active one-to-two power divider, and divides the downlink radio-frequency signals transmitted by the first radio-frequency transceiver into forward link radio-frequency signals and reverse link radio-frequency signals.
2. The power detection regulation system of claim 1,
the attenuator is a fixed value attenuator.
3. The power detection regulation system of claim 1,
the FPGA is used for controlling the downlink attenuation value of the first radio frequency transceiver through an SPI bus.
4. A power detection method implemented by the power detection regulation system according to any one of claims 1 to 3, comprising:
obtaining forward link gain GFIn the reverse directionLink gain of GBThe parallel digital signal is obtained by digitizing the output signal of the attenuator by the second radio frequency transceiver;
processing and operating the parallel digital signals to obtain statistical real-time power PInverse direction；
Forward link gain GFReverse link gain of GBAnd counting the real-time power PInverse directionSumming to obtain real-time output power PFruit of Chinese wolfberry。
5. A power conditioning method implemented by the power detection conditioning system according to any of claims 1-3, comprising:
obtaining target output power P and real-time output power PFruit of Chinese wolfberry；
Calculating the target output power P and the real-time output power PFruit of Chinese wolfberryReal-time difference value P betweenDifference (D)；
According to the real-time difference value PDifference (D)Determining the degree of adjustment of the downlink attenuation value of the first radio frequency transceiver.
6. The method of claim 5, further comprising:
and controlling the first radio frequency transceiver to carry out power regulation through the SPI bus according to the regulation degree of the downlink attenuation value of the first radio frequency transceiver.
7. The method of claim 6, wherein the adjustment accuracy of the adjustment degree of the first RF transceiver downstream attenuation value is 0.25 dB.
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| CN113809993B (en) * | 2021-11-18 | 2022-03-04 | 成都市卫莱科技有限公司 | Working signal monitoring control device, system and method for power amplifier |
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