CN110139309A - A kind of power detection regulating system, power detecting method and power regulating method - Google Patents
A kind of power detection regulating system, power detecting method and power regulating method Download PDFInfo
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- CN110139309A CN110139309A CN201910354874.XA CN201910354874A CN110139309A CN 110139309 A CN110139309 A CN 110139309A CN 201910354874 A CN201910354874 A CN 201910354874A CN 110139309 A CN110139309 A CN 110139309A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/08—Testing, supervising or monitoring using real traffic
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/04—TPC
- H04W52/18—TPC being performed according to specific parameters
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Abstract
The embodiment of the invention provides a kind of power detection regulating system, power detecting method and power regulating method, system includes: programmable gate array FPGA, the first RF transceiver, the second RF transceiver, power splitter, power amplifier PA, duplexer, attenuator and antenna；FPGA is separately connected the first RF transceiver and the second RF transceiver；The input terminal of the transmitting terminal connection power splitter of first RF transceiver；The output end of power splitter is connect with the input terminal of the input terminal of PA and attenuator respectively；The output end of attenuator connects the second RF transceiver；The input terminal of the output end connection duplexer of PA, duplexer connect antenna.A kind of power detection regulating system, power detecting method and power regulating method provided in an embodiment of the present invention, the forward link and reverse link constituted based on Double RF transceiver, and pass through the data real-time operation of FPGA, realize real-time detection and adjusting in real time to power.
Description
Technical field
The present embodiments relate to wireless communication technology field more particularly to a kind of power detection regulating systems, power inspection
Survey method and power regulating method.
Background technique
There are many functions to require detection output power, such as ALC in mobile radio communication apparatus such as repeater system
(Auto Level Control, auto level control), standing-wave ratio detection etc..Accurate power detection and power control are directly to put
The key technical index for system of standing, accurate power detection and power control, which not only facilitate, ensures the reliable work of system high efficiency
Make, it helps the quick positioning question when system breaks down, help system exploitation and maintenance.
Existing output power detection mainly detection digital power signal, is completed before Digital Signal Processing, can not
It detects the signal power after DA, can not also adjust the power after control digital signal in real time.
Therefore, the new power detection regulating system of one kind is needed now to solve the above problems.
Summary of the invention
To solve the above-mentioned problems, the embodiment of the present invention provides one kind and overcomes the above problem or at least be partially solved
State a kind of power detection regulating system, power detecting method and the power regulating method of problem.
The first aspect embodiment of the present invention provides a kind of power detection regulating system, comprising:
It is programmable gate array FPGA, the first RF transceiver, the second RF transceiver, power splitter, power amplifier PA, double
Work device, attenuator and antenna；
The FPGA is separately connected first RF transceiver and second RF transceiver；
The transmitting terminal of first RF transceiver connects the input terminal of the power splitter；
The output end of the power splitter is connect with the input terminal of the input terminal of the PA and the attenuator respectively；
The output end of the attenuator connects second RF transceiver；
The output end of the PA connects the input terminal of the duplexer, and the duplexer connects the antenna.
The embodiment of the invention provides power detecting methods for second aspect, comprising:
Obtain forward link gain GF, reverse link gain GBAnd parallel digital signal, the parallel digital signal are
What the second RF transceiver was digitized according to attenuator output signal；
Processing operation is carried out to the parallel digital signal, obtains statistics realtime power PInstead；
By forward link gain GF, reverse link gain GBAnd statistics realtime power PInsteadSummation obtains real-time output work
Rate PIt is real。
The embodiment of the invention provides power regulating methods for the third aspect, comprising:
Obtain target output P and real-time output power PIt is real；
Calculate the target output P and real-time output power PIt is realBetween real-time difference PDifference；
According to the real-time difference PDifferenceSize, determine the degree of regulation of the first RF transceiver downstream attenuation values.
A kind of power detection regulating system, power detecting method and power regulating method provided in an embodiment of the present invention, base
In forward link and reverse link that Double RF transceiver is constituted, and pass through the data real-time operation of FPGA, realizes to power
Real-time detection and in real time adjusting.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of power detection regulating system structural schematic diagram provided in an embodiment of the present invention；
Fig. 2 is near and remote machine basic element of character schematic diagram in optical fiber and digital repeater provided in an embodiment of the present invention；
Fig. 3 is power detecting method flow diagram provided in an embodiment of the present invention；
Fig. 4 is power regulating method flow diagram provided in an embodiment of the present invention；
Fig. 5 is that down output power provided in an embodiment of the present invention adjusts schematic diagram in real time.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical solution in the embodiment of the present invention is explicitly described, it is clear that described embodiment is the present invention
A part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not having
Every other embodiment obtained under the premise of creative work is made, shall fall within the protection scope of the present invention.
Fig. 1 is a kind of power detection regulating system structural schematic diagram provided in an embodiment of the present invention, as shown in Figure 1, comprising:
Programmable gate array FPGA 1, the first RF transceiver 2, the second RF transceiver 3, power splitter 4, power amplifier
PA5, duplexer 6, attenuator 7 and antenna 8；
The FPGA1 is separately connected first RF transceiver 2 and second RF transceiver 3；
The transmitting terminal of first RF transceiver 2 connects the input terminal of the power splitter 4；
The output end of the power splitter 4 is connect with the input terminal of the input terminal of the PA5 and the attenuator 7 respectively；
The output end of the attenuator 7 connects second RF transceiver 3；
The output end of the PA5 connects the input terminal of the duplexer 6, and the duplexer 6 connects the antenna 8.
It should be noted that power detection regulating system application environment provided in an embodiment of the present invention is mobile radio telecommunications
Power in device systems is detected and is adjusted automatically, and the embodiment of the present invention is illustrated by taking optical fiber and digital repeater as an example, other
The application of mobile radio communication apparatus system section reference fiber digital high-frequency amplification station, the embodiment of the present invention repeat no more this.
Fig. 2 is near and remote machine basic element of character schematic diagram in optical fiber and digital repeater provided in an embodiment of the present invention, such as Fig. 2 institute
Show, in the downlink, near-end machine couples base station signal by radio frequency mouth, and signal after coupling is through duplexer, frequency converter, ADC,
Optical module carries out electro-optic conversion after Digital Down Convert, passes to remote termination by optical fiber, and the optical module of remote termination carries out photoelectric conversion,
After Digital Up Convert, DAC, frequency converter, amplified into radio-frequency power amplifier, amplified radiofrequency signal by antenna into
Row radiation covering；For uplink, identical processing is carried out with downlink.
It is understood that the power detection regulating system of the arrangement of remote termination shown in Fig. 1, that is, embodiment of the present invention, passes through
The power detection regulating system can be realized the real-time detection and adjusting of power.
Specifically, baseband signal is sent to the first RF transceiver 2 by FPGA1 in the embodiment of the present invention, the first radio frequency is received
It sends out device 2 and frame decoding is carried out to the baseband signal, complete Digital Up Convert, so that radio frequency analog signal is converted by the baseband signal,
Then the radio frequency analog signal is transmitted to power splitter 4 from transmitting terminal TX by the first RF transceiver 2, by the signal of power splitter 4
The radio frequency analog signal is divided into two-way radiofrequency signal by function point function, constitutes forward link and reverse strand in the embodiment of the present invention
Road.
Forward link is transmitted to PA5 by power splitter 4, and duplexer 6 is transmitted to after PA5 is amplified, and duplexer 6 connects day
Line 8 is covered the transmitting for completing forward link by aerial radiation.Reverse link is transmitted to attenuator 7 by power splitter 4, by attenuator 7
Be sent to the second RF transceiver 2 after carrying out power attenuation, the second RF transceiver will return after data digitalization processing to
FPGA1 completes the transmitting of reverse link.
It is understood that the Double RF transceiver that the power detection regulating system of design of the embodiment of the present invention provides is constituted
Forward link and reverse link, can in signals transmission, in real time obtain forward link gain GF, reverse link gain
GBIt is P with statistics realtime powerInstead, then three, which is summed, can know real-time output power for PIt is real, then PIt is real=PInstead+GB+GF。
Further, the embodiment of the present invention can be according to obtained real-time output power PIt is realIt is adjusted, is had in real time by FPGA1
Body, if target output is P, then target output and real-time output power can be calculated as PIt is realIt is real-time poor
Value PDifference, FPGA1 can be according to the real-time difference PDifferenceThe downstream attenuation values for controlling the first RF transceiver 2 are completed to adjust in real time.
A kind of power detection regulating system provided in an embodiment of the present invention, the forward link constituted based on Double RF transceiver
And reverse link, and pass through the data real-time operation of FPGA, realize real-time detection and adjusting in real time to power.
On the basis of the above embodiments, the power detection regulating system further include:
Low-noise amplifier LNA9, the input terminal of the LNA9 connect the output end of the duplexer；The LNA9's is defeated
Outlet connects the receiving end of first RF transceiver.
As shown in Figure 1, it is to be understood that power detection regulating system provided by the embodiment of the present invention has downlink chain
Road also has uplink transmission while transmission.Preferably, used in the embodiment of the present invention in an uplink transmission to be
The input terminal of LNA9, LNA9 connect the output end of the duplexer；The output end of the LNA9 connects first radio-frequency receiving-transmitting
The receiving end of device, LNA are the very low amplifiers of noise coefficient, can reduce noise jamming as far as possible.
On the basis of the above embodiments, the power splitter is active one-to-two power splitter, and the power splitter is by described the
The downlink radio-frequency signal of one RF transceiver transmitting is divided into forward link radio-frequency signal and reverse link radio frequency signals.
By the content of above-described embodiment it is found that the embodiment of the invention provides a power splitters to be divided into forward chaining for signal function
Road signal and reverse link signal.
Preferably, power splitter used in the embodiment of the present invention is active one-to-two power splitter, is using one-to-two power splitter
Due to need to only carry out the two-way function point of signal in embodiments of the present invention.It is since activated distributor can using activated distributor
There is gain, isolation is higher, and the loss of passive power splitter should not be used for a long time greatly very much.
On the basis of the above embodiments, the attenuator is fixed value attenuator.
By the content of above-described embodiment it is found that the reverse link signal that the embodiment of the present invention needs to transmit power splitter carries out
Power attenuation.Equipment used in decaying is attenuator, it is preferred that the attenuator that the embodiment of the present invention uses is fixed value decaying
Device, can decay fixed gain dB.
On the basis of the above embodiments, the FPGA is used to control first RF transceiver by spi bus
Downstream attenuation values.
By the content of above-described embodiment it is found that the embodiment of the invention provides the downlinks that FPGA controls the first RF transceiver
Pad value is completed to adjust in real time.Specifically, controlled by spi bus in adjustment process.It is understood that
Spi bus is the synchronous serial port communicated between processing and control element (PCE) and peripheral equipment, processing and control element (PCE) i.e. this hair
FPGA in bright embodiment, the first RF transceiver in peripheral equipment, that is, embodiment of the present invention, then by spi bus,
FPGA can issue the downstream attenuation that control command controls the first RF transceiver.
Fig. 3 is power detecting method flow diagram provided in an embodiment of the present invention, as shown in Figure 3, comprising:
301, forward link gain G is obtainedF, reverse link gain GBAnd parallel digital signal, the Parallel Digital letter
It number is that the second RF transceiver is digitized according to attenuator output signal；
302, processing operation is carried out to the parallel digital signal, obtains statistics realtime power PInstead；
303, by forward link gain GF, reverse link gain GBAnd statistics realtime power PInsteadSummation obtains defeated in real time
Power P outIt is real。
It should be noted that the executing subject of the embodiment of the present invention is FPGA, method provided by the embodiment of the present invention is answered
It is to be detected to the realtime power of mobile radio communication apparatus with environment.
Specifically, in step 301, FPGA can obtain the forward link gain generated in power detection regulating system
GF, reverse link gain GBAnd parallel digital signal, the parallel digital signal are that the second RF transceiver receiving end receives
After attenuator output signal S, S signal is digitized to the parallel digital signal being converted into.
Further, in step 302, FPGA carries out processing operation to the parallel digital signal, and operation obtains system
Count realtime power PInstead。
Finally, in step 303, realtime power P will be countedInstead, forward link gain GF, reverse link gain GBSummation
Obtain final real-time output power PIt is real, i.e. PIt is real=PInstead+GB+GF。
Fig. 4 is power regulating method flow diagram provided in an embodiment of the present invention, as shown in Figure 4, comprising:
401, target output P and real-time output power P is obtainedIt is real；
402, the target output P and real-time output power P is calculatedIt is realBetween real-time difference PDifference；
403, according to the real-time difference PDifferenceSize, determine the degree of regulation of the first RF transceiver downstream attenuation values.
It should be noted that the executing subject of the embodiment of the present invention is FPGA, method provided by the embodiment of the present invention is answered
It is to be adjusted to the realtime power of mobile radio communication apparatus with environment.
Fig. 5 is that down output power provided in an embodiment of the present invention adjusts schematic diagram in real time, in conjunction with Fig. 5, in step 401
In, FPGA can obtain target output P and real-time output power P firstIt is real, target output P refers to mobile radio telecommunications
Equipment and the output power pre-set, real-time output power PIt is realIt is that FPGA real-time detection obtains, it is preferred that can use
PIt is real=PInstead+GB+GFIt is calculated, wherein PInsteadTo count realtime power, GFFor forward link gain, GBFor reverse link gain,
PInsteadCalculating referring to Figure 5.
It further, in step 402, is P according to target output P and real-time output powerIt is real, can be calculated
The realtime power difference P at each momentDifference。
Finally, in step 403, according to realtime power difference PDifference, FPGA can determine under the first RF transceiver
The degree of regulation of row pad value needs the amplitude of accommodation carried out, to complete to adjust in real time.
On the basis of the above embodiments, the method also includes:
According to the degree of regulation of the first RF transceiver downstream attenuation values, by spi bus control the first RF transceiver into
Row power regulation.
By the content of above-described embodiment it is found that the embodiment of the present invention can determine whether the tune of the first RF transceiver downstream attenuation values
Then section degree controls the first RF transceiver and carries out power regulation.It is received specifically, FPGA controls the first radio frequency by spi bus
The downstream attenuation values for sending out device complete the real-time adjusting of power.
On the basis of the above embodiments, the degree of regulation of the degree of regulation of the first RF transceiver downstream attenuation values is
0.25dB。
Preferably, FPGA is to the degree of regulation of the first RF transceiver downstream attenuation values in the embodiment of the present invention
0.25dB。
Through the above description of the embodiments, those skilled in the art can be understood that each embodiment can
It realizes by means of software and necessary general hardware platform, naturally it is also possible to pass through hardware.Based on this understanding, on
Stating technical solution, substantially the part that contributes to existing technology can be embodied in the form of software products in other words, should
Computer software product may be stored in a computer readable storage medium, such as ROM/RAM, magnetic disk, CD, including several fingers
It enables and using so that a computer equipment (can be personal computer, server or the network equipment etc.) executes each implementation
Method described in certain parts of example or embodiment.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (9)
1. a kind of power detection regulating system characterized by comprising
Programmable gate array FPGA, the first RF transceiver, the second RF transceiver, power splitter, power amplifier PA, duplex
Device, attenuator and antenna；
The FPGA is separately connected first RF transceiver and second RF transceiver；
The transmitting terminal of first RF transceiver connects the input terminal of the power splitter；
The output end of the power splitter is connect with the input terminal of the input terminal of the PA and the attenuator respectively；
The output end of the attenuator connects second RF transceiver；
The output end of the PA connects the input terminal of the duplexer, and the duplexer connects the antenna.
2. system according to claim 1, which is characterized in that the power detection regulating system further include:
Low-noise amplifier LNA, the input terminal of the LNA connect the output end of the duplexer；The output end of the LNA connects
The receiving end of first RF transceiver.
3. power detection regulating system according to claim 1, which is characterized in that the power splitter is active one-to-two function
The downlink radio-frequency signal that first RF transceiver emit is divided into forward link radio-frequency signal and instead by point device, the power splitter
To link radio frequency signals.
4. power detection regulating system according to claim 1, which is characterized in that
The attenuator is fixed value attenuator.
5. power detection regulating system according to claim 1, which is characterized in that
The FPGA is used to control the downstream attenuation values of first RF transceiver by spi bus.
6. a kind of power detecting method that -5 any power detection regulating systems are implemented according to claim 1, feature
It is, comprising:
Obtain forward link gain GF, reverse link gain GBAnd parallel digital signal, the parallel digital signal are second
RF transceiver is digitized according to attenuator output signal；
Processing operation is carried out to the parallel digital signal, obtains statistics realtime power PInstead；
By forward link gain GF, reverse link gain GBAnd statistics realtime power PInsteadSummation obtains real-time output power PIt is real。
7. a kind of power regulating method that -5 any power detection regulating systems are implemented according to claim 1, feature
It is, comprising:
Obtain target output P and real-time output power PIt is real；
Calculate the target output P and real-time output power PIt is realBetween real-time difference PDifference；
According to the real-time difference PDifferenceSize, determine the degree of regulation of the first RF transceiver downstream attenuation values.
8. the method according to the description of claim 7 is characterized in that the method also includes:
According to the degree of regulation of the first RF transceiver downstream attenuation values, the first RF transceiver is controlled by spi bus and carries out function
Rate is adjusted.
9. according to the method described in claim 8, it is characterized in that, the degree of regulation of the first RF transceiver downstream attenuation values
Degree of regulation be 0.25dB.
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| CN201910354874.XA CN110139309B (en) | 2019-04-29 | 2019-04-29 | Power detection and regulation system, power detection method and power regulation method |
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| CN201910354874.XA CN110139309B (en) | 2019-04-29 | 2019-04-29 | Power detection and regulation system, power detection method and power regulation method |
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