CN104752492A - 用于制造半导体器件的方法和半导体器件 - Google Patents

用于制造半导体器件的方法和半导体器件 Download PDF

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CN104752492A
CN104752492A CN201410831980.XA CN201410831980A CN104752492A CN 104752492 A CN104752492 A CN 104752492A CN 201410831980 A CN201410831980 A CN 201410831980A CN 104752492 A CN104752492 A CN 104752492A
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semiconductor device
doping
source region
groove
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CN104752492B (zh
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P·伊尔西格勒
J·鲍姆加特尔
M·聪德尔
A·毛德
F·希尔勒
R·威斯
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Infineon Technologies Austria AG
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Abstract

本公开涉及用于制造半导体器件的方法和半导体器件，该半导体器件通过形成以下项而形成：在具有主表面的半导体衬底中的晶体管；源极和漏极区域；和在源极区域和漏极区域之间的沟道区域和漂移区。源极区域和漏极区域被沿着平行于主表面的第一方向布置。栅极沟槽和栅极电极形成于栅极沟槽中。在主表面中形成的副沟槽在与第一方向相交的第二方向上延伸。使用经由副沟槽的侧壁引入掺杂物的掺杂方法形成源极区域。

Description

用于制造半导体器件的方法和半导体器件
技术领域
本申请涉及用于制造半导体器件的方法和半导体器件。
背景技术
通常使用于汽车和工业电子装置的功率晶体管需要低的导通电阻(Ron)，同时获得高的电压阻挡能力。例如，MOS(“金属氧化物半导体”)功率晶体管应该是能够胜任的，依赖于阻挡几十到几百或几千伏的漏极至源极电压Vds的应用需要。MOS功率晶体管通常导通非常大的电流，在约2至20V的典型的栅极-源极电压下可以高至几百安培。
正在试图开发用于功率晶体管的新构思。尤其正在寻找具有增加的沟道宽度的功率晶体管。
发明内容
根据一实施例，形成半导体器件的方法包括在具有主表面的半导体衬底中形成晶体管。该方法包括形成源极区域和漏极区域，形成布置在源极区域和漏极区域之间的沟道区域和漂移区，源极区域和漏极区域沿着平行于主表面的第一方向布置。该方法进一步包括形成栅极沟槽以及在栅极沟槽中形成栅极电极。该方法附加地包括在主表面中形成副沟槽，副沟槽在与第一方向相交的第二方向上延伸。使用经由副沟槽的侧壁引入掺杂物的掺杂方法形成源极区域。
根据一实施例，半导体器件包括在具有主表面的半导体衬底中的晶体管。该晶体管包括源极区域和漏极区域、在源极区域和漏极区域之间的沟道区域、在主表面中布置在邻近的沟道区域之间的栅极沟槽、在栅极沟槽中的栅极电极和在主表面处的本体接触区域，源极区域和漏极区域中的每个区域被布置在主表面处，本体接触区域接触沟道区域。源极区域和本体接触区域沿着与第一方向交叉的第二方向交替地布置。
根据另外的实施例，集成电路包括如上所定义的半导体器件。
本领域的技术人员一旦阅读下文的详细描述并且观看附图，将认识到附加的特征和优点。
附图说明
附图被包括以提供本发明的实施例的进一步的理解并且被并入和组成本说明书的一部分。附图图示了本发明的实施例，并且和说明一起用来解释原理。本发明的其他实施例和众多预期的优点将会被轻易地领会，因为通过参考下面的详细描述它们变得更加易懂。附图的元件不一定相对彼此成比例。相同的附图标记标示相应的类似的部件。
图1A示出了根据一实施例的半导体器件的平面视图；
图1B示出了图1A所示的半导体器件的第一截面视图；
图1C示出了图1A所示的半导体器件的在与图1B的截面视图的方向垂直的方向上的截面视图；
图1D示出了图1A所示的半导体器件的另一部分的截面视图；
图2A示出了进行根据一实施例的方法时的半导体器件的截面视图；
图2B示出了衬底在进行进一步的加工步骤之后的截面视图；
图2C示出了衬底在进行进一步的加工步骤之后的截面视图；
图2D示出了半导体衬底在进行进一步的加工步骤之后的截面视图；
图2E示出了衬底在进行进一步的加工步骤之后的截面视图；
图3A图示了进行了根据另一实施例的方法时衬底的截面视图；
图3B示出了进行另一方法时衬底的截面视图；
图4A示出了进行根据又一实施例的方法时半导体衬底的截面视图；
图4B示出了根据另一实施例的半导体器件的截面视图；
图5A示出了根据一实施例的半导体器件的平面视图；
图5B示出了根据另一实施例的半导体器件的截面视图；
图6A示出了根据另一实施例的半导体器件的平面视图；
图6B示出了根据一实施例的半导体器件的截面视图；
图6C示出了进行根据一实施例的方法时的衬底的截面视图；
图6D示出了进行根据一实施例的方法时的半导体器件的平面视图；
图6E示出了进行进一步的加工步骤之后的半导体器件的平面视图；
图6F示出了进行进一步的加工步骤之后的半导体器件的平面视图；
图7示出了根据一实施例的方法的流程图；
图8A示出了根据另一实施例的方法的流程图；以及
图8B示出了根据又一实施例的方法的流程图。
具体实施方式
在下面的详细描述中，参考附图，附图形成本文的一部分并且其中通过图示的方式图示了可以实施本发明的特定实施例。就这点而言，参考描述附图的方向来使用方向术语，诸如“顶”、“底”、“前”、“后”、“前面的”、“后面的”等。由于本发明的实施例的部件可以被放置在很多不同的方向上，方向术语用于图示的目的，而绝不是限制。应当理解可以使用其他实施例并且可以在不偏离权利要求所定义的范围的情况下做出结构或者逻辑上的变化。
对于实施例的描述不是限制性的。特别地，在下文中所描述的实施例的元件可以与不同实施例的元件结合。
在下面的说明中使用的术语“晶片”、“衬底”或“半导体衬底”可以包括具有半导体表面的任何基于半导体的结构。晶片和结构应当被理解为包括硅、绝缘体上硅(SOI)、蓝宝石上硅(SOS)、掺杂和非掺杂半导体、由基底半导体基础支撑的硅外延层、和其他半导体结构。半导体不需要是基于硅的。半导体也可以是硅锗、锗、或砷化镓。根据其它实施例，碳化硅(SiC)或者氮化镓(GaN)可以形成半导体衬底材料。
如本说明书中使用的术语“横向的”和“水平的”旨在描述平行于半导体衬底或者半导体本体的主表面的方向。例如这可以是晶片或者裸片的表面。
如本说明书中使用的术语“垂直的”旨在描述布置成垂直于半导体衬底或者半导体本体的第一表面的方向。
附图和描述通过指明紧挨着掺杂类型“n”或“p”的“-”或“+”图示了相对掺杂浓度。例如，“n-”意指比“n”掺杂区域的掺杂浓度更低的掺杂浓度，而“n+”掺杂区域具有比“n”掺杂区域更高的掺杂浓度。具有相同相对掺杂浓度的掺杂区域不一定具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区域可以具有相同或者不同的绝对掺杂浓度。在附图和描述中，为了更好地理解，通常掺杂部分被标示为“p”型或“n”型掺杂。如将要清晰地理解的，该标示绝不是旨在限制。掺杂类型可以是任意的，只要实现所描述的功能。进一步地，在所有实施例中，掺杂类型可以被反转。
如本文所使用的术语“具有”、“包含”、“包括”、“含有”等是开放式术语，也就是说，这些术语表明所叙述的元件或者特征的存在，但并不排除附加的元件或者特征。冠词“一”、“一个”和“该”旨在包括单数和复数，除非上下文另外明确指明。
如本说明书所使用的，术语“耦合”和/或“电耦合”不是意于意指元件必须直接耦合在一起，而是可以在“耦合”或“电耦合”元件之间提供中介元件。术语“电耦合”旨在描述电连接到一起的元件之间的低欧姆电连接。
本说明书涉及半导体部分被掺杂的“第一”和“第二”导电类型的掺杂物。第一导电类型可以是p型，而第二导电类型可以是n型，或者反之亦然。如一般所知的，依赖于掺杂类型或者源极和漏极区域的极性，MOSFET可以是n沟道或者p沟道MOSFET。例如，在n沟道MOSFET中，源极和漏极区域掺有n型掺杂物，并且电流方向是从漏极区域到源极区域。在p沟道MOSFET中，源极和漏极区域掺有p型掺杂物，并且电流方向是从源极区域到漏极区域。如将要清晰地理解的，在本说明书的上下文内，掺杂类型可以被反转。如果使用方向语言描述特定的电流路径，该描述应当仅仅被理解为指明路径，而不是电流的极性，即不管晶体管是p沟道还是n沟道晶体管。附图可以包括极性敏感的部件，例如二极管。如将要清晰地理解的，这些极性敏感的部件的特定布置是作为示例给出，并且可以被颠倒以便实现所描述的功能，取决于第一导电类型意指n型还是p型。
实施例被描述同时明确地指的是所谓的常断型晶体管，即当没有栅极电压或者0V的栅极电压被施加时，处于关断状态的晶体管。如将要清晰地理解的，本教导可以同等地应用于常通型晶体管，即当没有栅极电压或者0V的栅极电压被施加时，处于导通状态的晶体管。
图1A示出了半导体器件1或者集成电路的平面图，或者更确切地，在平行于半导体衬底的主表面中截取的截面视图。
半导体器件1包括晶体管200。图1A所示的晶体管200包括源极区域201、漏极区域205、沟道区域220、和漂移区260。源极区域201、漏极区域205和漂移区260可以由第一导电类型的掺杂物掺杂，例如n型掺杂物。源极区域201和漏极区域205的掺杂浓度可以比漂移区260的掺杂浓度更高。沟道区域220被布置在源极区域201和漂移区260之间。沟道区域220被第二导电类型的掺杂物掺杂，例如p型掺杂物。漂移区260可以被布置在沟道区域220和漏极区域205之间。源极区域201、沟道区域220、漂移区260和漏极区域205被沿着平行于半导体衬底的主表面的第一方向布置。源极区域201电连接到源极电极202。漏极区域205电连接到漏极电极206。半导体器件1进一步包括栅极电极210。栅极电极210借助于诸如氧化硅之类的绝缘栅极电介质材料211与沟道区域220绝缘。
根据一实施例，晶体管可以进一步包括邻近漂移区260布置的场板250。场板250借助于诸如氧化硅之类的绝缘场电介质层251与漂移区260绝缘。晶体管200是横向晶体管。因此，从源极区域201到漏极区域205的电流主要在平行于半导体衬底的主表面的第一方向上实现。
当施加合适的电压到栅极电极210时，在沟道区域220或者本体区域和绝缘栅极电介质材料211之间的边界处形成反型层。因此，晶体管处在经由漂移区260从源极区域201到漏极区域205的导通状态。在沟道区域220中形成的沟道的导电性受栅极电极的控制。通过控制形成于沟道区域中的沟道的导电性，可以控制从源极区域201经由形成于沟道区域220中的沟道和漂移区260到漏极区域205的电流。
当晶体管被关断时，在沟道区域220和绝缘栅极电介质材料211之间的边界处没有导电沟道形成，从而只有亚阈值电流可以流过。
根据一实施例，晶体管可以被实现为常断型晶体管。根据另一实施例，晶体管可以被实现为常通型晶体。在该情况下，沟道区域220可以由第一导电类型的掺杂物掺杂，例如n型掺杂物。
可以施加合适的电压到处于关断状态的场板。例如，场板250可以电连接到源极端子，源极端子也电连接到源极电极202。在关断状态下，场板250耗尽来自漂移区260的电荷载流子，从而改善晶体管200的击穿电压特性。在包括场板250的晶体管200中，相比于没有场板的器件，可以增加漂移区260的掺杂浓度，而不恶化击穿电压特性。由于漂移区的更高的掺杂浓度，导通电阻RDSon被进一步减小，导致改善的器件特性。
图1B图示了半导体器件1的在如图1A也指明的I和I’之间的沿着第一方向的截面视图。选取图1B的截面视图以便横切沟道区域220和漂移区260。如虚线所指明的，栅极沟槽212被布置成在附图的所描绘的平面前面和后面的平面中邻近沟道区域220。进一步地，场板沟槽252可以被布置成在附图的所描绘的平面前面和后面的平面中邻近漂移区260。栅极沟槽212和场板沟槽252在衬底100的深度方向上从主表面110延伸。因此，栅极电极邻近沟道区域220的至少两侧。进一步地，沟道区域220具有第一脊部的形状。由于场板沟道252的存在，根据一实施例，漂移区260可以具有第二脊部的形状。
源极区域201从主表面110沿着衬底100的深度方向(即相对于主表面110垂直)延伸。漏极区域205同样地从主表面110沿着衬底100的深度方向延伸。
图1C图示了半导体器件的如图1A也图示了的在II和II’之间截取的截面视图。在II和II’之间的方向垂直于第一方向。如图1C所示，沟道区域220具有脊部的形状，脊部具有宽度d1。例如，脊部可以具有顶侧、第一侧壁220b和第二侧壁220a。侧壁220b、220a可以垂直于主表面110或者相对于主表面110成大于75°的角度延伸。
如可以从图1B和图1C的组合推断出的，晶体管的有效宽度取决于脊部的深度t1，以及进一步地取决于源极区域202的深度。换句话说，沟道的有效宽度取决于栅极电极被布置于其中的栅极沟槽的深度，以及取决于源极区域202的深度。
如下文将要解释的，可以使用沿着与在I和I’之间的第一方向交叉的第二方向延伸的副沟槽形成源极。例如，副沟槽可以在半导体衬底的主表面110中形成，并且可以使用副沟槽进行形成源极区域201的掺杂工艺。更详细地，可以经由副沟槽的侧壁完成掺杂。例如，可以将掺杂物引入，或者经由副沟槽的侧壁引入布置在栅极电极一侧上的侧壁。由此，例如，可以实现掺杂到半导体衬底的期望的深度。
图1B进一步示出了本体接触区域225，本体接触区域225可以布置在沟道区域220之下以及在漂移区260的部分之下。本体接触区域225电连接沟道区域或者本体区域到源极电极202，并且进一步抑制或者恶化寄生双极型晶体管。此外，本体接触区域225可以在漂移区260之下延伸，从而在晶体管的关断状态，漂移区260可以被轻易地耗尽。本体接触导电区域225可以由第二导电类型的掺杂物以高于沟道区域的掺杂浓度掺杂。在下文中，将要讨论该本体接触区域225的备选的构思。
参考图1C，沟道区域220或者本体区域(例如p型掺杂的本体区域)的宽度d1满足下列关系：d1≤2*ld，其中ld表示在栅极电介质层211与本体区域或者沟道区域220之间的界面处形成的耗尽区的长度。例如，耗尽区的宽度可以确定为：
l d = 4 ϵ s kT ln ( N A / n i ) q 2 N A
其中，εs表示半导体材料的介电常数(硅为11.9×ε0，ε0＝8.85×10-14F/cm)，k表示玻尔兹曼常数(1.38066×10-23J/K)，T表示温度，ln表示自然对数，NA表示半导体本体的杂质浓度，ni表示本征载流子浓度(硅在27℃下为1.45×1010cm-3)，以及q表示元电荷(1.6×10-19C)。
通常，耗尽区的长度根据栅极电压变化。假定在晶体管中在对应于阈值电压的栅极电压下耗尽区的长度对应于耗尽区的最大宽度。例如，第一脊部的宽度可以是约10到200nm，例如沿着半导体衬底100的主表面110约20到60nm。
此外，长度对宽度的比可以满足下列关系：s1/d1＞2.0，其中s1表示第一脊部与栅极电极210重叠的长度，或者换句话说，沿着第一方向测量的沟道区域的长度，如图1A也图示了的。根据另一实施例，s1/d1＞2.5。
根据其中宽度d1≤2*ld的实施例，晶体管200是所谓的“完全耗尽型”晶体管，其中当栅极电极210被设置到导通电压时，本体区域(例如p型掺杂本体区域)或者沟道区域220被完全耗尽。在这种晶体管中，可以实现最优的亚阈值电压并且可以有效地抑制短沟道效应，导致改善的器件特性。
根据一实施例，漂移区260可以包括没有被图形化以形成脊部的平坦的表面。根据另一实施例，场板250可以被布置在沟槽252中，从而漂移区260包括脊部。在包括场板250的晶体管中，使用具有大于沟道区域的宽度d1的宽度d2的漂移区260可以是有利的。因此，场板沟槽252可以以更大的距离布置，从而漂移区260布置在邻近的场板沟槽252之间的部分具有更大的宽度。根据另一实施例，可以选择d2小于d1。通常，在场板和漂移区之间的场电介质层的厚度大于栅极电介质的厚度，以增加源极-漏极击穿电压。这可以导致场板沟槽与栅极沟槽和隔离沟槽相比具有更大的节距。
为了改善半导体器件在沟道区域的特性并且进一步改善在漂移区的器件特性，可以使用合适的刻蚀掩膜来实现图形化栅极电极和场板以便提供第一和第二脊部的不同的宽度。
根据一实施例，栅极沟槽212和场板沟槽252可以彼此分开。根据另一实施例，栅极沟槽212和场板沟槽252可以被合并以便形成具有不同宽度的单一的沟槽。
在图1A至图1D中图示的半导体器件实现了横向功率晶体管。因为它们可以以简单的方式集成，所以它们可以使用在DC/DC或AC/DC转换器上。进一步地，它们可以达到高电流密度，从而它们可以用于小功率和在10V和几百伏之间的电压。
图2A至图2E图示了根据一实施例的制造半导体器件的方法。例如，使用该方法，可以制造在图1A至图1D中图示的半导体器件。
可以通过进行众所周知的浅沟槽隔离工艺(STI)和注入步骤对半导体衬底进行预处理。例如，可以进行阱注入步骤以便形成阱注入部分120，随后进行另一注入步骤用于提供本体接触区域225，以及掺杂步骤用于在衬底材料层130中形成沟道区域220。进一步地，可以进行注入步骤以便限定漂移区260。在图2A所示的实施例中，漂移区260是n型掺杂的，而沟道区域是p型掺杂的。衬底材料层130可以是n型掺杂的。本体接触区域225是重度p型掺杂的。如将要清晰地理解的，可以实施反转的掺杂类型。
图2A示出了图1A所示的I和I’之间的截面视图。在下一步骤中，栅极沟槽212和可选地场板沟槽(未在该图中示出)可选地使用硬掩膜被通过光刻限定和刻蚀。例如，栅极沟槽可以具有约500nm至5000nn，更明确地，1000nm至2000nm，的深度。邻近栅极沟槽212之间的距离依赖于将要实现的特定的半导体器件。例如，在将要形成完全耗尽型晶体管的情况下，距离可以是30nm至300nm。然而，该距离也可以更大，例如500至1000nm。栅极沟槽212被限定以便将沟道区域220图形化成脊部。图2B示出了在IV和IV’之间，即在包括栅极沟槽并且其中不存在场板的截面中选取的截面视图。
依赖于将要实现的结构，可以形成场板电介质层251并且将其从不需要的部分移除。然后可以，例如通过热氧化，形成栅极电介质层211。例如，栅极电介质层211可以具有5nm至50nm的厚度。然后，形成栅极电极210的导电材料以及可选地场板250被形成。例如，可以沉积多晶硅。例如，多晶硅可以具有50nm至200nm的厚度。多晶硅材料可以是n型掺杂的或者可以是非掺的并且可以在沉积之后被掺杂。然后，导电材料被图形化以便形成栅极电极210以及可选地场板250。
图2C示出了得到的结构的示例。栅极电极210被形成以便邻近在附图所绘平面之前和之后布置的沟道区域220。栅极沟槽212延伸到深度t1。
此后，副沟槽140被限定在半导体衬底的主表面110中。
例如，副沟槽140可以可选地使用硬掩膜被通过光刻限定和刻蚀。例如，副沟槽140可以被刻蚀以便具有锥形的侧壁。图2D示出了得到的结构在I和I’之间，即在其中没有布置栅极沟槽的部分处的示例。副沟槽140可以被形成为邻近于沟道区域220。例如，副沟槽140可以延伸到约500nm至5000nm的深度。例如，副沟槽140可以延伸到与栅极沟槽212大约相同或者更少的深度。术语“大约相同的深度”旨在意指由于工艺导致的变化，任一副沟槽140的深度可以比栅极沟槽212的深度少或者多约10％。
用于形成源极区域201的掺杂物可以经由副沟槽140的侧壁引入。例如，可以进行倾斜的离子注入步骤145以便掺杂邻近于副沟槽140的侧壁的半导体材料。由此，源极区域201可以被形成为邻近于副沟槽140的侧壁。
图2E示出了当进行倾斜的离子注入工艺145时的衬底的截面视图的示例。根据另一实施例，副沟槽140可以利用掺杂的材料进行填充，诸如掺杂的氧化物或者掺杂的硅材料，接着进行扩散工艺。此后，可以从副沟槽140去除掺杂材料。可以在副沟槽140中填充导电材料，由此形成源极电极202。合适的导电材料包括重度掺杂的多晶硅、硅化物(例如金属硅化物)、金属以及这些材料的组合。
根据另一实施例，副沟槽可以被形成以具有近似垂直于主表面的侧壁。例如，可以使用各向异性的刻蚀工艺。
图3A示出了具有近似垂直于主表面110的侧壁的副沟槽140的示例。然后，进行包括各向同性掺杂工艺147的掺杂工艺，诸如等离子体辅助掺杂(PLAD)。
图3B示出了当进行该各向同性掺杂方法147时的半导体衬底的示例。由于该掺杂工艺，源极区域201被形成为邻近于副沟槽140的侧壁。根据备选例，可以在副沟槽140中填充由CVD(化学气相沉积)形成的掺杂材料，诸如掺杂的氧化磷、掺杂的氧化硅、掺杂的多晶硅、玻璃，以及由选择性外延方法形成的掺杂材料，接着进行扩散工艺以形成源极区域201。然后，可以以如上文所述的方法在副沟槽中沉积导电材料。
根据另一实施例，可以附加地使用副沟槽140用于形成本体接触区域225。根据该实施例，副沟槽140的底部部分掺有第一导电类型的掺杂物以形成本体接触区域225。此后，在副沟槽140的底部部分之上形成牺牲材料150。例如，牺牲材料150可以包括可以通过高密度等离子体方法形成的氧化硅，其中只有副沟槽140的水平部分被氧化硅材料覆盖。然后，进行另一掺杂工艺以便形成邻近副沟槽140的侧壁的源极区域201。
图4A示出了得到的结构的示例。如图所示，本体接触区域225被布置在副沟槽140的底侧下方，而源极区域201在牺牲材料150上方的部分处形成。图4A进一步示出了掩埋的本体接触区域225在沟槽区域下方延伸、并且可选地进一步在漂移区260下方延伸的部分。也可以省去掩埋本体接触区域225在沟槽区域下方延伸的部分。此后，将去除牺牲材料150，接着进行形成导电材料的步骤用来形成源极电极202。导电材料的示例包括上文所述的材料。
图4B示出了得到的结构的示例。如图所示，源极电极202被电连接到源极区域201和本体接触区域225。
图5A示出了根据另一实施例的半导体器件的平面视图。根据图5A所示的实施例，半导体器件形成在具有主表面110的半导体衬底100中。晶体管包括源极区域501和漏极区域205、沟道区域220和漏极区域205。源极区域501和漏极区域205被沿着平行于主表面的第一方向布置。栅极电极510被布置在形成于半导体衬底100的主表面中的栅极沟槽512之中。例如，栅极沟槽512可以类似于图1B所图示的栅极沟槽212。半导体器件进一步包括在主表面中形成的本体接触区域225。如图5A所示，半导体器件进一步包括与源极区域501相接触的源极接触502。源极区域501和本体接触区域225被沿着与第一方向相交的第二方向交替地布置。栅极沟槽512的数目可以对应于源极区域501和本体接触区域225的总和。
如图5A所示的栅极电极510被耦合到栅极端子530。进一步地，在邻近本体接触区域225的栅极沟槽512中的导电材料520可以与不同于栅极端子的端子连接。例如，端子535可以是源极端子。根据另一实施例，邻近本体接触区域的栅极沟槽512可以由绝缘材料填充。根据另一实施例，所有栅极沟槽512可以具有连接到栅极端子530的导电填充物。根据图5A所示的实施例，导电材料155邻近并且电连接到本体接触区域225。进一步地，源极电极502邻近并且电连接到源极区域501。源极电极502和导电材料155电连接到源极端子。根据另一实施例，源极电极502和导电材料155可以是在副沟槽内的导电填充物的部分。根据该实施例，源极区域501和本体接触区域225在导电填充物和邻近的栅极沟槽512之间以交替的方式布置。在图5A所示的布置下，由于源极区域501和本体接触区域225沿着第二方向测量的尺寸，邻近的栅极沟槽512之间的距离并且因此沟道区域的宽度d1可以大于在栅极电介质层511和沟道区域220之间的界面处形成的耗尽区的长度。因此，晶体管可以不实现“完全耗尽型”晶体管，其中当栅极电极210被设置到导通电压时，沟道区域220被完全耗尽。例如，沟道区域的宽度d1可以是150nm至300nm，例如，200nm至250nm。
图5B示出了如图5A也示出的半导体器件在I和I’之间的截面视图。栅极沟槽512在半导体衬底100的主表面110中形成。例如，栅极沟槽512可以被形成栅极电极510的导电材料填充。进一步地，栅极电介质材料511可以布置在栅极电极510和邻近的衬底材料之间。掺杂部分501、225可以被布置为邻近栅极沟槽512。例如，掺杂部分可以实现例如由第一导电类型掺杂物(例如n型掺杂物)掺杂的源极区域501。备选地，掺杂部分225可以由第二导电类型的掺杂物掺杂以实现本体接触区域225。导电材料502、155可以邻近掺杂部分形成并且可以被电连接到掺杂部分。导电材料501、155可以被连接到源极端子。
沟道区域220被布置在附图所绘的平面之前和之后的平面中。沟道区域220和漂移区260被布置在源极区域501和漏极区域205之间。漏极区域205可以延伸到任意的深度。依赖于截面视图的精确位置，要么源极区域501要么本体接触区域225可以被布置邻近栅极沟槽512。如参考图5A已经讨论的，栅极沟槽512内的导电材料510被电连接到栅极端子以防邻近的掺杂部分实现源极区域501。当邻近的掺杂部分实现本体接触区域225时，栅极沟槽512的导电填充物可以被连接到源极端子535或者可以是绝缘填充物。
图6A至图6D图示了制造图5的半导体器件的方法。出发点是包括栅极沟槽650和副沟槽610的半导体器件。图6A示出了该半导体衬底100的平面视图。例如，半导体衬底100可以以已经参考图2A至2D所解释的方式进行加工，而不形成掩埋本体接触区域225。虽然没有明确示出，沟道区域220和漂移区260已经在半导体衬底100内以传统的方式形成。
图6B示出了半导体衬底100在如图6A也图示的I和I’之间的截面视图。如图所示，邻近于由虚线指明的栅极沟槽650形成副沟槽610。此后，在表面上形成包括诸如氧化硅的牺牲材料的牺牲层以填充副沟槽610。然后，在牺牲层630的表面之上形成光刻胶层640。
图6C示出了得到的结构的截面视图。通过光刻将开口限定在光刻胶层640之内，接着进行刻蚀以形成第一开口620。例如，第一开口可以具有约0.2μm至0.7μm的宽度，例如，0.3μm至0.5μm。使用第一开口620作为掺杂掩膜，可以进行掺杂工艺以便掺杂邻近相应的栅极沟槽650的未覆盖的侧壁。如图6D明确示出的，第一开口620被形成以便邻近每个第二栅极沟槽650。可以以任意方式进行掺杂工艺，例如使用上文参考图2至图4解释的方法中的任何一个。更具体些，可以实现来自气相的掺杂或者使用气相材料。备选地，第一开口620可以填充有掺杂材料，诸如掺杂氧化磷、掺杂氧化硅、或者硅或者掺杂玻璃。例如，可以进行用第二导电类型的掺杂物的掺杂以便形成本体接触区域225。
在进行第一掺杂工艺之后，得到的结构可以被另一光刻胶层覆盖，并且第二开口625可以被限定在两个邻近的第一开口620之间的位置处。第二开口625的尺寸可以等于第一开口620的尺寸。此后，可以进行另一掺杂工艺以便掺杂邻近相应的沟槽650的侧壁。例如，可以进行用第一导电类型的掺杂物的掺杂以便形成源极区域501。可以使用如上文所阐明的相似的掺杂方法进行第二掺杂工艺。根据一实施例，第二开口625可以利用由第一导电类型的掺杂物掺杂的填充物进行填充。
图6E示出了得到的包括第二开口625的衬底的示例的平面视图。
图6F示出了在去除光刻胶层之后得到的结构的示例的平面视图。如图所示，第一开口620和第二开口625以交替的方式布置。此后，例如，可以进行热处理以便实施从第一开口和从第二开口的扩散工艺。然后，可以进行另外的工艺以便提供半导体器件的另外的部件。例如，可以从第一开口620和第二开口625之间的空间去除牺牲材料。然后，在第一开口620和第二开口625之间的衬底部分可以通过外延再生长。可选地，可以去除第一开口620和第二开口625的填充物。可以在第一开口620和第二开口625内填充导电材料以提供到源极端子的电连接。合适的导电材料包括重度掺杂的多晶硅、硅化物(例如金属硅化物)、金属和这些材料的组合。这些材料可以通过通常所知的方法形成。
图7总结了根据一实施例的形成半导体器件的方法。形成半导体器件的方法包括在具有主表面的半导体衬底中形成半导体器件。该方法包括形成源极区域(S60)和漏极区域，形成布置在源极区域和漏极区域之间的沟道区域和漂移区(S10)。源极区域和漏极区域被沿着平行于主表面的第一方向布置。该方法进一步包括形成栅极沟槽(S20)和在栅极沟槽中形成栅极电极(S30)，该栅极沟槽具有对应于沟道区域的宽度d1的距离，宽度d1满足：d1≤2*ld，其中ld表示在沟道区域和邻近栅极电极的栅极电介质之间的界面处形成的耗尽区的长度。该方法进一步包括在主表面中形成副沟槽(S40)，副沟槽在与第一方向相交的第二方向上延伸。使用经由副沟槽的侧壁引入掺杂物的掺杂方法形成源极区域。
图8A总结了根据一实施例的形成半导体器件的另一方法。该方法包括在具有主表面的半导体衬底中形成晶体管。该方法包括形成源极区域和漏极区域(S165)，形成布置在源极区域和漏极区域之间的沟道区域和漂移区(S110)。源极区域和漏极区域被沿着平行于主表面的第一方向布置。该方法进一步包括形成栅极沟槽(S120)和在栅极沟槽中形成栅极电极(S130)、和在主表面内形成副沟槽(S140)，副沟槽沿着与第一方向相交的第二方向延伸。该方法进一步包括形成填充副沟槽的牺牲材料(S150)、在牺牲材料中形成第一开口(S160)和通过掺杂邻近第一开口的衬底材料进行第一掺杂工艺以形成本体接触区域(S170)。使用经由副沟槽的侧壁引入掺杂物的掺杂方法形成源极区域。例如，形成源极区域可以包括在牺牲材料中形成第二开口(S180)和通过掺杂邻近第二开口的衬底材料进行第二掺杂工艺(S190)以形成源极区域。
图8B总结了根据一实施例的形成半导体器件的方法。该方法包括在具有主表面的半导体衬底中形成晶体管。该方法包括形成源极区域和漏极区域(S260)，形成布置在源极区域和漏极区域之间的沟道区域和漂移区(S210)。源极区域和漏极区域被沿着与主表面平行的第一方向布置。该方法进一步包括形成栅极沟槽(S220)和在栅极沟槽中形成栅极电极(S230)、以及在主表面中形成副沟槽(S240)，副沟槽在与第一方向相交的第二方向上延伸。该方法进一步包括用第一导电类型的掺杂物来掺杂邻近副沟槽的底侧的衬底部分以形成本体接触区域(S250)。形成源极区域(S260)包括用第二导电类型的掺杂物来掺杂邻近主表面的衬底部分以形成源极区域。
如上文所解释的，所描述的实施例提供增加晶体管沟道宽度的可能性，由此可以降低功率晶体管的电阻率。由于所描述的方法，可以实现功率晶体管减少的开关损失和增加的健壮性。进一步地，所描述的半导体器件具有电连接源极端子和本体区域的低欧姆本体接触区域。由此，可以降低晶体管的开关电阻率。进一步地，例如，当体二极管的极性被反转或者将要发生雪崩击穿时，大量的空穴经由源极端子放电。由此，可以增加晶体管的健壮性。

Claims (20)

1.一种形成半导体器件的方法，所述方法包括在具有主表面的半导体衬底中形成晶体管，所述方法进一步包括：
形成源极区域和漏极区域；
形成布置在所述源极区域和所述漏极区域之间的沟道区域和漂移区，所述源极区域和所述漏极区域被沿着平行于所述主表面的第一方向布置；
形成栅极沟槽和在所述栅极沟槽中的栅极电极；以及
在所述主表面中形成副沟槽，所述副沟槽在与所述第一方向相交的第二方向上延伸，使用经由所述副沟槽的侧壁引入掺杂物的掺杂方法形成所述源极区域。
2.根据权利要求1所述的方法，其中形成所述副沟槽包括各向异性的刻蚀工艺以形成具有近似垂直于所述主表面的侧壁的所述副沟槽。
3.根据权利要求1所述的方法，其中所述掺杂方法从包括离子注入、等离子体辅助掺杂、经由CVD玻璃的掺杂、掺杂的选择性外延工艺、和p型或n型掺杂多晶硅的沉积的群组中选取。
4.根据权利要求1所述的方法，其中所述掺杂方法包括在所述副沟槽的侧壁上沉积掺杂层并且进行扩散工艺，所述掺杂层包括所述掺杂物。
5.根据权利要求1所述的方法，其中形成所述副沟槽包括刻蚀工艺以形成具有锥形侧壁的所述副沟槽。
6.根据权利要求1所述的方法，进一步包括：
形成填充所述副沟槽的牺牲材料；
在所述牺牲材料中形成第一开口；以及
通过掺杂邻近所述第一开口的衬底材料进行第一掺杂工艺以形成本体接触区域。
7.根据权利要求6所述的方法，进一步包括：
在所述牺牲材料中形成第二开口；以及
通过掺杂邻近所述第二开口的所述衬底材料进行第二掺杂工艺以形成源极区域。
8.根据权利要求1所述的方法，进一步包括：
用第一导电类型的掺杂物来掺杂邻近所述副沟槽的底侧的衬底部分以形成本体接触区域；以及
用第二导电类型的掺杂物来掺杂邻近所述主表面的衬底部分以形成所述源极区域。
9.根据权利要求1所述的方法，其中所述副沟槽具有近似等于所述栅极沟槽的所述深度的深度。
10.一种半导体器件，包括在具有主表面的半导体衬底中的晶体管，所述晶体管包括：
源极区域和漏极区域，所述源极区域和所述漏极区域中的每个区域被布置在所述主表面处；
在所述源极区域和所述漏极区域之间的沟道区域；
在所述主表面中的栅极沟槽，被布置在邻近的所述沟道区域之间；
在所述栅极沟槽中的栅极电极；以及
在所述主表面处的本体接触区域，所述本体接触区域接触所述沟道区域，
其中所述源极区域和所述本体接触区域被沿着与所述第一方向相交的第二方向交替地布置。
11.根据权利要求10所述的半导体器件，其中所述源极区域由第一导电类型的掺杂物掺杂，而所述本体接触区域由第二导电类型的掺杂物掺杂。
12.根据权利要求11所述的半导体器件，其中所述源极区域被电连接到所述本体接触区域。
13.根据权利要求10所述的半导体器件，其中所述栅极沟槽包括第一栅极沟槽和第二栅极沟槽，所述第一栅极沟槽被布置在所述源极区域处，所述第二栅极沟槽被布置在所述本体接触区域处。
14.根据权利要求13所述的半导体器件，其中所述第一栅极沟槽利用电连接到栅极端子的导电填充物进行填充。
15.根据权利要求14所述的半导体器件，其中所述第二栅极沟槽利用电连接到源极端子的导电填充物进行填充。
16.根据权利要求13所述的半导体器件，其中所述第二栅极沟槽利用绝缘材料进行填充。
17.根据权利要求10所述的半导体器件，进一步包括在所述沟道区域和所述漏极区域之间的漂移区。
18.根据权利要求10所述的半导体器件，其中所述第一栅极沟槽和所述第二栅极沟槽延伸到与所述源极接触近似相同的深度。
19.根据权利要求10所述的半导体器件，其中所述第一栅极沟槽和所述第二栅极沟槽延伸到与所述本体接触区域近似相同的深度。
20.一种集成电路，包括根据权利要求10所述的半导体器件。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745115A (zh) * 2020-05-27 2021-12-03 英飞凌科技奥地利有限公司 超结晶体管器件和用于形成超结晶体管器件的方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014114184B4 (de) * 2014-09-30 2018-07-05 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleitervorrichtung und Halbleitervorrichtung
DE102016104317B4 (de) 2015-04-14 2024-07-04 Infineon Technologies Ag Halbleitervorrichtung mit transistor einschliesslich eines bodykontaktteiles und herstellungsverfahren für die halbleitervorrichtung
DE102015109538B3 (de) * 2015-06-15 2016-12-08 Infineon Technologies Ag Transistor mit verbessertem Lawinendurchbruchsverhalten und Verfahren zur Herstellung
DE102016107714B4 (de) * 2015-08-14 2019-07-18 Infineon Technologies Dresden Gmbh Halbleitervorrichtung mit einer Transistorzelle, die einen Sourcekontakt in einem Graben umfasst, Verfahren zum Herstellen der Halbleitervorrichtung und integrierte Schaltung
US20210043735A1 (en) * 2016-04-07 2021-02-11 Abb Power Grids Switzerland Ag Short channel trench power mosfet and method
DE102016113393A1 (de) * 2016-07-20 2018-01-25 Infineon Technologies Ag Halbleitervorrichtung, die ein Transistor-Array und ein Abschlussgebiet enthält, und Verfahren zum Herstellen solch einer Halbleitervorrichtung
CN110828540B (zh) * 2018-08-10 2022-03-11 无锡华润上华科技有限公司 半导体器件及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252116A (ja) * 1996-03-14 1997-09-22 Sanyo Electric Co Ltd 半導体装置とその製造方法
WO2005045938A2 (en) * 2003-11-11 2005-05-19 Koninklijke Philips Electronics N.V. Insulated gate field-effect transistor
US20110156140A1 (en) * 2009-12-28 2011-06-30 Stmicroelectronics S.R.L. Method for manufacturing a power device being integrated on a semiconductor substrate, in particular having a field plate vertical structure and corresponding device
CN103378159A (zh) * 2012-04-20 2013-10-30 英飞凌科技奥地利有限公司 具有mosfet的晶体管装置和制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19743342C2 (de) 1997-09-30 2002-02-28 Infineon Technologies Ag Feldeffekttransistor hoher Packungsdichte und Verfahren zu seiner Herstellung
DE10313712B4 (de) * 2003-03-27 2008-04-03 Infineon Technologies Ag Laterales mittels Feldeffekt steuerbares Halbleiterbauelement für HF-Anwendungen
US7714384B2 (en) * 2003-09-15 2010-05-11 Seliskar John J Castellated gate MOSFET device capable of fully-depleted operation
DE102004063991B4 (de) 2004-10-29 2009-06-18 Infineon Technologies Ag Verfahren zur Herstellung von dotierten Halbleitergebieten in einem Halbleiterkörper eines lateralen Trenchtransistors
US8193559B2 (en) * 2009-01-27 2012-06-05 Infineon Technologies Austria Ag Monolithic semiconductor switches and method for manufacturing
US9396997B2 (en) * 2010-12-10 2016-07-19 Infineon Technologies Ag Method for producing a semiconductor component with insulated semiconductor mesas
US8587059B2 (en) * 2011-04-22 2013-11-19 Infineon Technologies Austria Ag Transistor arrangement with a MOSFET
DE102011087845B4 (de) * 2011-12-06 2015-07-02 Infineon Technologies Ag Laterales transistorbauelement und verfahren zu dessen herstellung
US9685511B2 (en) * 2012-05-21 2017-06-20 Infineon Technologies Austria Ag Semiconductor device and method for manufacturing a semiconductor device
US8921934B2 (en) * 2012-07-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with trench field plate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252116A (ja) * 1996-03-14 1997-09-22 Sanyo Electric Co Ltd 半導体装置とその製造方法
WO2005045938A2 (en) * 2003-11-11 2005-05-19 Koninklijke Philips Electronics N.V. Insulated gate field-effect transistor
US20110156140A1 (en) * 2009-12-28 2011-06-30 Stmicroelectronics S.R.L. Method for manufacturing a power device being integrated on a semiconductor substrate, in particular having a field plate vertical structure and corresponding device
CN103378159A (zh) * 2012-04-20 2013-10-30 英飞凌科技奥地利有限公司 具有mosfet的晶体管装置和制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745115A (zh) * 2020-05-27 2021-12-03 英飞凌科技奥地利有限公司 超结晶体管器件和用于形成超结晶体管器件的方法
US12034040B2 (en) 2020-05-27 2024-07-09 Infineon Technologies Austria Ag Superjunction transistor device and method for forming a superjunction transistor device

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