CN109950214A - 芯片级封装半导体器件及其制造方法 - Google Patents

芯片级封装半导体器件及其制造方法 Download PDF

Info

Publication number
CN109950214A
CN109950214A CN201711383469.8A CN201711383469A CN109950214A CN 109950214 A CN109950214 A CN 109950214A CN 201711383469 A CN201711383469 A CN 201711383469A CN 109950214 A CN109950214 A CN 109950214A
Authority
CN
China
Prior art keywords
carrier
main surface
wafer
semiconductor devices
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711383469.8A
Other languages
English (en)
Inventor
骆俊杰
邓添禧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yasuyo Co Ltd
Original Assignee
Yasuyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yasuyo Co Ltd filed Critical Yasuyo Co Ltd
Priority to CN201711383469.8A priority Critical patent/CN109950214A/zh
Priority to EP18202874.6A priority patent/EP3503177A1/en
Priority to US16/220,160 priority patent/US11817360B2/en
Publication of CN109950214A publication Critical patent/CN109950214A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本公开涉及一种半导体器件和一种制造半导体器件的方法。特别地，本公开涉及芯片级封装半导体器件，其包括：半导体晶片，其具有第一主表面和相对的第二主表面，所述半导体晶片包括布置在所述第二主表面上的至少两个端子；载体，其包括第一主表面和相对的第二主表面，其中所述半导体晶片的第一主表面被安装在所述载体的相对的第二主表面上；以及模塑材料，其部分地封装所述半导体晶片和所述载体，其中所述载体的第一主表面延伸并穿过模塑材料而暴露，并且所述至少两个端子在所述器件的第二侧面上穿过模塑材料而暴露。

Description

芯片级封装半导体器件及其制造方法
技术领域
本公开涉及一种半导体器件及其制造方法。特别地，本公开涉及一种芯片级封装半导体器件及相关的制造方法。
背景技术
芯片级封装(CSP)半导体器件对于要求小占用空间的应用正变得越来越重要。CSP通常用于例如移动通信装置，如移动电话和便携式电子装置。当CSP包括诸如晶体管或二极管的功率半导体器件时，它们需要高性能的热容量和散热性，因为它们需要将大电流排出到地或其他轨道，以保护与其连接的器件免受损坏。另一方面，功率器件面临着提升结构紧凑性的挑战，这一方面要求占用面积和封装高度非常小，另一方面要求通过封装材料进行保护。封装材料是保护器件免受诸如潮湿等环境因素影响所必要的。此外，封装材料防止用于将器件安装到印刷电路板上的焊膏与半导体晶片(die)的主体接触并潜在地使其短路。这种设置通常在器件的六个侧面上具有模塑材料，并被称为六面受保护CSP器件。
图1是传统的六面受保护CSP器件100的截面图。半导体器件100具有顶部主表面102和相对的底部主表面104。在底部主表面104上，CSP半导体器件100包括多个触点106、108。触点106、108电连接到半导体晶片110的底表面，并且连接到诸如印刷电路板(PCB)(未示出)的外部电路部件。触点106、108形成在半导体晶片110的表面上。
使用诸如基于环氧树脂的材料的任何适当的模塑化合物将半导体器件100封装在模塑材料116中。模塑材料116被布置为覆盖除触点106、108之外的半导体晶片110的全部六个侧面。
与没有模塑化合物的常规CSP半导体器件相比，常规的六面受保护CSP器件受如何驱散工作期间在半导体晶片中产生的热量的问题困扰。当半导体芯片是功率器件时，这特别受关注。
发明内容
根据实施例提供了一种芯片级封装半导体器件，其包括：半导体晶片，其具有第一主表面和相对的第二主表面，所述半导体晶片包括布置在所述第二主表面上的至少两个端子；载体，其包括第一主表面和相对的第二主表面，其中所述半导体晶片的第一主表面被安装在所述载体的相对的第二主表面上；以及模塑材料，其部分地封装所述半导体晶片和所述载体，其中所述载体的第一主表面延伸并穿过模塑材料而暴露，并且所述至少两个端子在所述器件的第二侧面上穿过模塑材料而暴露。
所述载体可在所述器件的相对侧壁上延伸并穿过所述模塑材料而暴露。
所述载体的第一主表面可与所述器件的顶部主表面上的模塑材料共面。
所述载体的相对的第二主表面可被布置为所述载体中的凹陷。所述凹陷可被布置为可安装地接收所述半导体晶片。所述凹陷可被布置为接收用于将所述半导体晶片安装到所述载体的粘合剂层。
所述封装半导体器件的顶部主表面可包括所述载体，并且所述封装半导体器件的第二相对主表面可包括所述端子和所述模塑材料。
根据实施例提供了一种制造芯片级封装半导体器件的方法，所述方法包括：提供具有第一主表面和相对的第二主表面的半导体晶片，所述半导体晶片包括布置在所述第二主表面上的至少两个端子；提供包括第一主表面和相对的第二主表面的载体；将所述半导体晶片的第一主表面安装到所述载体的相对的第二主表面上；将所述半导体晶片和所述载体部分地封装在模塑材料中，其中所述载体的第一主表面延伸并穿过模塑材料而暴露，并且所述至少两个端子在所述器件的第二侧面上穿过模塑材料而暴露。
所述半导体晶片和所述载体可被封装，使得所述载体的第一主表面与所述器件的顶部主表面上的模塑材料共面。
所述半导体晶片的第一主表面可被安装在布置在所述载体的相对的第二主表面上的凹陷中。
根据实施例的CSP半导体器件提供改进的散热和结构完整性，而不增加整个封装件的高度。根据实施例的CSP器件因此适合于高功率晶体管器件。
附图说明
为了能够详细理解本公开的特征，参照实施例进行更具体的描述，其中一些实施例在附图中示出。然而，应当注意，附图仅示出了典型的实施例，因此不应被认为是对其范围的限制。这些图用于帮助理解本公开，因此不一定按比例绘制。所要求保护的主题的优点对于本领域技术人员而言在结合附图阅读本说明书后将变得显而易见，其中相同的附图标记用于表示相同的元件，并且其中：
图1是已知的芯片级封装半导体器件的截面图；
图2a是根据实施例的芯片级封装半导体器件的截面图；
图2b是根据实施例的芯片级封装半导体器件的侧示图；
图2c是根据实施例的芯片级封装半导体器件的底示图；
图2d是根据实施例的芯片级封装半导体器件视图的顶示图；
图3a是根据实施例的包含多个半导体晶片的半导体器件的侧示图；
图3b是根据实施例的芯片级封装半导体器件的侧示图；
图4a示出了根据实施例的布置被布置在载体带上的框架的步骤；
图4b示出了根据实施例的被布置为重复的载体矩阵的框架；
图4c示出了根据实施例的在载体上布置半导体晶片的步骤；
图4d示出了根据实施例的封装附接到载体的半导体晶片的步骤；
图4e示出了根据实施例的封装之后去带的步骤；
图4f示出了根据实施例的去带之后去毛边的步骤；
图4g示出了根据实施例的产品标记的步骤；
图4h示出了根据实施例的载体上的示例产品标记；
图5a示出了根据实施例的用于封装CSP的包覆模塑处理；以及
图5b示出了根据实施例的包覆模塑之后的研磨处理。
具体实施方式
图2a是根据实施例的六面受保护芯片级封装(CSP)半导体器件200的截面图。CSP半导体器件200具有顶部主表面202和相对的底部主表面204。在底部主表面204上，CSP半导体器件200包括多个端子或触点206、208。端子206、208电连接到CSP半导体器件200的半导体晶片210的底表面，并且连接到未示出的诸如印刷电路板(PCB)的外部电路部件。触点206、208形成在半导体晶片210的表面上。
CSP半导体器件200的顶部主表面202包括用于支撑半导体晶片210的金属(或塑料)载体212。载体212通过任何适当的手段(例如，基于环氧树脂的粘合剂214)被固定地安装到半导体晶片210的顶表面。
虽然图2a示出了形成在半导体晶片210的底表面上的两个触点206、208，但是本领域技术人员将认识到，可以根据半导体晶片210的类型和功能提供任意数量的触点。例如，在半导体晶片是场效应晶体管的情况下，触点的数量可以是三个，其中各个触点连接到半导体晶片210的对应的源极端子、栅极端子、和漏极端子。可替代地，半导体晶片210也可以是双极结型晶体管、晶闸管、或双端二极管。此外，半导体晶片210的具有触点206、208的表面上可以包括钝化层217。
使用诸如基于环氧树脂的材料的任何适当的模塑化合物将CSP半导体器件200封装在模塑材料216中。该模塑材料可基本覆盖CSP半导体器件200的四个次要侧面。模塑材料216还可以形成为覆盖器件200的除触点206、208之外的底部主表面。模塑材料216可以被布置在器件200的顶部主表面202上，使得载体212的顶表面暴露。
载体212还可以包括一个或多个金属突片218，其从载体212的每一侧延伸以穿过模塑材料216突出，从而暴露在CSP半导体器件200的相对侧。突片218是CSP半导体器件200的分割(singulation)处理的产物，这将在下面更详细地讨论。
图2b中示出了CSP半导体器件200的侧示图，其示出了在器件200的侧面上突出穿过模塑材料216的突片218。图2b示出了器件200的一个侧面，并且本领域技术人员将认识到，由于如下所述的载体的矩阵布置，相应的相对侧面将具有突出穿过模塑材料216的突片218的相同布置。
图2c示出了CSP半导体器件200的底示图，并且示出了布置在器件200的底表面204上的触点206、208和模塑材料216。图2d示出了CSP半导体器件200的顶示图，并且示出了载体212突出穿过模塑材料216，使得该载体暴露在器件200的顶表面202上。可以在载体212上布置可选倒角222，其可以用于指示接触极性并在将器件放置在PCB上时辅助器件定向。
载体212的突出穿过器件200的顶表面202并且还穿过相对的侧壁的布置方式提供了器件200的改进的热特性。充当散热器的载体被暴露，而不是被模塑材料所覆盖，从而在器件工作期间晶片中产生的任何热量都可以被有效地从半导体晶片210中驱散。在器件是高功率器件的情况下，这可以是特别有利的。
此外，如以下关于制造方法的更详细讨论所述，相比于常规器件，器件200中的载体212的布置方式被设置为不增加器件200的总封装高度。
此外，载体212还通过支撑半导体晶片210来为器件200提供机械强度。这在器件200用于恶劣的环境条件下时(例如，在汽车应用中)特别有利。
图3a示出了多晶片CSP半导体器件300的实施例，其中多个半导体晶片310a、310b被布置在CSP半导体器件300中。与之前的实施例一样，使用例如基于环氧树脂的粘合剂将晶片固定到载体312。模塑材料316被布置为分隔多个晶片310a、310b。在以例如共源共栅、或半桥配置来布置半导体晶片310a、310b时，这种布置方式可以是有利的。
图3b示出了一个实施例，其中载体312包括用于容纳粘合剂314和/或半导体晶片310的上部的凹陷部。在图3b的实施例中，载体312的凹陷部的尺寸为适合于接收布置在其上的半导体晶片310和粘合剂314。可替代地，载体312的凹陷部324的尺寸可为适合于接收布置在半导体晶片310上的粘合剂314。图3b的布置方式可以有利于降低器件300的总封装高度。此外，通过将粘合剂314容纳在载体312的凹陷324内可以防止粘合剂渗出。本领域技术人员还将理解，图3b的实施例也适用于诸如图3a的布置的多晶片布置。
现在将参考示出示例处理步骤的图4a至图4h来描述用于制造根据上述实施例的半导体器件的示例处理流程。
参照图4a，金属框架411被布置在载体带413上。载体带413防止模塑材料在模塑处理过程中覆盖载体，并确保(如上参照图2a和图2d所讨论的)载体412被暴露并突出穿过器件400的顶表面402。金属框架包括重复的载体412的矩阵，其中相邻的载体通过连接构件418或系杆互相连接。由连接构件418互相连接的载体矩阵可以是线性矩阵。可替代地，并且如图4b的平面图所示，载体矩阵可以是n×m矩阵，其中n是矩阵中的行数，m是矩阵中的列数，其中n和m均为正整数，相邻的载体412通过连接构件418连接。图4b的示例示出了连接任何行或列中的相邻载体的一个连接构件418。然而，与图2b的示例一样，本领域技术人员将理解，器件的任何一个侧面上的连接构件418的数量都可以大于一个。
如图4c所示，然后利用晶片附接材料414(例如，如之前提及的基于环氧树脂的粘合剂、或任何合适的焊料或胶粘剂)将半导体晶片410附接至各自的载体412。在某些应用中，晶片附接材料可以是导电的，以实现从载体412到半导体晶片410的电连接。应当注意，半导体晶片410从顶部向下附接到载体412。换句话说，使用粘合剂414将半导体晶片410的顶部主表面(即，与具有触点406、408的表面相对的主表面)固定到相应的载体。然后可以通过热固化来固定或凝固粘合剂。
在上面讨论的半导体晶片410的附接处理之后，对半导体晶片被附接至载体的布置进行封装。图4d示出了被称为膜辅助模塑(FAM)的封装处理，其中将保护膜417施加在附接的或固定的晶片矩阵上。然后将矩阵装入模塑机中，其中将液化的模塑材料迫使进入由保护膜417和载体带413形成的封闭模腔中。然后通过固化使模塑材料凝固。
当将模塑的矩阵从模塑机中取出时，保护膜417也被去除。在模塑处理之后，矩阵还可以进行被称为后模固化的处理以进一步固化和凝固液化的模塑材料。
在模塑和固化之后，如图4e所示，通过被称为去带(de-taping)的处理将载体带从模塑矩阵上去除。在去带完成后，如图4f所示，通过被称为去毛边的处理，去除存在于触点上或载体的被暴露的侧面上的任何多余的模塑材料。一旦完成去毛边，如图4g所示，可以使用例如激光在载体的被暴露的侧面上标记器件细节(例如，产品类型)。载体上的产品标记例如如图4h所示。
作为上述FAM处理的替代方案，可以使用如图5a和图5b所示的包覆模塑(over-moulding)处理来实现模塑。在该包覆模塑过程中，模塑材料516被布置为完全覆盖半导体晶片510，包括布置在其上的触点。在模塑材料516固化之后，使用研磨处理去除模塑材料，直到触点暴露。
在标记之后，通过分割将各个CSP半导体器件400从矩阵布置中分离出来。分割沿着半导体器件400的侧壁进行。为了分离器件400，分割处理可以是任何合适的切割处理，例如激光切割、等离子切割、锯切、或它们的任何组合。分割步骤切断了相邻器件400的连接构件418和模塑材料416。这导致如上面关于图2a所讨论的突片218在器件400的侧壁处延伸穿过的模塑材料416。
在分割之后，可以对器件进行电测试以确保它们在封装处理过程中没有被损坏。在测试之后，可以将器件放置在载体带上并装载在卷轴上以准备运输。
根据实施例的CSP半导体器件提供改进的散热和结构完整性，而不增加整个封装件的高度。根据实施例的CSP器件因此适合于高功率晶体管器件。
本发明的特定和优选方面在所附的独立权利要求中阐述。来自从属权利要求和/或独立权利要求的特征的组合可以适当地组合，而不仅仅如权利要求中所阐述的那样。
本公开的范围包括任何新颖特征或其中明确或隐含地公开的特征组合、或其任何概括，而不管其是否涉及要求保护的发明或缓解本发明所解决的任何或所有问题。申请人特此通知，在本申请或由此衍生的任何此类进一步申请期间，可以对这些特征提出新的权利要求。特别地，参考所附权利要求书，来自从属权利要求的特征可以与独立权利要求的特征组合，并且来自各个独立权利要求的特征可以以任何适当的方式组合，而不仅仅以权利要求中列举的特定组合。
在不同实施例的上下文中描述的特征也可以在单个实施例中组合提供。相反地，为了简洁起见而在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合来提供。
术语“包括”不排除其他元件或步骤，术语“一”或“一个”不排除多个。权利要求中的附图标记不应被解释为限制权利要求的范围。

Claims (10)

1.一种芯片级封装半导体器件，包括：
半导体晶片，其具有第一主表面和相对的第二主表面，所述半导体晶片包括布置在所述第二主表面上的至少两个端子；
载体，其包括第一主表面和相对的第二主表面，
其中所述半导体晶片的第一主表面被安装在所述载体的相对的第二主表面上；以及
模塑材料，其部分地封装所述半导体晶片和所述载体，其中所述载体的第一主表面延伸并穿过模塑材料而暴露，并且所述至少两个端子在所述器件的第二侧面上穿过模塑材料而暴露。
2.根据权利要求1所述的芯片级封装半导体器件，其中所述载体在所述器件的相对侧壁上延伸并穿过所述模塑材料而暴露。
3.根据权利要求1所述的芯片级封装半导体器件，其中所述载体的第一主表面与所述器件的顶部主表面上的模塑材料共面。
4.根据前述权利要求中任一项所述的芯片级封装半导体器件，其中所述载体的相对的第二主表面被布置为所述载体中的凹陷。
5.根据权利要求4所述的芯片级封装半导体器件，其中所述凹陷被布置为可安装地接收所述半导体晶片。
6.根据权利要求4所述的芯片级封装半导体器件，其中所述凹陷被布置为接收用于将所述半导体晶片安装到所述载体的粘合剂层。
7.根据前述权利要求中任一项所述的芯片级封装半导体器件，其中所述封装半导体器件的顶部主表面包括所述载体，并且所述封装半导体器件的第二相对主表面包括所述端子和所述模塑材料。
8.一种制造芯片级封装半导体器件的方法，所述方法包括：
提供具有第一主表面和相对的第二主表面的半导体晶片，所述半导体晶片包括布置在所述第二主表面上的至少两个端子；
提供包括第一主表面和相对的第二主表面的载体；
将所述半导体晶片的第一主表面安装到所述载体的相对的第二主表面上；
将所述半导体晶片和所述载体部分地封装在模塑材料中，其中所述载体的第一主表面延伸并穿过模塑材料而暴露，并且所述至少两个端子在所述器件的第二侧面上穿过模塑材料而暴露。
9.根据权利要求8所述的方法，其中所述半导体晶片和所述载体被封装，使得所述载体的第一主表面与所述器件的顶部主表面上的模塑材料共面。
10.根据权利要求8或9所述的方法，其中所述半导体晶片的第一主表面被安装在布置在所述载体的相对的第二主表面上的凹陷中。
CN201711383469.8A 2017-12-20 2017-12-20 芯片级封装半导体器件及其制造方法 Pending CN109950214A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201711383469.8A CN109950214A (zh) 2017-12-20 2017-12-20 芯片级封装半导体器件及其制造方法
EP18202874.6A EP3503177A1 (en) 2017-12-20 2018-10-26 Carrier protected chip scale package
US16/220,160 US11817360B2 (en) 2017-12-20 2018-12-14 Chip scale package semiconductor device and method of manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711383469.8A CN109950214A (zh) 2017-12-20 2017-12-20 芯片级封装半导体器件及其制造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202410396027.0A Division CN118263196A (zh) 2017-12-20 芯片级封装半导体器件及其制造方法

Publications (1)

Publication Number Publication Date
CN109950214A true CN109950214A (zh) 2019-06-28

Family

ID=64082888

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711383469.8A Pending CN109950214A (zh) 2017-12-20 2017-12-20 芯片级封装半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US11817360B2 (zh)
EP (1) EP3503177A1 (zh)
CN (1) CN109950214A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11018030B2 (en) * 2019-03-20 2021-05-25 Semiconductor Components Industries, Llc Fan-out wafer level chip-scale packages and methods of manufacture

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6707148B1 (en) * 2002-05-21 2004-03-16 National Semiconductor Corporation Bumped integrated circuits for optical applications
US20130037917A1 (en) * 2011-08-09 2013-02-14 Yan Xun Xue Wafer level chip scale package with thick bottom metal exposed and preparation method thereof
US20130187284A1 (en) * 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
US20140264802A1 (en) * 2013-03-12 2014-09-18 Hamza Yilmaz Semiconductor Device with Thick Bottom Metal and Preparation Method Thereof
US20150262972A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
CN105870080A (zh) * 2015-02-09 2016-08-17 株式会社吉帝伟士 半导体装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970010678B1 (ko) * 1994-03-30 1997-06-30 엘지반도체 주식회사 리드 프레임 및 이를 이용한 반도체 패키지
JPH09260568A (ja) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP3842444B2 (ja) * 1998-07-24 2006-11-08 富士通株式会社 半導体装置の製造方法
US6495944B2 (en) * 2001-04-18 2002-12-17 International Business Machines Corporation Electrostatic microactuator with viscous liquid damping
US6709897B2 (en) * 2002-01-15 2004-03-23 Unimicron Technology Corp. Method of forming IC package having upward-facing chip cavity
JP3844467B2 (ja) * 2003-01-08 2006-11-15 沖電気工業株式会社 半導体装置及びその製造方法
WO2006035321A2 (en) * 2004-05-06 2006-04-06 United Test And Assembly Center, Ltd. Structurally-enhanced integrated circuit package and method of manufacture
JP2006339354A (ja) * 2005-06-01 2006-12-14 Tdk Corp 半導体ｉｃ及びその製造方法、並びに、半導体ｉｃ内蔵モジュール及びその製造方法
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface
US7476980B2 (en) * 2006-06-27 2009-01-13 Infineon Technologies Ag Die configurations and methods of manufacture
US7968378B2 (en) * 2008-02-06 2011-06-28 Infineon Technologies Ag Electronic device
KR101009130B1 (ko) * 2009-02-05 2011-01-18 삼성전기주식회사 웨이퍼 레벨 방열 패키지 및 그 제조방법
US10373870B2 (en) * 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US8288203B2 (en) * 2011-02-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump
US8610286B2 (en) * 2011-12-08 2013-12-17 Stats Chippac, Ltd. Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP
KR20160143264A (ko) * 2015-06-05 2016-12-14 주식회사 에스에프에이반도체 팬-아웃 웨이퍼 레벨 패키지 및 그 제조방법
JP6605382B2 (ja) * 2016-03-30 2019-11-13 新光電気工業株式会社 半導体装置及び半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6707148B1 (en) * 2002-05-21 2004-03-16 National Semiconductor Corporation Bumped integrated circuits for optical applications
US20130037917A1 (en) * 2011-08-09 2013-02-14 Yan Xun Xue Wafer level chip scale package with thick bottom metal exposed and preparation method thereof
US20130187284A1 (en) * 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
US20140264802A1 (en) * 2013-03-12 2014-09-18 Hamza Yilmaz Semiconductor Device with Thick Bottom Metal and Preparation Method Thereof
US20150262972A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
CN105870080A (zh) * 2015-02-09 2016-08-17 株式会社吉帝伟士 半导体装置

Also Published As

Publication number Publication date
US11817360B2 (en) 2023-11-14
US20190189530A1 (en) 2019-06-20
EP3503177A1 (en) 2019-06-26

Similar Documents

Publication Publication Date Title
US20070132091A1 (en) Thermal enhanced upper and dual heat sink exposed molded leadless package
US7683461B2 (en) Integrated circuit leadless package system
US20040124508A1 (en) High performance chip scale leadframe package and method of manufacturing the package
US20160379916A1 (en) Method for making semiconductor device with sidewall recess and related devices
US8766430B2 (en) Semiconductor modules and methods of formation thereof
KR101440933B1 (ko) 범프 기술을 이용하는 ｉｃ 패키지 시스템
CN110473858A (zh) 半导体封装及其制造方法
US9147600B2 (en) Packages for multiple semiconductor chips
CN101312177A (zh) 用于半导体器件的引线框
US11393699B2 (en) Packaging process for plating with selective molding
US10256168B2 (en) Semiconductor device and lead frame therefor
US11538742B2 (en) Packaged multichip module with conductive connectors
US10529680B2 (en) Encapsulated electronic device mounted on a redistribution layer
CN109950214A (zh) 芯片级封装半导体器件及其制造方法
CN106847780B (zh) 框架具有多个臂的半导体器件及相关方法
CN212625552U (zh) 半导体芯片封装结构与电子设备
US11605959B2 (en) Battery control system-in-package and method of fabricating the same
KR102225628B1 (ko) 고방열 플라스틱 큐에프엔 패키지
JP5302234B2 (ja) 半導体装置
US11984388B2 (en) Semiconductor package structures and methods of manufacture
CN118263196A (zh) 芯片级封装半导体器件及其制造方法
US20230402355A1 (en) Electronic package with heatsink and manufacturing method therefor
CN218123390U (zh) 引线框架、封装结构及电子设备
US20230178428A1 (en) Leaded semiconductor package formation using lead frame with structured central pad
KR20180062479A (ko) 반도체 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination