CN109935634A - 集成在超级结功率mosfet中的肖特基二极管 - Google Patents
集成在超级结功率mosfet中的肖特基二极管 Download PDFInfo
- Publication number
- CN109935634A CN109935634A CN201811393031.2A CN201811393031A CN109935634A CN 109935634 A CN109935634 A CN 109935634A CN 201811393031 A CN201811393031 A CN 201811393031A CN 109935634 A CN109935634 A CN 109935634A
- Authority
- CN
- China
- Prior art keywords
- schottky
- gate trench
- drift region
- region
- conduction type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims abstract description 7
- 238000002347 injection Methods 0.000 claims description 25
- 239000007924 injection Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 21
- 238000002360 preparation method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 239000000463 material Substances 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 11
- 239000002019 doping agent Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001802 infusion Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 239000004327 boric acid Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/086—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- High Energy & Nuclear Physics (AREA)
- Composite Materials (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
一种沟槽金属‑氧化物‑半导体场效应晶体管(MOSFET)器件,包括一个有源晶胞区,有源晶胞区包括多个超级结沟槽功率MOSFET,肖特基二极管区包括多个肖特基二极管,形成在具有超级结结构的漂流区中。每个集成的肖特基二极管都包括一个肖特基接头,在轻掺杂的半导体层和金属层之间。
Description
技术领域
本发明主要涉及金属-氧化物-半导体场效应晶体管(MOMSFET),更确切地说是一种超级结功率MOSFET及其制备方法。
背景技术
微处理器和存储器件等集成电路含有多个金属-氧化物-半导体场效应晶体管(MOSFET)。MOSFET通常用于需要功率切换和功率放大的应用中。用于功率开关的MOSFET器件有时称为功率MOSFET。大多数的功率MOSFET的特点是在填充多晶硅的栅极沟槽的对边上具有一个带有源极和漏极区的垂直结构,作为栅极电极。
功率MOSFET器件通常包括多个单独的MOSFET结构,排布在有源晶胞中。肖特基二极管通常用于低压功率MOSFET器件(例如小于40伏)。它们有助于改善器件开关动作的二极管恢复部分,并且由于它们较低的正向电压,从而可以降低功率损耗。另外,在某些应用中(例如直流-直流转换器),MOSFET快速的接通和断开可以产生带有电压尖峰的开关节点振铃。钳位到MOSFET器件的肖特基二极管可以减少这种电压尖峰。
另一方面,超级结结构已经用于高压功率MOSFET器件(例如500伏以上),以获得很低的导通电阻(Rds-on),同时保持很高的断开状态击穿电压(BV)。在一个功率MOSFET中,必须降低传导时的器件电阻(Rds-on),提高其击穿电压(BV)。然而,导通电阻(Rds-on)和击穿电压(BV)处于一种相互制约的关系。也就是说,对于传统的晶体管来说,随着击穿电压(BV)的增大,导通电阻(Rds-on)也会剧烈增大。由于超级结器件包括交替的p-型和n-型掺杂立柱,平行排布,并且在漂流区中相互连接,当漏极和源极之间加载反向偏压时,这些电荷平衡的立柱在水平方向上相互耗尽。因此,超级结器件可以在垂直方向上承受很高的击穿电压,同时在相同的击穿电压下,具有比传统的MOSFET器件低得多的导通电阻(Rds-on)(或者在指定的导通电阻Rds-on下,具有比传统的MOSFET器件高得多的击穿电压BV)。
正是在这样的背景下,提出了本发明的实施例。
发明内容
本发明的目的在于提出一种集成在超级结功率MOSFET中的肖特基二极管,以改善现有技术中的一个或多个问题。
本发明的一个方面在于提出一种金属-氧化物-半导体场效应晶体管(MOSFET)器件,包括:
一个有源晶胞区,包括多个超级结沟槽MOSFET,其中有源晶胞区包括:
一个第一导电类型的轻掺杂漂流区,位于相同导电类型的重掺杂衬底上方;
一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;
多个栅极沟槽,位于本体区中,并延伸到漂流区内,其中多个栅极沟槽中的每个栅极沟槽都内衬电介质材料,栅极沟槽包括一个栅极电极;
一个第一导电类型的重掺杂源极区,位于本体区中;
一个源极接头,位于源极接触沟槽中,延伸到两个相邻的栅极沟槽之间的本体区;以及
一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第二掺杂立柱位于每个源极接触沟槽的底部附近;以及
一个肖特基二极管区,包括多个肖特基二极管形成在具有超级结结构的漂流区中,每个肖特基二极管都包括一个肖特基接头,在轻掺杂的半导体层和金属层之间。
其中,肖特基接头沿肖特基接触沟槽的一部分垂直侧壁形成。
其中,肖特基接头形成在相邻的第二掺杂立柱之间的轻掺杂漂流区的表面上。
其中,肖特基接触沟槽比多个源极接触沟槽中的每个源极接触沟槽都宽。
其中,肖特基接触沟槽的宽度约为0.5至0.7微米。
其中,肖特基接触沟槽和相邻的栅极沟槽之间的缝隙小于0.2微米。
其中,器件的工作电压在8V至40V之间,多个栅极沟槽的每个栅极沟槽的间距在1.3至1.7微米之间。
其中,器件的工作电压为30V,多个栅极沟槽的每个栅极沟槽的间距在1.3至1.7微米之间。
其中,器件的工作电压高于100V,多个栅极沟槽的每个栅极沟槽的间距在3.5至5微米之间。
其中,多个栅极沟槽的每个栅极沟槽都包括一个在顶部的栅极电极以及一个在底部的屏蔽电极。
其中,形成肖特基接头的表面是凹陷的。
本发明的另一个方面在于提出一种沟槽金属-氧化物-半导体场效应晶体管(MOSFET)器件的制备方法,该方法包括:
制备一个有源晶胞区,包括多个超级结沟槽功率MOSFET,其中制备有源晶胞区包括:
制备一个第一导电类型的漂流区,位于相同导电类型的重掺杂衬底上方;
制备一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;
制备多个栅极沟槽,位于本体区中,并延伸到漂流区内,其中内衬电介质材料的多个栅极沟槽的每个栅极沟槽都含有一个栅极电极;
制备一个第一导电类型的重掺杂源极区,位于本体区中;
制备一个源极接头,在源极接触沟槽中,延伸到两个相邻的栅极沟槽之间的本体区;并且
制备一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第二掺杂立柱的每个立柱都位于每个源极接触沟槽的底部附近;并且
制备多个肖特基二极管,在肖特基二极管区中具有超级结结构的漂流区中,每个肖特基二极管都包括一个肖特基接头,在轻掺杂半导体层和金属层之间。
其中,肖特基接头沿肖特基接触沟槽的一部分垂直侧壁形成。
其中,肖特基接头形成在相邻的第二掺杂立柱之间的轻掺杂漂流区的表面上。
其中,肖特基接触沟槽比多个源极接触沟槽的每个源极接触沟槽都宽。
其中,肖特基接触沟槽和相邻的栅极沟槽之间的缝隙小于0.2微米。
其中,制备多个栅极沟槽包括在漂流区上使用一个栅极沟槽掩膜,不覆盖有源晶胞区中的栅极沟槽开口以及肖特基二极管区中的栅极沟槽开口的位置。
其中,制备多个栅极沟槽包括在漂流区上使用一个栅极沟槽掩膜,不覆盖有源晶胞区中的栅极沟槽开口的位置,覆盖肖特基二极管区的整个部分。
其中,制备一个本体区包括使用一个本体掩膜,覆盖着肖特基二极管区的整个部分,留下有源晶胞区不覆盖。
其中,制备一个源极区包括使用一个本体掩膜,覆盖着肖特基二极管区的整个部分,留下有源晶胞区不覆盖。
其中,制备多个肖特基二极管包括在每个肖特基接触沟槽下方,制备一个接触注入区,其中通过肖特基接触沟槽开口,利用带角度的注入,制备接触注入区。
其中,制备多个肖特基二极管包括在每个肖特基接触沟槽下方,制备一个接触注入区,其中通过肖特基接触沟槽开口,利用香农注入,制备接触注入区。
阅读以下详细说明的实施例并参照各种附图,本发明的这些特点和优势对于本领域的技术人员来说,无疑将显而易见。
附图说明
阅读以下详细说明并参照附图之后,本发明的各个方面及优势将显而易见:
图1表示依据本发明的各个方面,一部分功率MOSFET器件的俯视图。
图2表示依据本发明的各个方面,一部分功率MOSFET器件的剖面图。
图3表示依据本发明的各个方面,一部分功率MOSFET器件的剖面图。
图4表示依据本发明的各个方面,一部分功率MOSFET器件的剖面图。
图5表示依据本发明的各个方面,一部分功率MOSFET器件的剖面图。
图6表示依据本发明的各个方面,一种功率MOSFET器件的制备流程图。
具体实施方式
在以下说明中,参照附图,该附图形成了本发明的一部分,并且在其中表示出了可以实施本发明的图示特定实施例的方式。为方便起见,在特定的导电或净杂质载流子类型(P或N)之后使用+或-,通常指的是半导体材料中指定类型的净杂质载流子的相对浓度。一般而言,n+材料具有比n材料更高的n型净掺杂物(例如,电子)浓度,并且n材料具有比n材料更高的载流子浓度。与之类似,p+材料具有比p材料更高的p型净掺杂物(例如空穴)浓度,并且p材料具有比p材料更高的浓度。要注意的是,相关的是载流子的净浓度,而不一定是掺杂物。例如,材料可以重掺杂n-型掺杂物,但是如果材料也充分反向掺杂p-型掺杂物,那么仍然具有相对低的净载流子浓度。此处所用的掺杂物浓度小于1016/cm3可以认为是“轻掺杂”,掺杂物浓度大于1017/cm3可以认为是“重掺杂”。此处所使用的高压器件是指工作电压为400V以上的器件。中压器件是指工作电压在40V至400V之间的器件,低压器件是指工作电压低于40V的器件,最好是在8V至40V之间。
引言
虽然超级结器件通常用于高压应用,但是人们已经提议它们也可以用于低压应用。在一个示例中,超级结器件可以用于低压热插拔应用。热插拔时,漏极和源极之间相对很高的电压以及高电流会导致器件发生故障。超级结结构有助于降低来自沟槽电极的高电场,从而防止击穿,并提高性能。
本发明的各个方面提出了与超级结功率MOSFET器件集成在一起的肖特基二极管,可以用于低压应用以及中压或高压应用。肖特基二极管可以降低体二极管正向电压降(Vf)并且使存储的电荷最少,具有快速的反向恢复时间,从而使MOSFET器件更加高效。依据本发明的各个方面,肖特基接头可以沿肖特基接触沟槽的侧壁形成。依据本发明的其他方面,肖特基接头可以形成在轻掺杂的半导体层的表面上,在超级结结构的p立柱之间。
图1表示依据本发明的各个方面,一部分功率MOSFET器件的俯视图。功率MOSFET器件100包括一个有源晶胞区110和一个肖特基二极管区120。在某些实施例中,有源晶胞区110和肖特基二极管区120包含在功率MOSFET器件中的有源晶胞区中。有源晶胞区110包括带有超级结结构的器件晶胞的一个阵列。器件中的每个器件晶胞都具有一个栅极电极,在器件沟槽(或栅极沟槽)中。栅极电极可以通过栅极滑道132连接到栅极垫130。器件晶胞的源极区可以连接到有源晶胞区110内的源极垫(图中没有表示出)。肖特基二极管区120具有多个肖特基二极管。肖特基二极管可以连接到栅极垫130和源极垫,在有源晶胞区110中,用于合适的连接。肖特基二极管的面积小于器件晶胞的面积。作为示例,但不作为局限,肖特基二极管的面积(即肖特基二极管区120)约为功率MOSFET器件100的整个有源晶胞区面积的10%至15%。要注意的是,图1表示依据本发明的一个方面,功率MOSFET器件的一种可能的布局。本发明的其他方面包括可选的器件布局。在某些实施例中,包括多个肖特基二极管区,包围着多个有源晶胞区110。在某些实施例中,多个肖特基二极管区位于有源晶胞区110中。另外,栅极电极可以呈条形,但是本发明的可选方面还包括可选的器件布局,例如但不局限于封闭的晶胞方向。
在以下示例中,功率MOSFET器件表示为一个n-型超级结沟槽MOSFET器件,其中器件晶胞的源极区和漏极区具有n型导电类型,本体区具有p型导电类型。要注意的是,这些导电类型可以相反,以获得p-型超级结沟槽MOSFET。还要注意的是,依据本发明的各个方面,功率MOSFET器件可以是一个单独的多晶硅MOSFET器件或一个屏蔽栅沟槽MOSFET器件。
第一个示例
图2表示依据本发明的一部分功率MOSFET器件的剖面图。图2所示的n-型功率MOSFET器件200包括一个有源晶胞区200a和一个肖特基二极管区200b。有源晶胞区200a由一个器件晶胞的阵列组成。每个器件晶胞都包括一个n-型轻掺杂的漂流区204,在重掺杂的n-型半导体衬底202上方,以及一个形成在漂流区204顶部附近的p-型本体区206。另外,器件晶胞包括一个栅极电极212,形成在栅极沟槽210中,在本体区206和漂流区204中延伸,以及一个重掺杂的n-型源极区208,形成在本体区206的顶部附近,在源极接触沟槽230a的对边上。形成在源极接触沟槽230a中的源极接头(图中没有表示出)提供了一个到源极区208的外部接头。栅极电极212通过电介质层216,与源极接头(图中没有表示出)电绝缘。
功率MOSFET器件200具有一个在漂流区中的超级结结构,包括交替的第一导电类型的第一掺杂立柱(即n立柱)和平行排布的第二导电类型的第二掺杂立柱(即p立柱)。每个p立柱220都形成在源极接触沟槽230a下方,以及两个相邻的栅极沟槽210之间。N立柱可以包括n漂流区204位于p立柱220附近的那一部分。
与有源晶胞区200a类似,肖特基二极管区200b可以包括n+衬底202、位于衬底202上方的n漂流区204、形成在内衬电介质材料214的栅极沟槽210中的栅极电极212以及一个形成在栅极沟槽210上的绝缘层216。肖特基二极管区200b还包括超级结结构,具有交替的p掺杂立柱220和n掺杂立柱。一个p立柱220形成在漂流区204中的两个相邻的栅极沟槽210之间。N立柱可以包括位于p立柱220附近的那部分n漂流区204。
肖特基接触沟槽230b形成在漂流区204中,在p立柱220上方的两个相邻的栅极沟槽之间。接触注入物232形成在肖特基接触沟槽230b底部下方。势垒金属(图中没有表示出)可以沉积在肖特基接触沟槽230b的表面上方。作为示例,但不作为局限,势垒金属可以是通过物理气相沉积(PVD)的钛(Ti),或者是通过CVD或PVD沉积的TiN等合金。沉积势垒金属之后,可以通过CVD,在肖特基接触沟槽230b中沉积导电材料(钨)。一旦沉积了一层钨之后,可以回刻,以便保留源极接触沟槽230a和肖特基接触沟槽230b中的钨。肖特基接头可以形成在肖特基沟槽230b的侧壁上。在整个表面上沉积金属,并形成图案,以便为源极区和栅极电极提供合适的接头。
可以调节肖特基接触沟槽230b的宽度,以微调漏电流(Idss)。当肖特基接触沟槽230b较宽时,肖特基沟槽230b和栅极沟槽210之间的缝隙较窄。因此,可以降低漏电流。肖特基接触沟槽230b比形成在有源晶胞区200a中的源极接触沟槽230a更宽。作为示例,但不作为局限,有源晶胞区200a中的源极接触沟槽230a可以具有0.4微米的宽度,对于1.4微米的间距尺寸来说,肖特基接触沟槽230b的宽度约为0.5至0.7微米。在某些实施例中,肖特基接触沟槽230b和栅极沟槽210之间的缝隙可以小于0.2微米。另外,对于低压器件(例如25V)来说,栅极沟槽的间距可以在1.3至1.5微米之间,对于30V的器件来说,间距在1.3至1.7微米之间,对于中压器件(例如200V)来说,间距在3.5至5微米之间。P立柱的间距与器件栅极沟槽的间距相等。与肖特基二极管集成之后,功率MOSFET器件就可以具有很低的体二极管正向电压降(Vf),在0.35至0.45V之间。
图2所示的功率MOSFET200表示为一个单独的多晶硅MOSFET器件。本发明的各个方面还使用了如图3所示的屏蔽栅沟槽MOSFET器件。确切地说,功率MOSFET器件300与图2所示的器件200类似,除了功率MOSFET器件300中的栅极沟槽310具有一个在沟槽顶部的栅极电极312a以及一个在栅极沟槽底部的屏蔽电极312b。这种屏蔽栅沟槽(SGT)结构允许很低的栅极电荷和很高的开关频率。图3和图2所示的一致的数字符号代表一样的部件/元件或等效器件。这些一致的部件的详细说明在此不再赘述,以便简便。如图3所示,肖特基接头形成在肖特基接触沟槽230b的侧壁上。
第二个示例
图4表示依据本发明的各个方面,一部分功率MOSFET器件400的剖面图。图4所示的n-型功率MOSFET器件400包括一个有源晶胞区400a和一个肖特基二极管区400b。有源晶胞区400a包括一个器件晶胞的阵列,与图2所示的器件晶胞类似。图4和图2所示的一致的数字符号代表一样的部件/元件或等效器件。这些一致的部件的详细说明在此不再赘述,以便简便。虽然图4所示的有源晶胞区400a中每个器件晶胞都具有一个单独的栅极多晶硅在栅极沟槽210中,要注意的是,器件晶胞可以选择具有一个SGT结构,即一个在栅极沟槽顶部的栅极电极以及一个在沟槽底部的屏蔽电极。
肖特基二极管区400b可以包括n+衬底202、位于衬底202上方的n漂流区204、形成在漂流区202顶部附近的p-型本体区206以及一个形成在本体区206上的绝缘层216。肖特基二极管区400b还包括超级结结构,具有交替的p掺杂立柱220和n掺杂立柱。P立柱220形成在漂流区204中的p型本体区206下方。N立柱可以由位于p立柱220附近的那部分n漂流区204构成。
肖特基接触构成430形成在漂流区204上方的两个相邻的p立柱220之间。势垒金属(图中没有表示出)可以沉积在肖特基接头430的表面上,然后在接触沟槽中沉积钨。肖特基接头可以形成在漂流区204的表面上,在两个相邻的p立柱220之间。金属可以沉积在整个表面上,以便为源极区和栅极电极提供合适的接头。
图5表示集成在功率MOSFET器件中的另一个肖特基二极管,肖特基接头也形成在两个相邻的p立柱之间的漂流区的表面上。确切地说,功率MOSFET器件500与图4所示的器件400类似,除了肖特基二极管区500b中的肖特基接触沟槽530延伸到漂流区204的顶部中。图5和图4所示的一致的数字符号代表一样的部件/元件或等效器件。这些一致的部件的详细说明在此不再赘述,以便简便。
对于该实施例来说,对于低压器件(例如25V)来说,栅极沟槽的间距可以在1.3至1.5微米之间,对于30V的器件来说,间距在1.3至1.7微米之间,对于中压器件(例如200V)来说,间距在3.5至5微米之间。P立柱的间距与器件栅极沟槽的间距相等。与肖特基二极管集成之后,功率MOSFET器件就可以具有很低的体二极管正向电压降(Vf),在0.35至0.45V之间。
制备工艺
图6表示依据本发明的各个方面,用于低压功率MOSFET器件的制备工艺的流程图。以下的制备工艺提出了用于制备一种n-型超级结沟槽MOSFET器件的工艺,其中器件晶胞的源极区和漏极区具有n型导电类型,本体区具有p型导电类型。要注意的是,这些导电类型可以反向,以便制备p型超级结沟槽MOSFET。
制备工艺从轻掺杂的n-型外延层(即漂流区)开始,在重掺杂的n-型半导体衬底上方,作为初始材料。在602处,在漂流区上使用一个沟槽掩膜。在某些实施例中,沟槽掩膜可以是一个氧化层,生长或沉积在漂流区上方。沟槽掩膜含有开口,以便为MOSFET器件的沟槽晶体管限定多个栅极沟槽的位置。对于肖特基接头沿肖特基接触沟槽(例如图2和图3所示的器件)形成的器件来说,沟槽掩膜含有开口,用于有源晶胞区和肖特基二极管区中的栅极沟槽。对于器件中肖特基接头形成在两个相邻的p立柱之间的漂流区的表面上的器件(例如图4和图5所示的器件)来说,沟槽掩膜含有开口,仅用于有源晶胞区中的栅极沟槽,并且整个肖特基二极管区被掩膜覆盖。在604处,进行刻蚀工艺,向下刻蚀下方的漂流区的相应部分,以构成多个栅极构成。栅极沟槽的深度约为1.0微米。栅极沟槽的宽度可以小到工艺允许的最小值。作为示例,但不作为局限,栅极沟槽的宽度在0.3至0.5微米之间。对于25V的器件来说,栅极沟槽的间距可以在1.3至1.5微米之间。还可选择,形成栅极沟槽并且出去沟槽掩膜之后,可以生长一个牺牲氧化层(图中没有表示出),然后除去,以改善硅表面。
然后,在漂流区的顶面上并且沿着栅极沟槽的内表面,在606处形成一个绝缘层(例如栅极氧化物)。在608处,在栅极氧化层上方沉积一个导电材料,然后通过回刻工艺或化学-机械抛光(CMP)工艺,在610处形成一个在栅极沟槽中的栅极电极。在某些实施例中,导电材料可以是原位掺杂的或未掺杂的多晶硅,这需要在后续的制备工艺中进行多晶硅掺杂。
对于器件中肖特基接头沿肖特基接触沟槽的侧壁形成的器件(例如图2和图3所示的器件)来说,在有源晶胞区中,利用漂流区上的本体掩膜,在612处进行本体注入,漂流区覆盖了肖特基二极管区,并且留下有源晶胞区未被覆盖。对于肖特基接头形成在两个相邻的p立柱之间的漂流区表面上的器件来说,利用漂流区上的本体掩膜,在有源晶胞区中以及肖特基二极管区域上的特定区域中的612处进行本体注入,漂流区覆盖了肖特基二极管区域中的肖特基接触沟槽的位置,并且保留有源晶胞区未被覆盖。利用本体掩膜注入本体掺杂物。掺杂物离子的导电类型与半导体衬底的掺杂物导电类型相反。在某些实施例中,对于n-型器件来说,掺杂离子可以是硼离子。在某些实施例中,对于p-型器件来说,可以使用磷或砷离子。利用热激活掺杂物原子,并驱使掺杂物扩散,形成本体区,在614处进行本体驱进。
在616处,进行源极注入,然后进行源极扩散工艺。确切地说,利用源极注入掩膜,在漂流区上进行源极掺杂注入,漂流区覆盖了肖特基二极管区域,保留有源晶胞区未被覆盖。掺杂离子的导电类型与半导体衬底的掺杂离子导电类型相同。在某些实施例中,对于n-型器件,可以注入磷或砷离子。随后进行源极扩散,在本体区中形成掺杂的源极区。
在618处,通过选择性注入P-型掺杂物,形成超级结结构。这种注入可以通过掩膜完成,以便在N-型衬底中形成P-立柱。通过沉积氧化物,例如低温氧化物(LTO)或含有硼酸的硅玻璃(BPSG),使栅极电极与源极接头电绝缘,如同620所示。
源极接触沟槽和肖特基接触沟槽形成在622处。确切地说,在电介质层上使用一个接触掩膜,接触掩膜所带的图案在器件晶胞区中的源极接触沟槽和肖特基二极管区中肖特基接触沟槽的位置上具有开口。利用刻蚀工艺,除去电介质层未被覆盖的那部分,形成源极接触沟槽,穿过源极区到本体区内,以及肖特基二极管区中所需的肖特基接触沟槽。肖特基接触沟槽比源极接触沟槽更宽。作为示例,但不作为局限,有源器件晶胞区中的源极接触沟槽的宽度约为0.4微米,肖特基接触沟槽的宽度约为0.5至0.7微米,取决于台面结构的宽度。
对于肖特基接头沿肖特基接触沟槽的侧壁形成的器件(例如图2和3所示的器件)来说,在624处进行p-型接触注入,在每个肖特基接触沟槽和每个源极接触沟槽下方形成一个接触注入区。接触注入区可以通过肖特基接触开口的带角度的注入形成。作为示例,但不作为局限,注入是在20至40KeV的能级下,使用1×1012-4×1012/cm2的剂量。根据所需的肖特基接头宽度,选择合适的角度。要注意的是,每个接触注入区都至少是肖特基接触沟槽的宽度。在某些实施例中,角度约为10至15°之间。我们希望,对于图2和3所示的器件来说,肖特基接触沟槽230b比接触注入物232下方的p立柱220的宽度更宽。对于肖特基接头形成在两个相邻的p立柱之间的漂流区的表面上的器件(例如图4和5所示的器件)来说,可以在624处进行轻p-型香农注入,以便在每个肖特基接触沟槽下方形成一个接触注入区。作为示例,但不作为局限,香农注入是在20至40KeV的能级下,使用1×1012-4×1012/cm2的剂量。
要注意的是,势垒高度取决于接触注入工艺。肖特基势垒高度与肖特基二极管的漏极至源极漏电流Idss有关。随着势垒高度的增加,漏电流降低,并且正向电压降增大。626表示退火工艺,进行退火工艺,激活注入物。
然后在628处,沉积一个薄势垒金属层(例如钛(Ti)或氮化钛(TiN)),在源极接触沟槽和肖特基接触沟槽的侧壁和底部。通过快速的加热工艺,加热势垒金属。在630处,在剩余的沟槽内沉积钨,然后在632处,进行回刻工艺。势垒金属作为钨插头和半导体材料之间的扩散势垒,沟槽就形成在半导体材料中。金属层(例如铝)可以沉积在BPSG层以及钨插头上方,在634处。进行金属刻蚀之后,在636处形成标准的刻蚀铝合金互联。
中压或高压功率MOSFET器件的制备工艺与图6所示的制备工艺类似,除了超级结结构在工艺开始阶段形成之外。超级结结构可以利用多层序列的外延和注入,在外延的n-型漂流区中形成p立柱。在每个连续的外延层中,通过注入掩膜,注入离子。重复使用相同的掩膜,注入每个外延层,产生p立柱。
尽管本发明关于某些较佳的版本已经做了详细的叙述,但是仍可能存在各种不同的修正、变化和等效情况。因此,本发明的范围不应由上述说明决定,与之相反,本发明的范围应参照所附的权利要求书及其全部等效内容。任何可选件(无论首选与否),都可与其他任何可选件(无论首选与否)组合。在以下权利要求中,除非特别声明,否则不定冠词“一个” 或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能,否则所附的权利要求书并不应认为是意义-加-功能的局限。没有明确指出“意思是”执行特定功能的权利要求书中的任意内容,都不应认为是35USC§112(f)中所述的“意思”或“步骤”。
Claims (22)
1.一种金属-氧化物-半导体场效应晶体管(MOSFET)器件,其特征在于,包括:
一个有源晶胞区,包括多个超级结沟槽MOSFET,其中有源晶胞区包括:
一个第一导电类型的轻掺杂漂流区,位于相同导电类型的重掺杂衬底上方;
一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;
多个栅极沟槽,位于本体区中,并延伸到漂流区内,其中多个栅极沟槽中的每个栅极沟槽都内衬电介质材料,栅极沟槽包括一个栅极电极;
一个第一导电类型的重掺杂源极区,位于本体区中;
一个源极接头,位于源极接触沟槽中,延伸到两个相邻的栅极沟槽之间的本体区;以及
一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第二掺杂立柱位于每个源极接触沟槽的底部附近;以及
一个肖特基二极管区,包括多个肖特基二极管形成在具有超级结结构的漂流区中,每个肖特基二极管都包括一个肖特基接头,在轻掺杂的半导体层和金属层之间。
2.如权利要求1所述的器件,其特征在于,肖特基接头沿肖特基接触沟槽的一部分垂直侧壁形成。
3.如权利要求1所述的器件,其特征在于,肖特基接头形成在相邻的第二掺杂立柱之间的轻掺杂漂流区的表面上。
4.如权利要求2所述的器件,其特征在于,肖特基接触沟槽比多个源极接触沟槽中的每个源极接触沟槽都宽。
5.如权利要求2所述的器件,其特征在于,肖特基接触沟槽的宽度约为0.5至0.7微米。
6.如权利要求2、4或5所述的器件,其特征在于,肖特基接触沟槽和相邻的栅极沟槽之间的缝隙小于0.2微米。
7.如权利要求1所述的器件,其特征在于,器件的工作电压在8V至40V之间,多个栅极沟槽的每个栅极沟槽的间距在1.3至1.7微米之间。
8.如权利要求1所述的器件,其特征在于,器件的工作电压为30V,多个栅极沟槽的每个栅极沟槽的间距在1.3至1.7微米之间。
9.如权利要求1所述的器件,其特征在于,器件的工作电压高于100V,多个栅极沟槽的每个栅极沟槽的间距在3.5至5微米之间。
10.如权利要求1所述的器件,其特征在于,多个栅极沟槽的每个栅极沟槽都包括一个在顶部的栅极电极以及一个在底部的屏蔽电极。
11.如权利要求3所述的器件,其特征在于,形成肖特基接头的表面是凹陷的。
12.一种沟槽金属-氧化物-半导体场效应晶体管(MOSFET)器件的制备方法,其特征在于,该方法包括:
制备一个有源晶胞区,包括多个超级结沟槽功率MOSFET,其中制备有源晶胞区包括:
制备一个第一导电类型的漂流区,位于相同导电类型的重掺杂衬底上方;
制备一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;
制备多个栅极沟槽,位于本体区中,并延伸到漂流区内,其中内衬电介质材料的多个栅极沟槽的每个栅极沟槽都含有一个栅极电极;
制备一个第一导电类型的重掺杂源极区,位于本体区中;
制备一个源极接头,在源极接触沟槽中,延伸到两个相邻的栅极沟槽之间的本体区;并且
制备一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第二掺杂立柱的每个立柱都位于每个源极接触沟槽的底部附近;并且
制备多个肖特基二极管,在肖特基二极管区中具有超级结结构的漂流区中,每个肖特基二极管都包括一个肖特基接头,在轻掺杂半导体层和金属层之间。
13.如权利要求11所述的方法,其特征在于,肖特基接头沿肖特基接触沟槽的一部分垂直侧壁形成。
14.如权利要求11所述的方法,其特征在于,肖特基接头形成在相邻的第二掺杂立柱之间的轻掺杂漂流区的表面上。
15.如权利要求13所述的方法,其特征在于,肖特基接触沟槽比多个源极接触沟槽的每个源极接触沟槽都宽。
16.如权利要求13或15所述的方法,其特征在于,肖特基接触沟槽和相邻的栅极沟槽之间的缝隙小于0.2微米。
17.如权利要求13所述的方法,其特征在于,制备多个栅极沟槽包括在漂流区上使用一个栅极沟槽掩膜,不覆盖有源晶胞区中的栅极沟槽开口以及肖特基二极管区中的栅极沟槽开口的位置。
18.权利要求14所述的方法,其特征在于,制备多个栅极沟槽包括在漂流区上使用一个栅极沟槽掩膜,不覆盖有源晶胞区中的栅极沟槽开口的位置,覆盖肖特基二极管区的整个部分。
19.权利要求13所述的方法,其特征在于,制备一个本体区包括使用一个本体掩膜,覆盖着肖特基二极管区的整个部分,留下有源晶胞区不覆盖。
20.权利要求13所述的方法,其特征在于,制备一个源极区包括使用一个本体掩膜,覆盖着肖特基二极管区的整个部分,留下有源晶胞区不覆盖。
21.权利要求13所述的方法,其特征在于,制备多个肖特基二极管包括在每个肖特基接触沟槽下方,制备一个接触注入区,其中通过肖特基接触沟槽开口,利用带角度的注入,制备接触注入区。
22.权利要求14所述的方法,其特征在于,制备多个肖特基二极管包括在每个肖特基接触沟槽下方,制备一个接触注入区,其中通过肖特基接触沟槽开口,利用香农注入,制备接触注入区。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/843,327 US10818788B2 (en) | 2017-12-15 | 2017-12-15 | Schottky diode integrated into superjunction power MOSFETs |
US15/843,327 | 2017-12-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109935634A true CN109935634A (zh) | 2019-06-25 |
CN109935634B CN109935634B (zh) | 2022-07-12 |
Family
ID=66815174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811393031.2A Active CN109935634B (zh) | 2017-12-15 | 2018-11-21 | 集成在超级结功率mosfet中的肖特基二极管 |
Country Status (3)
Country | Link |
---|---|
US (3) | US10818788B2 (zh) |
CN (1) | CN109935634B (zh) |
TW (1) | TWI712173B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112436052A (zh) * | 2020-12-09 | 2021-03-02 | 南京紫竹微电子有限公司 | 具有超结晶体管机构的集成电路***和其制造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112543993A (zh) * | 2019-02-07 | 2021-03-23 | 富士电机株式会社 | 半导体装置 |
KR102554248B1 (ko) * | 2019-02-28 | 2023-07-11 | 주식회사 디비하이텍 | 수퍼 정션 반도체 장치 및 이의 제조 방법 |
IT201900006709A1 (it) * | 2019-05-10 | 2020-11-10 | St Microelectronics Srl | Dispositivo mosfet di potenza a super giunzione con affidabilita' migliorata, e metodo di fabbricazione |
CN111092123A (zh) * | 2019-12-10 | 2020-05-01 | 杰华特微电子(杭州)有限公司 | 横向双扩散晶体管及其制造方法 |
US20220069073A1 (en) * | 2020-08-28 | 2022-03-03 | Nanjing Zizhu Microelectronics Co., Ltd. | Integrated circuit system with super junction transistor mechanism and method of manufacture thereof |
US11410995B1 (en) * | 2021-05-14 | 2022-08-09 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of forming thereof |
CN115148791B (zh) * | 2022-09-05 | 2022-12-02 | 深圳市威兆半导体股份有限公司 | 一种超结mosfet |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009027152A (ja) * | 2007-06-20 | 2009-02-05 | Denso Corp | 半導体装置及び半導体装置の製造方法 |
CN102034818A (zh) * | 2009-09-30 | 2011-04-27 | 万国半导体股份有限公司 | 通过p-体电荷的最小化改善高压mosfet二极管的反向恢复 |
CN102623349A (zh) * | 2006-01-31 | 2012-08-01 | 株式会社电装 | 具有超结结构的半导体器件及其制造方法 |
CN102820294A (zh) * | 2011-06-03 | 2012-12-12 | 飞兆半导体公司 | 超结mosfet和二极管的集成 |
CN103022156A (zh) * | 2011-09-22 | 2013-04-03 | 万国半导体股份有限公司 | 带有集成肖特基势垒二极管的沟槽mosfet器件 |
US20160233210A1 (en) * | 2015-02-11 | 2016-08-11 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
US20170062605A1 (en) * | 2013-10-30 | 2017-03-02 | Infineon Technologies Austria Ag | Semiconductor device |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5365102A (en) | 1993-07-06 | 1994-11-15 | North Carolina State University | Schottky barrier rectifier with MOS trench |
US6078090A (en) | 1997-04-02 | 2000-06-20 | Siliconix Incorporated | Trench-gated Schottky diode with integral clamping diode |
US6351018B1 (en) | 1999-02-26 | 2002-02-26 | Fairchild Semiconductor Corporation | Monolithically integrated trench MOSFET and Schottky diode |
US6621107B2 (en) * | 2001-08-23 | 2003-09-16 | General Semiconductor, Inc. | Trench DMOS transistor with embedded trench schottky rectifier |
US9882049B2 (en) * | 2014-10-06 | 2018-01-30 | Alpha And Omega Semiconductor Incorporated | Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method |
US20120273916A1 (en) * | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
US9620584B2 (en) | 2009-08-31 | 2017-04-11 | Alpha And Omega Semiconductor Incorporated | Integrated Schottky diode in high voltage semiconductor device |
US8829614B2 (en) | 2009-08-31 | 2014-09-09 | Alpha And Omega Semiconductor Incorporated | Integrated Schottky diode in high voltage semiconductor device |
US8466510B2 (en) | 2009-10-30 | 2013-06-18 | Alpha And Omega Semiconductor Incorporated | Staggered column superjunction |
US8476698B2 (en) | 2010-02-19 | 2013-07-02 | Alpha And Omega Semiconductor Incorporated | Corner layout for superjunction device |
JP2012023199A (ja) * | 2010-07-14 | 2012-02-02 | Rohm Co Ltd | ショットキバリアダイオード |
US8431470B2 (en) * | 2011-04-04 | 2013-04-30 | Alpha And Omega Semiconductor Incorporated | Approach to integrate Schottky in MOSFET |
US8502302B2 (en) | 2011-05-02 | 2013-08-06 | Alpha And Omega Semiconductor Incorporated | Integrating Schottky diode into power MOSFET |
US8860130B2 (en) * | 2012-11-05 | 2014-10-14 | Alpha And Omega Semiconductor Incorporated | Charged balanced devices with shielded gate trench |
US9105494B2 (en) | 2013-02-25 | 2015-08-11 | Alpha and Omega Semiconductors, Incorporated | Termination trench for power MOSFET applications |
US9761702B2 (en) * | 2014-02-04 | 2017-09-12 | MaxPower Semiconductor | Power MOSFET having planar channel, vertical current path, and top drain electrode |
US9761676B2 (en) * | 2014-03-26 | 2017-09-12 | Infineon Technologies Americas Corp. | Power semiconductor device with embedded field electrodes |
-
2017
- 2017-12-15 US US15/843,327 patent/US10818788B2/en active Active
-
2018
- 2018-11-21 CN CN201811393031.2A patent/CN109935634B/zh active Active
- 2018-11-28 TW TW107142428A patent/TWI712173B/zh active
-
2020
- 2020-09-30 US US17/039,703 patent/US11538933B2/en active Active
-
2022
- 2022-11-01 US US17/978,839 patent/US20230045954A1/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102623349A (zh) * | 2006-01-31 | 2012-08-01 | 株式会社电装 | 具有超结结构的半导体器件及其制造方法 |
JP2009027152A (ja) * | 2007-06-20 | 2009-02-05 | Denso Corp | 半導体装置及び半導体装置の製造方法 |
CN102034818A (zh) * | 2009-09-30 | 2011-04-27 | 万国半导体股份有限公司 | 通过p-体电荷的最小化改善高压mosfet二极管的反向恢复 |
CN102820294A (zh) * | 2011-06-03 | 2012-12-12 | 飞兆半导体公司 | 超结mosfet和二极管的集成 |
CN103022156A (zh) * | 2011-09-22 | 2013-04-03 | 万国半导体股份有限公司 | 带有集成肖特基势垒二极管的沟槽mosfet器件 |
US20170062605A1 (en) * | 2013-10-30 | 2017-03-02 | Infineon Technologies Austria Ag | Semiconductor device |
US20160233210A1 (en) * | 2015-02-11 | 2016-08-11 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112436052A (zh) * | 2020-12-09 | 2021-03-02 | 南京紫竹微电子有限公司 | 具有超结晶体管机构的集成电路***和其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW201937726A (zh) | 2019-09-16 |
US20210020773A1 (en) | 2021-01-21 |
CN109935634B (zh) | 2022-07-12 |
US10818788B2 (en) | 2020-10-27 |
US20230045954A1 (en) | 2023-02-16 |
TWI712173B (zh) | 2020-12-01 |
US20190189796A1 (en) | 2019-06-20 |
US11538933B2 (en) | 2022-12-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109935634A (zh) | 集成在超级结功率mosfet中的肖特基二极管 | |
CN101645448B (zh) | 用于在沟槽下形成pn嵌位区的结构和方法 | |
TWI469347B (zh) | 帶有溝槽-氧化物-奈米管超級接面之元件結構及製備方法 | |
CN203690306U (zh) | 半导体器件及半导体器件结构 | |
CN102856182B (zh) | 制造绝缘栅极半导体装置的方法及结构 | |
CN103703566B (zh) | 半导体装置及其制造方法 | |
CN101471264B (zh) | 具有优化的可制造性的垂直功率器件的高压结构及方法 | |
US8390058B2 (en) | Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions | |
CN105280711B (zh) | 电荷补偿结构及用于其的制造 | |
CN203690305U (zh) | 半导体器件及半导体器件结构 | |
KR101324855B1 (ko) | 수퍼접합 전력 mosfet | |
JP2004511910A (ja) | トレンチショットキー整流器が組み込まれたトレンチ二重拡散金属酸化膜半導体トランジスタ | |
KR20130093126A (ko) | 개선된 쇼트키 정류기 | |
CN104319288B (zh) | 包括电容器结构的电子设备及其形成工艺 | |
CN101552293A (zh) | 用于使用多晶硅的沟槽dmos器件的源极和本体连接结构 | |
JP2005507160A (ja) | 半導体装置および電界効果トランジスタならびにそれらの形成方法 | |
CN109037212A (zh) | Lv/mv超级结沟槽功率mosfet的制备方法 | |
KR20080100265A (ko) | 종래의 종단을 갖는 수퍼 접합 장치를 제조하는 방법 | |
CN110071169A (zh) | 具有体接触与介电间隔部的半导体器件及对应的制造方法 | |
KR20070029656A (ko) | 슈퍼접합 장치를 제조하기 위한 평탄화 방법 | |
CN109659351A (zh) | 绝缘栅双极晶体管 | |
JP2019521529A (ja) | パワーデバイス及びその製造方法 | |
CN105027290B (zh) | 自适应电荷平衡的mosfet技术 | |
US7238976B1 (en) | Schottky barrier rectifier and method of manufacturing the same | |
US20150137175A1 (en) | Charge reservoir igbt top structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |