CN103022156A - 带有集成肖特基势垒二极管的沟槽mosfet器件 - Google Patents
带有集成肖特基势垒二极管的沟槽mosfet器件 Download PDFInfo
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Abstract
本发明涉及一种带有集成肖特基势垒二极管的沟槽MOSFET器件,其中肖特基二极管包括一个形成在半导体衬底上的半导体层;形成在半导体层中的第一和第二沟槽,其中第一和第二沟槽内衬薄电介质层,并用沟槽导体层部分填充,第一电介质层填充第一和第二沟槽的剩余部分;以及一个形成在第一和第二沟槽之间的半导体层顶面上的肖特基金属层。所形成的肖特基二极管中,肖特基金属层作为阳极,第一和第二沟槽之间的半导体层作为阴极。每个第一和第二沟槽中的沟槽导体层电连接到肖特基二极管的阳极。在一个实施例中,所形成的肖特基二极管与沟槽场效应晶体管集成在同一个半导体衬底上。
Description
技术领域
本发明涉及半导体器件,尤其是涉及一种集成肖特基势垒二极管的沟槽MOSFET器件。
背景技术
肖特基结的特点在于,能垒(对于自由载流子)低于PN二极管结,单极电流传导与PN二极管情况下的双极电流传导相反。因此,虽然肖特基二极管在低于典型PN结二极管的正向电压下开始电流传导,但是肖特基二极管的反向偏置漏电流高于典型的PN结二极管。由于肖特基二极管是单极器件,因此开关速度比PN结二极管更快。
肖特基二极管通常使用在电子器件中,用于整流。例如,在功率转换器实现同步整流的器件中,功率转换器使用功率MOSFET,作为高端开关,使用另一个功率MOSFET,作为低端开关,两个功率MOSFET用于调制电流传导到负载。在实际运行中,在一个开关开启之前,两个开关都断开。当两个开关断开时,功率MOSFET的体二极管传导电流。然而,为了提高转换效率,肖特基二极管通常与MOSFET体二极管并联,如图1所示。N-型功率MOSFET M1具有一个体二极管D1,由P-型本体区构成,作为阳极,N-型漏极区作为阴极。为了提高功率MOSFET M1的性能,肖特基二极管SD1与体二极管D1并联。肖特基二极管SD1的阳极电连接到功率MOSFET M1的源极端或体二极管D1的阳极。肖特基二极管SD1的阴极电连接到功率MOSFET M1的漏极端,或体二极管D1的阴极。肖特基二极管SD1的正向偏压低于体二极管D1,从而降低了正向压降,并且改善了恢复时间。
发明内容
本发明的目的是提供一种集成肖特基势垒二极管的沟槽MOSFET器件的新型结构。
依据本发明的一个实施例,肖特基二极管包括一个第一导电类型的半导体衬底;一个形成在半导体衬底上的第一导电类型的半导体层;形成在半导体层中的第一和第二沟槽,第一和第二沟槽内衬一薄电介质层,并用沟槽导体层部分填充,第一和第二沟槽的剩余部分用第一电介质层填充;一个形成在第一和第二沟槽之间的半导体层顶面上的肖特基金属层。所形成的肖特基二极管带有肖特基金属层,作为阳极,第一和第二沟槽之间的半导体层,作为阴极。每个第一和第二沟槽中的沟槽导体层都电连接到肖特基二极管的阳极。
依据本发明的另一个方面,含有场效应晶体管和肖特基二极管的半导体器件包括,一个第一导电类型的半导体衬底;一个形成在半导体衬底上的第一导电类型的半导体层;形成在半导体层中的第一和第二沟槽,第一和第二沟槽内衬一薄电介质层,并用第一沟槽导体层填充,第一和第二沟槽的剩余部分用第一电介质层填充;一个形成在第一和第二沟槽之间的半导体层顶面上的肖特基金属层;一个形成在半导体层中的第三沟槽,第三沟槽内衬薄电介质层,并用第一沟槽导体层和第二沟槽导体层填充,第一沟槽导体层通过中间层电介质层,与第二沟槽导体层绝缘,第一沟槽导体层填充一部分第三沟槽,第二沟槽导体层从中间层电介质开始,延伸到第三沟槽的顶面附近;一个形成在第三沟槽附近的半导体层顶部中的第二导电类型的第一阱区,第一阱区延伸到形成在第三沟槽中的第二沟槽导体层底部边缘附近的深度;以及一个形成在第三沟槽侧壁附近的第一阱区中,第一导电类型的重掺杂源极区。
制备一个肖特基二极管,其中肖特基金属层作为阳极,第一和第二沟槽之间的半导体层作为阴极。制备场效应晶体管,其中重掺杂N-型半导体衬底作为漏极,第三沟槽中的第二沟槽导电层作为栅极,第一阱区作为本体区,重掺杂源极区作为源极,第三沟槽中的第一沟槽导电层作为栅极屏蔽电极。第三沟槽中的第一沟槽导电层电连接到源极,每个第一和第二沟槽中的第一沟槽导电层都电连接到肖特基二极管的阳极。
阅读以下详细说明并参照附图后,将更好地理解本发明。
附图说明
图1表示肖特基二极管与功率MOSFET和功率MOSFET的体二极管并联的电路图。
图2表示依据本发明的一个实施例,集成肖特基二极管的沟槽MOSFET器件的剖面图。
图3为图2所示的沟槽肖特基二极管的等轴测试图,表示沟槽的纵轴和形成肖特基二极管的台面结构。
图4表示依据本发明的第一可选实施例,沟槽肖特基二极管的等轴测试图。
图5表示依据本发明的一个实施例,图4中的沟槽肖特基二极管沿纵轴线A-A’的剖面图。
图6表示依据本发明的第二可选实施例,沟槽肖特基二极管的等轴测试图。
图7表示依据本发明的一个实施例,图6中的沟槽肖特基二极管沿纵轴线A-A’的剖面图。
图8表示依据本发明的第三可选实施例,沟槽肖特基二极管的等轴测试图。
图9表示依据本发明的一个实施例,图8中的沟槽肖特基二极管沿纵轴线A-A’的剖面图。
图10表示依据本发明的第四可选实施例,沟槽肖特基二极管的等轴测试图。
具体实施方式
依据本发明的原理,利用沟槽界定的台面结构,将肖特基二极管集成在沟槽MOSFET结构中,沟槽仅由沟槽导体部分填充,沟槽导体电连接到肖特基二极管的阳极。在这种情况下,就可以使用沟槽MOSFET器件的标准制备工艺,制备“沟槽”肖特基二极管,使肖特基二极管无缝集成在沟槽MOSFET器件结构中。
图2表示依据本发明的一个实施例,集成肖特基二极管的沟槽MOSFET器件的剖面图。参见图2,沟槽MOSFET(金属-氧化物-硅场效应晶体管)器件10以及沟槽肖特基二极管20形成在半导体本体上。在本说明中,半导体本体含有一个形成在重掺杂N+衬底21上的N-型外延层22。在其他实施例中,半导体本体含有一个P-型半导体衬底,P-型外延层形成在上方。半导体本体的准确结构,对本发明的实施并不重要。沟槽12(包括沟槽12a至12c)形成在N-型外延层22中,限定台面结构,扩散区就形成在台面结构中。沟槽12a-12c的内壁内衬电介质层15,例如氧化硅层。
第一沟槽导体层13形成在沟槽12的底部。更确切地说,第一沟槽导体层13a至13c形成在每个沟槽12a至12c中。在本发明的实施例中,第一沟槽导体层13为多晶硅层。中间多晶硅电介质层17形成在第一沟槽导体层上。然后,在与沟槽MOSFET器件10有关的沟槽12a中,第二沟槽导体层14形成在中间-多晶硅电介质层17上方。在本发明的实施例中,第二沟槽导体层14为多晶硅层。第二沟槽导体层有时也称为栅极导体层、栅极多晶硅层或栅极电极,其功能同MOSFET器件的栅极导体一样。沟槽12b和12c由台面结构限定,沟槽肖特基二极管20形成在台面结构中,第二沟槽导体层14并没有填充沟槽,而是用电介质层19(例如氧化硅层)填充沟槽的剩余部分。因此,沟槽导体层仅部分填充沟槽12b和12c。
P-阱区24形成在沟槽MOSFET器件所形成的台面结构中。例如,P-阱区24形成在沟槽12a附近的台面结构中,以及沟槽MOSFET器件10所形成的沟槽12a和12b之间。P-阱区24至少延伸到附近沟槽12a中的栅极多晶硅层底部周围。沟槽肖特基二极管20所形成的沟槽12b和12c之间的台面结构,并不接受P-阱植入物,从而仍然是轻掺杂N-型,带有N-型外延层的掺杂浓度。P-阱区24构成沟槽MOSFET器件的本体区,N-型外延层22构成漏极区。N+衬底21构成沟槽MOSFET器件的背部漏极电极。重掺杂N+区16形成在沟槽MOSFET器件所形成的台面结构的顶部。因此,重掺杂N+区16形成在沟槽12a和12b之间的台面结构中,以及沟槽12a附近的台面结构中。电介质层18形成在半导体本体上方,然后形成图案,在N+区16附近的台面结构中,构成源极-本体接触开口。接触开口穿过N+源极区(即,16)延伸到P-阱区24本体区中。然后,用源极金属层填充接触开口,以便将N+源极区(即,16)电连接到P-阱区24本体区。填充接触开口的源极金属层有时也称为源极接触插头或源极插头26,源极金属层(即,26)填充源极区(即,16)和P-阱区24中的接触开口。在某些实施例中,源极接触插头(即,26)为钨插头。在某些实施例中,填充源极接触开口之前,可以选择通过在源极-本体接触开口的底部进行P+植入,形成P-型本体接触扩散区23,以便改善源极插头和P-阱区24本体区之间的欧姆接触。
形成源极插头之后,在源极插头和电介质层18上方制备金属层38,形成到源极区和阱区的电连接。在某些实施例中,金属层38为铝层。后续的电介质或绝缘层(图中没有表示出)可以形成在金属层38上方。在沟槽之间的台面结构中,制备到漏极区(N-型外延层22)以及到第一、第二沟槽导体层的电接触,在第三维度上垂直于图2所示的剖面。
因此,所形成的沟槽MOSFET器件10包括一个形成在栅极多晶硅层(即,14)中的栅极区,一个形成在N+区16中的源极区,一个形成在N-型外延层22中的漏极区,以及一个形成在P-阱区24中的本体区。MOSFET器件10为屏蔽栅沟槽MOSFET器件,第一沟槽导体层13屏蔽栅极多晶硅层(即,14)不受高压的影响。因此,第一沟槽导体层有时也称为屏蔽多晶硅层或栅极屏蔽电极。在某些实施例中,MOSFET器件10的源极区电连接到接地端,屏蔽多晶硅层也电连接到地电势。到屏蔽多晶硅层的电连接可以处于沟槽之间的台面结构中,在第三维度上,垂直于图2所示的剖面。
沟槽肖特基二极管20形成在沟槽12b和12c之间的台面结构27中。如上所述,沟槽12b和12c之间的台面结构并不接受P-阱植入,因此,台面结构仍然保持N-型外延层22的掺杂水平。为了制备肖特基势垒二极管,肖特基金属层28形成在台面结构27的表面上,并与台面结构27电接触。图3为沟槽肖特基二极管20的等轴测试图,表示的是沟槽的长轴以及肖特基二极管所形成的台面结构。参见图3,肖特基结形成在肖特基金属层28和台面结构27处的N-型外延层22的金属-硅结处。台面结构27构成肖特基二极管的阴极,而肖特基金属层28构成肖特基二极管的阳极。在本发明的实施例中,额外的金属层形成在肖特基金属层28上,以便改善导电。在本实施例中,金属层30形成在肖特基金属层28上方。在一个实施例中,金属层30为复合金属层,包括钨层和铝-硅层。
本发明所述的沟槽肖特基二极管20的显著特点是,肖特基二极管形成在沟槽12b、12c限定的台面结构27中,沟槽12b、12c仅仅用沟槽导体层部分填充,沟槽导体层电连接到肖特基二极管的阳极。在本实施例中,限定肖特基二极管20台面结构27的沟槽12b、12c,都仅用屏蔽多晶硅层(即,13b、13c)填充。栅极多晶硅层并不形成在沟槽12b、12c中。在这种情况下,删除沟槽12b、12c中的栅极多晶硅层,并且修正台面结构27中的P-阱区之后,就可以利用与沟槽MOSFET相同的制备工艺,制备沟槽肖特基二极管。在本实施例中,台面结构27中完全删除P-阱区。在本发明的可选实施例中,分立的P-阱区可以分散形成,或者沿台面结构的长轴方向间隔开,肖特基二极管就形成在P-阱区之间的N-型外延层中,下文还将详细介绍。
本发明所述的沟槽肖特基二极管20的另一个显著特点是,沟槽MOSFET器件和沟槽肖特基二极管的台面结构宽度相同。沟槽肖特基二极管不需要像传统的器件那样,使台面结构变窄。肖特基二极管使用较宽的台面结构宽度的优势在于,改善了肖特基二极管的串联电阻,提高了肖特基二极管的效率。在一个实施例中,肖特基二极管形成在台面结构中,该台面结构也用于制备到屏蔽多晶硅层的电接触。因此,在沟槽MOSFET器件中集成肖特基二极管有效利用了硅不动产。
本发明的另一个实施例,部分填充肖特基二极管的沟槽12b和12c的沟槽导体层,可以是任意其他类型的导体层,包括金属和多晶硅。此外,在本发明的实施例中,肖特基二极管的沟槽12b和12c可以用沟槽导体层填充,一直到沟槽深度的一半左右,或小于沟槽深度的一半。然而,在另一个实施例中,肖特基二极管的沟槽12b和12c中的沟槽导体层13b、13c可以电连接到沟槽MOSFET器件10的屏蔽多晶硅层(即,13a),以及电连接到MOSFET器件的源极电势。
在一些实施例中,在台面结构27的顶面进行浅补偿植入29,以调节肖特基二极管函数附近的台面结构表面上的势垒高度。在本发明的实施例中,浅补偿植入29为P-型离子植入到N-外延层22中。选取浅补偿植入29的深度和剂量,以调节肖特基二极管20的正向偏压和击穿漏电流。浅补偿植入的植入剂量可以或不足以超过N-外延层22的基础掺杂浓度。因此,台面结构27表面上所形成的植入区可以转换成P-型或仍然保持N-型。
在一些实施例中,在N-型外延层22中试用一个或多个深腔补偿植入35,远离肖特基结,在台面结构的深处。深腔补偿植入35可以是N-型植入或P-型植入。可以选取深腔补偿植入35的植入剂量,使N-外延层22的基础掺杂浓度高于深腔补偿植入。因此,所形成的植入区仍然是N-型,但是势垒高度可以通过补偿植入来调节。深腔补偿植入35的作用是控制肖特基结的电流通路,以降低漏电流。
图4表示依据本发明的第一可选实施例,沟槽肖特基二极管的等轴测试图。参见图4,沟槽肖特基二极管40的制备方式与上述沟槽肖特基二极管20的制备方式大致相同。更确切地说,沟槽肖特基二极管40形成在两个沟槽12b和12c之间的台面结构27中,沟槽12b和12c仅用沟槽导体层13b和13c部分填充。在本实施例中,P-阱区24可以分散形成,或者在台面结构27中沿台面结构的长轴方向间隔开。台面结构的长轴与沟槽的长轴平行。因此,P-阱区24从一个沟槽侧壁延伸到下一个,例如从沟槽12b的侧壁延伸到沟槽12c的侧壁。P-阱区沿台面结构的长轴方向间隔开,形成沿台面结构的长度方向独立的P-阱区。在本实施例中,肖特基金属层48作为长条纹,覆盖着P-阱区以及P-阱区之间的N-型外延区。在一个实施例中,肖特基金属条纹48的宽度小于两个邻近沟槽12b、12c之间的台面结构宽度。因此,沟槽肖特基二极管40形成在肖特基金属层48和N-型外延层22之间的肖特基结处,以及肖特基金属层48和P-阱区24之间的肖特基结之间。
图5表示依据本发明的一个实施例,沟槽肖特基二极管40沿长轴方向A-A’的剖面图。参见图5,沟槽肖特基二极管40形成在N-型外延层22中,在两个沟槽12b、12c(图4)之间,还在两个邻近的P-阱区24之间。肖特基金属层48形成在N-型外延层22和P-阱区24的表面上,以构成肖特基结。在本说明中,肖特基金属覆盖P-阱区24以及N-型外延层22。在一个实施例中,肖特基金属层48为氮化钛(TiN)层。此外,在一些实施例中,额外的金属层形成在肖特基金属层上,以降低肖特基二极管的阳极电阻。在本实施例中,钨(W)层51形成在肖特基金属层48上,铝-硅(Al-Si)层52形成在钨层51上。绝缘层(图中没有表示出)形成在肖特基二极管结构上方,提供绝缘或钝化。
在散布的P-阱区之间,制备沟槽肖特基二极管具有许多优势。特别是P-阱区的作用是夹断肖特基二极管电流通路,从而限制漏电流。P-阱区还可以控制肖特基结附近的台面结构的表面电场。从而提升肖特基二极管的性能。
在本发明的实施例中,如上所述,在沟槽肖特基二极管结构中进行补偿植入,以提高肖特基二极管的电场性能。在一个实施例中,在肖特基结附近的N-型外延层22的顶面进行浅补偿植入29。浅补偿植入29可以控制肖特基二极管的正向偏压及击穿漏电流。在一些实施例中,对N-型外延层22进行一次或多次深腔补偿植入35,远离肖特基结,在台面结构的深处。深腔补偿植入35的作用是控制肖特基二极管的电流通路,降低漏电流。
图6表示依据本发明的第二可选实施例,沟槽肖特基二极管的等轴测试图。图7表示依据本发明的一个实施例,图6所示的沟槽肖特基二极管沿长轴A-A’的剖面图。参见图6和图7,沟槽肖特基二极管60的制备方式与上述沟槽肖特基二极管40的制备方式大致相同。更确切地说,沟槽肖特基二极管60形成在两个沟槽12b和12c之间的台面结构27中,沟槽12b和12c仅用沟槽导体层13b和13c部分填充。此外,P-阱区24在台面结构27中沿台面结构的长轴分散形成。在本实施例中,源极接触插头(即,26)以及可选的P+本体接触扩散区23形成在P-阱区24中。肖特基金属层68形成在一条长条纹中,覆盖着台面结构27中的N-型外延层、P-阱区24以及源极插头26。源极插头26使肖特基金属层68和P-阱区24之间形成欧姆接触。在这种情况下,P-阱区24电连接到与肖特基二极管相同的电势上。因此,沟槽导体层13b、13c、P-阱区24以及阳极都连接到相同的电势。在一些实施例中,沟槽导体层13b、13c、P-阱区24以及阳极都电连接到地电压。沟槽导体层13b、13c以及P-阱区都为肖特基二极管提供屏蔽。在本发明的实施例中,肖特基二极管的阳极转而连接到沟槽MOSFET的源极,沟槽MOSFET形成在同一个半导体层上。沟槽肖特基二极管60还包括一个浅补偿植入29以及一个或多个深腔补偿植入35,如图上述图7所示。
图8表示依据本发明的第三可选实施例,沟槽肖特基二极管的等轴测试图。图9表示依据本发明的一个实施例,图8所示的沟槽肖特基二极管沿长轴A-A’的剖面图。参见图8和图9,沟槽肖特基二极管70的制备方式与上述沟槽肖特基二极管60的制备方式大致相同。更确切地说,沟槽肖特基二极管70形成在两个沟槽12b和12c之间的台面结构27中,沟槽12b和12c仅用沟槽导体层13b和13c部分填充。P-阱区24在台面结构27中沿台面结构的长轴分散形成。源极接触插头(即,26)以及可选的P+本体接触扩散区23形成在P-阱区24中。在本实施例中,肖特基金属层78作为岛,形成在台面结构27中的N-型外延层22上。更确切地说,肖特基金属岛形成在N-型外延层22上方,在邻近的P-阱区24之间的台面结构27中,并且在被边缘终接扩散区54包围的区域中。边缘终接扩散区54为P-型区,形成在N-型外延层22的顶面中,包围着肖特基结。更确切地说,边缘终接扩散区54形成在被邻近的P-阱区24限定的台面结构27的边缘上。在一个实施例中,通过在N-外延层22中植入P-型离子,构成边缘终接扩散区54。边缘终接扩散区54的作用是降低肖特基结拐角处的电场。
在本发明的实施例中,如上所述,肖特基二极管70还包括一个浅补偿植入29以及一个或多个深腔补偿植入35。
在本实施例中,肖特基二极管70包括源极插头26和P+本体接触扩散区23,在P-阱区24中。源极插头26和P+本体接触扩散区23是可选的,在本发明的其他实施例中,可以省去这两者或其中之一。可以制备在P-阱区24中不带有任何源极插头或P+本体接触区的肖特基二极管70。
图10表示依据本发明的第四可选实施例,沟槽肖特基二极管的等轴测试图。参见图10,沟槽肖特基二极管80的制备方式与上述沟槽肖特基二极管60的制备方式大致相同。更确切地说,沟槽肖特基二极管80形成在两个沟槽12b和12c之间的台面结构27中,沟槽12b和12c仅用沟槽导体层13b和13c部分填充。此外,P-阱区24在台面结构27中沿台面结构的长轴分散形成,源极接触插头(即,26)以及可选的P+本体接触扩散区23形成在P-阱区24中。在本实施例中,肖特基金属层88作为岛,覆盖着邻近P-阱区24之间的台面结构27中的N-型外延层22。源极插头26电连接到肖特基二极管的阳极,肖特基二极管的阳极转而连接到形成在同一个半导体层上的沟槽MOSFET的源极。
在本实施例中,肖特基二极管80包括源极插头26和P+本体接触扩散区23,在P-阱区24中。源极插头26和P+本体接触扩散区23是可选的,在本发明的其他实施例中,可以省去这两者或其中之一。可以制备在P-阱区24中不带有任何源极插头或P+本体接触区的肖特基二极管80。
上述详细说明用于解释说明本发明的典型实施例,不作为局限。可能存在本发明范围内的多种修正和改变。例如,图2、3和10中所示的肖特基金属层可以延伸穿过两个邻近沟槽(12b、12c)之间的N-型外延层的整体宽度。在本发明的其他实施例中,肖特基金属层仅覆盖两个沟槽之间的宽度部分,如图4和图6所示。与之类似,图4和图6所示的肖特基金属层可以延伸覆盖两个邻近沟槽之间的半导体层的整体宽度。
此外,在上述实施例中,介绍了一种N-型沟槽MOSFET器件,沟槽肖特基二极管形成在N-型外延层上方。在本发明的器件实施例中,可以通过转换半导体层或衬底、外延层及各种扩散/植入区的极性,制备相反极性的器件。本发明范围应由所附的权利要求书限定。
尽管本发明的内容已经通过上述优选实施例作了详细介绍,但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后,对于本发明的多种修改和替代都将是显而易见的。因此,本发明的保护范围应由所附的权利要求来限定。
Claims (27)
1.一种肖特基二极管,其特征在于,包括:
一个第一导电类型的半导体衬底;
一个形成在半导体衬底上的第一导电类型的半导体层;
形成在半导体层中的第一和第二沟槽,第一和第二沟槽内衬一个薄电介质层,并且用一沟槽导体层部分填充,第一和第二沟槽的剩余部分用第一电介质层填充;以及
一个形成在第一和第二沟槽之间的半导体层顶面上的肖特基金属层,
其中所述的肖特基金属层形成所述的肖特基二极管的阳极,第一和第二沟槽之间的半导体层形成所述的肖特基二极管的阴极,每个第一和第二沟槽中的沟槽导体层都电连接到所述的肖特基二极管的阳极。
2.如权利要求1所述的肖特基二极管,其特征在于,其中所述的第一和第二沟槽都具有第一沟槽深度,第一沟槽导体层向上延伸到第一沟槽深度的一半或一半以下。
3.如权利要求1所述的肖特基二极管,其特征在于,其中所述的肖特基金属层形成在半导体层上覆盖从第一沟槽到第二沟槽的半导体层的部分宽度或整体宽度。
4.如权利要求1所述的肖特基二极管,其特征在于,还包括:
多个第二导电类型的阱区,形成在第一沟槽和第二沟槽之间的半导体层顶部,多个阱区在平行于第一和第二沟槽的长轴方向上分隔开;
其中所形成的肖特基金属层覆盖着多个阱区以及多个阱区之间的半导体层。
5.如权利要求4所述的肖特基二极管,其特征在于,其中所述的肖特基金属层形成在半导体层以及多个阱区上方,覆盖着从第一沟槽到第二沟槽的半导体层以及阱区的一部分宽度或整体宽度。
6.如权利要求4所述的肖特基二极管,其特征在于,还包括:
多个接触插头,每个接触插头都形成在相应的阱区中;
其中所形成的肖特基金属层覆盖着多个阱区,多个接触插头以及多个阱区之间的半导体层,肖特基金属层与多个接触插头构成欧姆接触。
7.如权利要求6所述的肖特基二极管,其特征在于,还包括:
多个第二导电类型的接触扩散区,每个接触扩散区都分别形成在各自的接触插头下方各自的阱区中。
8.如权利要求6所述的肖特基二极管,其特征在于,其中所述的肖特基金属层形成在半导体层、多个阱区以及多个接触插头上,并且覆盖半导体层的一部分宽度或整体宽度,以及从第一沟槽到第二沟槽的阱区。
9.如权利要求1所述的肖特基二极管,其特征在于,还包括:
在第一和第二沟槽之间的半导体层顶面上,进行第二导电类型的浅补偿植入,利用浅补偿植入来调节肖特基二极管的正向偏压。
10.如权利要求1所述的肖特基二极管,其特征在于,还包括:
在第一和第二沟槽之间的半导体层中,以及在远离半导体层顶面的深处,进行第二导电类型的深腔补偿植入,利用深腔补偿植入,降低肖特基二极管的漏电流。
11.如权利要求1所述的肖特基二极管,其特征在于,还包括:
多个第二导电类型的阱区,形成在第一沟槽和第二沟槽之间的半导体层顶部,多个阱区在平行于第一和第二沟槽的长轴方向上间隔开;
其中肖特基金属层形成在第一和第二沟槽之间的半导体层顶面上,仅仅覆盖多个阱区之间的半导体层。
12.如权利要求1所述的肖特基二极管,其特征在于,还包括:
多个第二导电类型的阱区,形成在第一沟槽和第二沟槽之间的半导体层顶部,多个阱区在平行于第一和第二沟槽的长轴方向上间隔开;以及
一个第二导电类型的边缘终接扩散区,形成在沿第一和第二沟槽以及邻近的阱区限定的边缘的半导体层中;
其中所形成的肖特基金属层覆盖着被边缘终接扩散区限定的一个区域中的半导体层。
13.如权利要求1所述的肖特基二极管,其特征在于,其中所述的肖特基金属层是由氮化钛层构成的。
14.如权利要求1所述的肖特基二极管,其特征在于,其中所述的半导体层是由第一导电类型的外延层构成的。
15.如权利要求4所述的肖特基二极管,其特征在于,其中所述的第一导电类型是由N-型导电性构成的,第二导电类型是由P-型导电性构成的。
16.如权利要求1所述的肖特基二极管,其特征在于,其中半导体衬底是由第一导电类型的重掺杂半导体衬底构成的。
17.一种包含场效应晶体管和肖特基二极管的半导体器件,其特征在于,该半导体器件包括:
一个第一导电类型的半导体衬底;
一个第一导电类型的半导体层,形成在半导体衬底上;
第一和第二沟槽,形成在半导体层中,第一和第二沟槽内衬薄电介质层,并用第一沟槽导体层填充,第一沟槽导体层填充每个第一和第二沟槽的一部分,第一和第二沟槽的剩余部分用第一电介质层填充;
一个肖特基金属层,形成在第一和第二沟槽之间的半导体层顶面上;
一个第三沟槽,形成在半导体层中,第三沟槽内衬薄电介质层,并用第一沟槽导体层和第二沟槽导体层填充,通过一个中间层电介质层,第一沟槽导体层与第二沟槽导体层绝缘,第一沟槽导体层填充第三沟槽的一部分,且第二沟槽导体层从中间层电介质延伸到第三沟槽的顶面附近;
一个第二导电类型的第一阱区,形成在第三沟槽附近的半导体层顶部,第一阱区延伸到形成在第三沟槽中的第二沟槽导体层底部边缘附近的深度;以及
一个第一导电类型的重掺杂源极区,形成在第三沟槽侧壁附近的第一阱区;
其中所形成的肖特基二极管中,肖特基金属层作为阳极,第一和第二沟槽之间的半导体层作为阴极;
其中所形成的场效应晶体管中,重掺杂N-型半导体衬底作为漏极电极,第三沟槽中的第二沟槽导体层作为栅极电极,第一阱区作为本体区,重掺杂源极区作为源极电极,第三沟槽中的第一沟槽导体层作为栅极屏蔽电极;并且
其中第三沟槽中的第一沟槽导体层电连接到源极电极,每个第一和第二沟槽中的第一沟槽导体层都电连接到肖特基二极管的阳极。
18.如权利要求17所述的半导体器件,其特征在于,其中第一、第二和第三沟槽具有第一沟槽深度,第一沟槽导体层向上延伸到第一沟槽深度的一半或小于一半。
19.如权利要求17所述的半导体器件,其特征在于,还包括:
多个第二导电类型的阱区,形成在第一和第二沟槽之间的半导体层顶部,多个阱区在平行于第一和第二沟槽的长轴方向上间隔开;
其中所形成的肖特基金属层覆盖着多个阱区,以及多个阱区之间的半导体层。
20.如权利要求19所述的半导体器件,其特征在于,其中多个阱区的掺杂浓度和深度都与第一阱区相同。
21.如权利要求19所述的半导体器件,其特征在于,还包括:
多个接触插头,每个接触插头都形成在各自的多个阱区的其中之一;
其中所形成的肖特基金属层,覆盖多个阱区、多个接触插头以及多个阱区之间的半导体层,肖特基金属层与多个接触插头形成欧姆接触。
22.如权利要求21所述的半导体器件,其特征在于,还包括:
多个第二导电类型的接触扩散区,每个接触扩散区分别形成在各自的接触插头下方的阱区中。
23.如权利要求17所述的半导体器件,其特征在于,还包括:
一个第二导电类型的浅扩散区,形成在第一和第二沟槽之间的半导体层的顶面上。
24.如权利要求17所述的半导体器件,其特征在于,还包括:
一个第二导电类型的深腔扩散区,形成在第一和第二沟槽之间的半导体层中,在远离半导体层顶面的深处。
25.如权利要求17所述的半导体器件,其特征在于,其中所述的半导体层是由第一导电类型的外延层构成的。
26.如权利要求17所述的半导体器件,其特征在于,其中所述的第一导电类型是由N-型导电性构成的,第二导电类型是由P-型导电性构成的。
27.如权利要求17所述的半导体器件,其特征在于,其中所述的半导体衬底是由第一导电类型的重掺杂半导体衬底构成的。
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TWI481038B (zh) | 2015-04-11 |
US20130075808A1 (en) | 2013-03-28 |
US20140073098A1 (en) | 2014-03-13 |
CN103022156B (zh) | 2015-02-11 |
US8865540B2 (en) | 2014-10-21 |
US9281416B2 (en) | 2016-03-08 |
US20150001616A1 (en) | 2015-01-01 |
US8610235B2 (en) | 2013-12-17 |
TW201314918A (zh) | 2013-04-01 |
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