CN109884607B - Synthetic aperture address code generation method based on FPGA - Google Patents
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Abstract
The invention discloses a synthetic aperture address code generating method based on FPGA, which is used for high-speed processing of image data after synthetic aperture radar/sonar pulse compression, and three paths of synthetic range counters are utilized to generate count values of cnt _ i, cnt _ j and cnt _ k for driving a multi-path address code generating module; the address code generation module generates an address code d-1 in parallel by utilizing a pipeline structure through the driving of the three counters; the shift register is used for delaying the address code k-i and synchronizing with the address code d-1 generated by the pipeline structure, so that the high-speed address code generation effect is achieved; the invention can be applied to the occasion with high requirement on the synthetic aperture algorithm speed to carry out high-speed parallel generation of the address code.
Description
Technical Field
The invention belongs to the field of Field Programmable Gate Array (FPGA), and relates to a synthetic aperture address code generation method based on the FPGA.
Background
At present, a synthetic aperture algorithm can only be used in occasions with low requirements on processing speed, and a computing method capable of processing image data in real time after the image data are obtained by a side-scan radar/sonar is lacked. The existing methods are generally implemented by using a CPU, and the execution mode in the order of instructions requires a long time for processing image information with huge data size, and the larger the image to be processed, the longer the time is. In addition, for the address code generation of the synthetic aperture algorithm, more complex operations are required, and a large amount of data needs to be stored in the processing process. If the method is used in the occasions requiring high-speed acquisition of the images after the synthetic aperture processing, such as the situation that an airplane/submarine needs to acquire a large area of high-value targets almost in real time, the high-speed real-time requirements are obviously difficult to achieve.
Disclosure of Invention
The invention provides a synthetic aperture address code generation method based on FPGA (field programmable gate array), aiming at the defects of the prior art, and the method can be applied to the occasion with high requirement on the synthetic aperture algorithm speed to carry out high-speed parallel generation of address codes. The invention utilizes the advantage of high operation efficiency of FPGA and is based on a standard two-pass delay time formula
Calculating address code, and accelerating the implementation of the whole algorithm, wherein tdA two-pass delay time; r0The vertical distance of the air route shortcut; and x is the horizontal distance of the airway shortcut. In the implementation of the radar synthetic aperture, the two-pass delay time formula is that x is less than R0Can be simplified to
However, the synthetic aperture algorithm structure is not simplified in a root approximation manner in consideration of compatibility of the synthetic aperture algorithm structure used in radar and sonar.
The invention divides the generation of the address code into 16 paths of processing by utilizing the parallel characteristic of the FPGA so as to ensure the high speed of calculation, and respectively processes the images with insufficient aperture length at the two sides of the aperture processing and the images with enough aperture length in the middle to form a high-speed parallel processing structure with three major paths and 3 × 16 minor paths.
In order to achieve the above object, the technical solution of the present invention is a method for generating a synthetic aperture address code based on an FPGA, comprising the steps of:
s10, dividing the address code generation into 16 paths by using FPGA parallel characteristics, and respectively processing the images with insufficient aperture length at two sides of aperture processing and the images with sufficient aperture length in the middle to form a high-speed parallel processing structure with three major paths and 3 x 16 minor paths;
s20, counting the resultant width of the aperture process, and performing different nested counts for the counters cnt _ i, cnt _ j, and cnt _ k in the three major paths: in the first path, the cnt _ i loops from cnt _ k to 0; cnt _ j counts from 0 to DIS _ LINE/16, counting the 16 rows, where cnt _ j changes once per cycle of cnt _ i; cnt _ k counts from 0 to AL-1, where cnt _ k changes once per complete round of cnt _ j, counting aperture accumulations of the image that are less than the aperture length AL before the portion of the full aperture; in the second pass, cnt _ i cycles from AL-1 to 0; cnt _ j counts from 0 to DIS _ LINE/16, where cnt _ j changes once per cycle of cnt _ i completion; cnt _ k counts from AL to DIS _ DOOR-AL-1, where cnt _ k changes once per cycle of cnt _ j completion, counting the fraction of the image that falls within the full aperture size by aperture accumulation; in the third path, the cnt _ i loops to count from DIS _ DOOR-cnt _ k-1 to 0; cnt _ j counts from 0 to DIS _ LINE/16, where cnt _ j changes once per cycle of cnt _ i completion; counting cnt _ k from DIS _ DOOR-AL to DIS _ DOOR-1, wherein cnt _ k changes once every time cnt _ j completes one round of cycle, wherein, every time cnt _ i in three major-path counters completes one round of cycle, namely, when cnt _ i is 0, setting respective refresh _ flag to be high level for one period, giving a refresh signal for aperture processing, counting the aperture accumulation of the image which is less than the aperture length AL after the part of the complete aperture, DIS _ LINE is a distance LINE corresponding row, DIS _ DOOR is a distance gate corresponding column, and AL is an aperture length point number;
s30, generating an address code d-1;
and S40, generating an address code k-i.
Preferably, the S30 includes the steps of:
s31, according to the number rd _ num of input paths, a combinational logic circuit is used for adding (rd _ num-1) × (DIS _ LINE/16) to cnt _ j to obtain the pixel distance between a point to be calculated and an image edge in a path of 16 paths, a fixed point-floating point conversion IP core is used for converting the pixel distance into a 32-bit single-precision floating point number, and if the input data is in the I-th period, a corresponding value R0_ j _ pix can be obtained on the rising edge of the I + 4-th period; using combinational logic to realize the calculation of cnt _ I-AL/2-1, obtaining a result, recording the result as x _ I, converting the result into a 32-bit single-precision floating point number by using a fixed point-floating point conversion IP core, and obtaining the result at the rising edge of the I +4 th period, recording the result as fp _ x _ I;
s32, calculating R0_ j _ pix multiplied by 1/fs through a floating point multiplier, wherein 1/fs is the reciprocal of sampling frequency, namely a 32-bit single-precision floating point value corresponding to a sampling period, a multiplication result is obtained at the rising edge of the I +7 th period and is marked as t _ pix, and the multiplication result is the two-pass time for a beam to reach a point to be measured from the edge of the image to be measured; performing fp _ x _ I multiplied by delta _ sa calculation through a floating point multiplier, wherein delta _ sa is half of the length of a real aperture, namely the azimuth resolution, a multiplication result is obtained at the rising edge of the I +7 th period and is recorded as x _ I _ rl, and the multiplication result is the real distance from a sampling point to be calculated to the origin of the airway coordinate;
s33, summing the t _ pix and the two-pass time Ts used by the shortest vertical distance from the airway to the imaging area by using a floating point adder, and obtaining the two-pass time t _ R0_ j corresponding to the vertical distance from the airway to the point to be calculated on the rising edge of the I +10 th period; carrying out square operation on x _ I _ rl by using a floating-point multiplier, and obtaining x _ I _ sqr at the rising edge of the I +10 th cycle;
s34, multiplying t _ R0_ j by a single-precision floating point value corresponding to c/2 by using a floating point multiplier, wherein c is the wave speed, and obtaining a one-way vertical distance R0_ j of a beam from a navigation path to a point to be calculated at the rising edge of the (I + 13) th period; shifting x _ I _ sql by using a shift register, and outputting the shifted x _ I _ sql at the rising edge of the (I + 16) th cycle to obtain x _ I _ sql _ dly which is used for aligning data;
s35, conducting square operation on R0_ j by using a floating-point multiplier, and obtaining a result R0_ j _ sqr at the rising edge of the I +16 th period;
s36, adding x _ I _ sqr _ dly and R0_ j _ sqr by using a floating point adder, and obtaining the square R _ sqr of the one-way slope distance from the point to be calculated to the coordinate origin at the rising edge of the I +19 th period;
s37, conducting evolution operation on the R _ sqr by using a floating point evolution device, and obtaining a one-way slope distance R from a point to be calculated to a coordinate origin at the rising edge of the I +29 th period;
s38, multiplying R by a single-precision floating point value corresponding to 2/c by using a floating point multiplier, and obtaining a two-way delay time td used by the transducer for receiving the echo of the point to be calculated on the rising edge of the I +32 th period;
s39, subtracting a single-precision floating point value corresponding to the two-pass time Ts used by the shortest vertical distance from the airway to the imaging area from td by using a floating point subtracter, and obtaining Tr at the rising edge of the I +35 th period;
s310, multiplying Tr by a single-precision floating point value corresponding to sampling frequency fs by using a floating point multiplier, and obtaining two-way delay _ pix of the point to be measured at the rising edge of the I +38 th period;
s311, the delay _ pix utilizes the floating point-fixed point conversion IP core to convert the floating point into the fixed point number, utilizes the combinational logic to realize the delay _ fixed-1 operation, and obtains the address code dly _ tb _ d _1 of the point to be measured, namely d-1, at the rising edge of the I +40 th period.
Preferably, the S40 includes the steps of:
s41, using the values of cnt _ i and cnt _ k in S20 to form a combinational logic circuit calculation value cnt _ k-cnt _ i;
s42, the cnt _ k-cnt _ I is shifted by the shift register, and at the rising edge of the I +40 th cycle, the address code dly _ tb _ k _ I, i.e., k-I, outputted in synchronization with the address code dly _ tb _ d _1 is acquired.
The invention has the following beneficial effects:
the invention adopts 3-by-16 paths to generate the address code of the synthetic aperture algorithm in parallel, so that the generation speed of the address code is greatly improved, the time required by the traditional synthetic aperture method which is executed in sequence is greatly shortened, and the processing time required by the synthetic aperture algorithm is greatly saved.
Drawings
FIG. 1 is a flowchart of an algorithm of a method for generating a synthetic aperture address code based on an FPGA according to an embodiment of the present invention;
fig. 2 is a clock diagram of a method for generating a synthetic aperture address code based on an FPGA according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
Referring to fig. 1-2, the technical solution of the present invention, which is an embodiment of the present invention, is an algorithm flowchart and a clock diagram of a synthetic aperture address code generation method based on an FPGA, and includes the following steps:
s10, dividing the address code generation into 16 paths by using FPGA parallel characteristics, and respectively processing the images with insufficient aperture length at two sides of aperture processing and the images with sufficient aperture length in the middle to form a high-speed parallel processing structure with three major paths and 3 x 16 minor paths;
s20, counting the resultant width of the aperture process, and performing different nested counts for the counters cnt _ i, cnt _ j, and cnt _ k in the three major paths: in the first path, the cnt _ i loops from cnt _ k to 0; cnt _ j counts from 0 to DIS _ LINE/16, counting the 16 rows, where cnt _ j changes once per cycle of cnt _ i; cnt _ k counts from 0 to AL-1, where cnt _ k changes once per complete round of cnt _ j, counting aperture accumulations of the image that are less than the aperture length AL before the portion of the full aperture; in the second pass, cnt _ i cycles from AL-1 to 0; cnt _ j counts from 0 to DIS _ LINE/16, where cnt _ j changes once per cycle of cnt _ i completion; cnt _ k counts from AL to DIS _ DOOR-AL-1, where cnt _ k changes once per cycle of cnt _ j completion, counting the fraction of the image that falls within the full aperture size by aperture accumulation; in the third path, the cnt _ i loops to count from DIS _ DOOR-cnt _ k-1 to 0; cnt _ j counts from 0 to DIS _ LINE/16, where cnt _ j changes once per cycle of cnt _ i completion; counting cnt _ k from DIS _ DOOR-AL to DIS _ DOOR-1, wherein cnt _ k changes once every time cnt _ j completes one round of cycle, wherein, every time cnt _ i in three major-path counters completes one round of cycle, namely, when cnt _ i is 0, setting respective refresh _ flag to be high level for one period, giving a refresh signal for aperture processing, counting the aperture accumulation of the image which is less than the aperture length AL after the part of the complete aperture, DIS _ LINE is a distance LINE corresponding row, DIS _ DOOR is a distance gate corresponding column, and AL is an aperture length point number;
s30, generating an address code d-1;
and S40, generating an address code k-i.
In a specific embodiment, S30 includes the following steps:
s31, referring to the second row in fig. 1 and the first column and the second column in the clock diagram in fig. 2, according to the input lane number rd _ num, using a combinational logic circuit to add (rd _ num-1) × (DIS _ LINE/16) to cnt _ j to obtain the pixel distance between the point to be calculated and the image edge in a certain lane of 16 lanes, using a fixed point-floating point conversion IP core to convert it into a 32-bit single precision floating point number, if the input data is in the I-th cycle, then obtaining a corresponding value R0_ j _ pix at the rising edge of the I +4 th cycle; referring to the third row in fig. 1, the cnt _ I-AL/2-1 is calculated by using combinational logic, the result is obtained and recorded as x _ I, and is converted into a 32-bit single-precision floating point number by using a fixed point-floating point conversion IP core, and the result is obtained at the rising edge of the I +4 th cycle and recorded as fp _ x _ I;
s32, referring to the second row in FIG. 1 and the third column in the clock diagram in FIG. 2, R0_ j _ pix × 1/fs is calculated through a floating-point multiplier, wherein 1/fs is the reciprocal of the sampling frequency, namely a 32-bit single-precision floating-point value corresponding to the sampling period, a multiplication result is obtained at the rising edge of the (I + 7) th period, and is marked as t _ pix, and the multiplication result is the two-pass time for a beam to reach a point to be measured from the edge of the image to be measured; referring to fig. 1, the third row performs fp _ x _ I × delta _ sa calculation through a floating-point multiplier, where delta _ sa is half of the real aperture length, i.e., the azimuth resolution, and the rising edge in the I +7 th period obtains a multiplication result and records it as x _ I _ rl, which is the real distance from the sample point to be calculated to the origin of the airway coordinate;
s33, referring to the second row in FIG. 1 and the fourth column in the clock diagram of FIG. 2, summing the t _ pix and the two-way time Ts used by the shortest vertical distance from the airway to the imaging area by using a floating point adder, and obtaining the two-way time t _ R0_ j corresponding to the vertical distance from the airway to the point to be calculated on the rising edge of the I +10 th period; referring to the third row in fig. 1, the x _ I _ rl is squared by using a floating-point multiplier, and x _ I _ sql is obtained at the rising edge of the I +10 th cycle;
s34, referring to the second row in FIG. 1 and the fifth column in the clock diagram of FIG. 2, multiplying t _ R0_ j by a single-precision floating point value corresponding to c/2 by using a floating point multiplier, wherein c is the wave speed, and obtaining a one-way vertical distance R0_ j of a beam from a navigation path to a point to be calculated at the rising edge of the (I + 13) th period; referring to the third row in fig. 1 and the sixth column in the clock diagram of fig. 2, shifting x _ I _ sql by using a shift register, so that the shifted x _ I _ sql is output at the rising edge of the I +16 th cycle, and obtaining x _ I _ sql r _ dly used for aligning data;
s35, referring to the second row in FIG. 1 and the sixth column of the clock diagram in FIG. 2, using a floating-point multiplier to square R0_ j to obtain a result R0_ j _ sqr at the rising edge of the I +16 th cycle;
s36, referring to the first row and the second row in FIG. 1 and the seventh column in the clock diagram in FIG. 2, adding x _ I _ sqr _ dly and R0_ j _ sqr by using a floating point adder, and obtaining the square R _ sqr of the one-way slope distance from the point to be calculated to the coordinate origin at the rising edge of the I +19 th period;
s37, referring to the fourth row in fig. 1 and the eighth column in the clock diagram in fig. 2, performing a square operation on R _ sql using a floating-point square root, and obtaining a one-way slope distance R from a point to be calculated to the coordinate origin at the rising edge of the I +29 th cycle;
s38, referring to the fourth row in fig. 1 and the ninth column in the clock diagram in fig. 2, multiplying R by a single-precision floating point value corresponding to 2/c using a floating point multiplier, and obtaining a two-way delay time td used by the transducer to receive the echo of the point to be calculated at the rising edge of the I +32 th cycle;
s39, referring to the fourth row in fig. 1 and the tenth column in the clock diagram of fig. 2, subtracting the single-precision floating point value corresponding to the two-pass time Ts used by the shortest vertical distance from the airway to the imaging area from td by using the floating point subtractor, and obtaining Tr at the rising edge of the I +35 th cycle;
s310, referring to the fourth row in fig. 1 and the eleventh column in the clock diagram in fig. 2, multiplying Tr by a single-precision floating point value corresponding to the sampling frequency fs using a floating point multiplier, and obtaining a two-way delay _ pix of the point to be measured at the rising edge of the I +38 th cycle;
s311, referring to the fourth row in FIG. 1 and the twelfth column in the clock diagram of FIG. 2, the delay _ pix is converted from floating point to fixed point by using the floating point-fixed point conversion IP core, the delay _ fixed-1 operation is realized by using combinational logic, and the address code dly _ tb _ d _1, namely d-1, of the point to be measured is obtained at the rising edge of the I +40 th period.
Preferably, the S40 includes the steps of:
s41, referring to the first row in FIG. 1, forming a combinational logic circuit calculation value cnt _ k-cnt _ i using the values of cnt _ i and cnt _ k in S20;
s42, referring to the fourth row in fig. 1 and the twelfth to fourteenth columns in the clock diagram of fig. 2, the cnt _ k-cnt _ I is shifted by the shift register, and the rising edge in the I +40 th cycle acquires the address code dly _ tb _ k _ I, i.e., k-I, output in synchronization with the address code dly _ tb _ d _ 1.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (1)
1. A synthetic aperture address code generation method based on FPGA is characterized by comprising the following steps:
s10, dividing the address code generation into 16 paths by using FPGA parallel characteristics, and respectively processing the images with insufficient aperture length at two sides of aperture processing and the images with sufficient aperture length in the middle to form a high-speed parallel processing structure with three major paths and 3 x 16 minor paths;
s20, counting the resultant width of the aperture process, and performing different nested counts for the counters cnt _ i, cnt _ j, and cnt _ k in the three major paths: in the first path, the cnt _ i loops from cnt _ k to 0; cnt _ j counts from 0 to DIS _ LINE/16, counting the 16 rows, where cnt _ j changes once per cycle of cnt _ i; cnt _ k counts from 0 to AL-1, where cnt _ k changes once per cycle of cnt _ j completion, counting aperture accumulations of the image that are less than the number of aperture length points AL before the portion of the full aperture; in the second pass, cnt _ i cycles from AL-1 to 0; cnt _ j counts from 0 to DIS _ LINE/16, where cnt _ j changes once per cycle of cnt _ i completion; cnt _ k counts from AL to DIS _ DOOR-AL-1, where cnt _ k changes once per cycle of cnt _ j completion, counting the fraction of the image that falls within the full aperture size by aperture accumulation; in the third path, the cnt _ i loops to count from DIS _ DOOR-cnt _ k-1 to 0; cnt _ j counts from 0 to DIS _ LINE/16, where cnt _ j changes once per cycle of cnt _ i completion; counting cnt _ k from DIS _ DOOR-AL to DIS _ DOOR-1, wherein cnt _ k changes once every time cnt _ j completes one round of cycle, wherein, every time cnt _ i in three major-path counters completes one round of cycle, namely, when cnt _ i is 0, setting respective refresh _ flag to be high level for one period, giving a refresh signal for aperture processing, counting the aperture accumulation of the image which is less than the number of aperture length points AL after the part of the complete aperture, DIS _ LINE is a distance LINE corresponding row, DIS _ DOOR is a distance gate corresponding column, and AL is the number of aperture length points;
s30, generating an address code d-1;
s40, generating an address code k-i;
the S30 includes the steps of:
s31, according to the number rd _ num of input paths, a combinational logic circuit is used for adding (rd _ num-1) × (DIS _ LINE/16) to cnt _ j to obtain the pixel distance between a point to be calculated and an image edge in a path of 16 paths, a fixed point-floating point conversion IP core is used for converting the pixel distance into a 32-bit single-precision floating point number, and if the input data is in the I-th period, a corresponding value R0_ j _ pix is obtained on the rising edge of the I + 4-th period; using combinational logic to realize the calculation of cnt _ I-AL/2-1, obtaining a result, recording the result as x _ I, converting the result into a 32-bit single-precision floating point number by using a fixed point-floating point conversion IP core, and obtaining the result at the rising edge of the I +4 th period, recording the result as fp _ x _ I;
s32, calculating R0_ j _ pix multiplied by 1/fs through a floating point multiplier, wherein 1/fs is the reciprocal of sampling frequency, namely a 32-bit single-precision floating point value corresponding to a sampling period, a multiplication result is obtained at the rising edge of the I +7 th period and is marked as t _ pix, and the multiplication result is the two-pass time for a beam to reach a point to be measured from the edge of the image to be measured; performing fp _ x _ I multiplied by delta _ sa calculation through a floating point multiplier, wherein delta _ sa is half of the length of a real aperture, namely the azimuth resolution, a multiplication result is obtained at the rising edge of the I +7 th period and is recorded as x _ I _ rl, and the multiplication result is the real distance from a sampling point to be calculated to the origin of the airway coordinate;
s33, summing the t _ pix and the two-pass time Ts used by the shortest vertical distance from the airway to the imaging area by using a floating point adder, and obtaining the two-pass time t _ R0_ j corresponding to the vertical distance from the airway to the point to be calculated on the rising edge of the I +10 th period; carrying out square operation on x _ I _ rl by using a floating-point multiplier, and obtaining x _ I _ sqr at the rising edge of the I +10 th cycle;
s34, multiplying t _ R0_ j by a single-precision floating point value corresponding to c/2 by using a floating point multiplier, wherein c is the wave speed, and obtaining a one-way vertical distance R0_ j of a beam from a navigation path to a point to be calculated at the rising edge of the (I + 13) th period; shifting x _ I _ sql by using a shift register, and outputting the shifted x _ I _ sql at the rising edge of the (I + 16) th cycle to obtain x _ I _ sql _ dly which is used for aligning data;
s35, conducting square operation on R0_ j by using a floating-point multiplier, and obtaining a result R0_ j _ sqr at the rising edge of the I +16 th period;
s36, adding x _ I _ sqr _ dly and R0_ j _ sqr by using a floating point adder, and obtaining the square R _ sqr of the one-way slope distance from the point to be calculated to the coordinate origin at the rising edge of the I +19 th period;
s37, conducting evolution operation on the R _ sqr by using a floating point evolution device, and obtaining a one-way slope distance R from a point to be calculated to a coordinate origin at the rising edge of the I +29 th period;
s38, multiplying R by a single-precision floating point value corresponding to 2/c by using a floating point multiplier, and obtaining a two-way delay time td used by the transducer for receiving the echo of the point to be calculated on the rising edge of the I +32 th period;
s39, subtracting a single-precision floating point value corresponding to the two-pass time Ts used by the shortest vertical distance from the airway to the imaging area from td by using a floating point subtracter, and obtaining Tr at the rising edge of the I +35 th period;
s310, multiplying Tr by a single-precision floating point value corresponding to sampling frequency fs by using a floating point multiplier, and obtaining two-way delay _ pix of the point to be measured at the rising edge of the I +38 th period;
s311, converting the delay _ pix from a floating point to a fixed point by using a floating point-fixed point conversion IP core, realizing delay _ fixed-1 operation by using combinational logic, and obtaining an address code dly _ tb _ d _1, namely d-1, of the point to be measured at the rising edge of the I +40 th period;
the S40 includes the steps of:
s41, using the values of cnt _ i and cnt _ k in S20 to form a combinational logic circuit calculation value cnt _ k-cnt _ i;
s42, the cnt _ k-cnt _ I is shifted by the shift register, and at the rising edge of the I +40 th cycle, the address code dly _ tb _ k _ I, i.e., k-I, outputted in synchronization with the address code dly _ tb _ d _1 is acquired.
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