CN114626006B - FPGA (field programmable Gate array) realization method for real-time generation of CS (Circuit switched) algorithm compensation factor in radar imaging - Google Patents
FPGA (field programmable Gate array) realization method for real-time generation of CS (Circuit switched) algorithm compensation factor in radar imaging Download PDFInfo
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Abstract
The invention belongs to the technical field of radar imaging signals and Field Programmable Gate Array (FPGA), and particularly relates to a FPGA implementation method for real-time generation of a Circuit Switched (CS) algorithm compensation factor in radar imaging. The invention mainly provides a real-time generation module of a CS algorithm compensation factor realized based on FPGA, which consists of 21-level pipeline structures, wherein each layer of pipeline structure mainly utilizes a Floating Point IP core and a Cordic IP core to quickly calculate input parameters, so that the real-time generation of the CS algorithm compensation factor is realized, and the problem that the traditional DSP scheme has long calculation time and cannot meet the real-time requirement of system imaging under a high-speed clock is solved.
Description
Technical Field
The invention belongs to the technical field of radar imaging signals and Field Programmable Gate Array (FPGA), and particularly relates to a FPGA implementation method for real-time generation of a Circuit Switched (CS) algorithm compensation factor in radar imaging.
Background
Synthetic Aperture Radars (SAR) have all-weather working characteristics and high-resolution imaging accuracy all day long, and play a great role in remote sensing mapping in cloudy and foggy areas, military reconnaissance, national economic construction and the like. In recent years, with the rapid development of the hardware manufacturing level, the SAR real-time imaging system design is receiving more and more research. In the SAR imaging algorithm, the CS algorithm replaces matrix difference by phase multiplication, so that complex operation is avoided, phase information of an image can be well kept, and a good imaging effect is achieved. The CS algorithm involves the calculation of a large number of phase factors, and because the system needs to meet the requirement of real-time performance, the calculation efficiency of the phase factors of the CS algorithm influences the imaging processing speed of the CS algorithm.
In an early SAR imaging processing system based on a CS algorithm, a DSP is mostly adopted as a processor to carry out floating-point number operation, but with the continuous improvement of the requirements, the DSP gradually cannot meet the requirement of real-time performance. Nowadays, the FPGA can rapidly complete common basic operations in imaging processing such as addition, subtraction, multiplication, division, trigonometric function and the like, so that the FPGA-based CS algorithm multiplication factor real-time generation scheme has extremely high data processing rate.
The research institute of computational technology of Chinese academy of sciences Jian Fangjun, chu Chao, the paper published by Hanchengde, "Cs and Bro numerical computation and hardware design in Chirp Scaling imaging algorithm", provides a new polynomial approximation computation method easy for hardware implementation, and provides the computation accuracy and error analysis of the method. The method provided by the article reduces the calculation complexity, the actually measured imaging quality is equivalent to the original calculation, but the SAR image of the orientation sample point number 16384 and the distance sample point number 16384 is processed by the system, 8 seconds are needed to complete all the calculations of the three factors, and the real-time requirement of the calculation cannot be met.
The multiplication factor generation module receives a scene center distance R _ nc, a radar effective speed Vr, a pulse emission time width Tr, a radar working frequency f0, a distance direction sampling point Nr, an azimuth direction sampling point Na, a beam squint angle theta, a distance direction oversampling coefficient alpha, an azimuth direction oversampling coefficient belta, a bandwidth Bw and an antenna azimuth direction length La and is used for calculating the following three phase factors:
wherein s _ sc is used for the first phase multiplication to realize the Chirp Scaling operation, km is the distance modulation frequency transformed to the distance Doppler domain, D _ fn _ ref _ Vr is the migration factor at the reference frequency, D _ fn _ Vr _ mtx is a forming matrix, tr _ mtx is a distance time axis matrix, R _ ref is a reference target slant distance, and c is the optical speed.
Where H1 is used for the second phase multiplication to achieve range compression, SRC and uniform RCMC operation, fr _ mtx is the range frequency axis matrix.
Where Haz H2 is used for the third phase multiplication to perform the azimuth compression and phase correction operations, haz is the azimuth matched filter, H2 is the additional phase correction term, and R0_ RCMC is the slant distance that varies with distance.
Disclosure of Invention
Aiming at the problems, the invention provides an FPGA implementation method for generating a CS algorithm compensation factor in real time in radar imaging in order to meet the real-time requirement of calculation.
The technical scheme of the invention is as follows:
the FPGA implementation method for real-time generation of the CS algorithm compensation factor in radar imaging is characterized by comprising the following steps of:
s1, radar echo data are obtained;
s2, processing radar echo data by adopting a CS (circuit switched) algorithm to obtain a radar imaging image, wherein the processing process of the CS algorithm on the radar echo data comprises four times of FFT (fast Fourier transform) and three times of phase multiplication, the first time of FFT is an azimuth direction FFT, the data is converted into a range Doppler domain, and the first time of phase multiplication is carried out by adopting a Chirp Scaling phase factor to make migration tracks of all targets consistent; performing a second FFT, wherein the second FFT is a distance direction FFT, converting the data to a two-dimensional frequency domain, and performing a second phase multiplication by adopting an RCMC and a distance direction compression factor to complete distance compression, SRC and consistent RCMC; performing a third FFT which is a range-to-IFFT, converting the data back to a range-Doppler domain, and performing a third phase multiplication by using phase correction and a direction compression factor; performing a fourth FFT, wherein the fourth FFT is an azimuth IFFT to obtain an output image;
the Chirp Scaling phase factor, the RCMC, the distance direction compression factor, the phase correction and the orientation compression factor are CS algorithm multiplication factors, the CS algorithm multiplication factors are generated in real time through a CS algorithm compensation factor real-time generation module, and the CS algorithm compensation factor real-time generation module is realized in an FPGA-based mode, and specifically comprises the following steps: adopting a 21-stage pipeline structure, and calculating input radar signal parameters by using a Floating Point IP core and a Cordic IP core in each layer of water flow structure so as to obtain CS algorithm multiplication factors including a Chirp Scaling phase factor, an RCMC (remote control center) and a distance direction compression factor, a phase correction factor and a direction compression factor; the real-time generation control mode of the CS algorithm compensation factor real-time generation module is that the effective signal flag bit output by the FFT module is received through the control signal port, and the corresponding factor output effective signal flag bit is set at the output port, so that the corresponding CS algorithm multiplication factor required by the next phase multiplication is obtained according to the specific operation of the last FFT during each phase multiplication.
Specifically, the multiplication factor of the CS algorithm includes two data output sequences, which are:
a. outputting in azimuth order:
a 1,1 、a 1,2 、a 1,3 、a 1,4 、
a 2,1 、a 2,2 、a 2,3 、a 2,4
……
a 8191,1 、a 8191,2 、a 8191,3 、a 8191,4
a 8192,1 、a 8192,2 、a 8192,3 、a 8192,4
and four-way factors, namely outputting the following four azimuth factors until the current four azimuth factors are output:
a 1,5 、a 1,6 、a 1,7 、a 1,8
a 2,5 、a 2,6 、a 2,7 、a 2,8
……
a 8191,5 、a 8191,6 、a 8191,7 、a 8191,8
a 8192,5 、a 8192,6 、a 8192,7 、a 8192,8
b. sequentially outputting in the distance direction:
a 1,1 、a 2,1 、a 3,1 、a 4,1
a 1,2 、a 2,2 、a 3,2 、a 4,2
……
a 1，8191 、a 2，8191 、a 3,8191 、a 4,8191
a 1，8192 、a 2，8192, 、a 3，8192, 、a 4，8192
and four-way factors, namely outputting the following four distance direction factors until the current four distance direction factors are output:
a 1,1 、a 2,1 、a 3,1 、a 4,1
a 1,2 、a 2,2 、a 3,2 、a 4,2
……
a 1，8191 、a 2，8191 、a 3,8191 、a 4,8191
a 1，8192 、a 2，8192 、a 3，8192 、a 4，8192
until the factor output corresponding to one frame of data is completed.
In the scheme, the parameter input bit width of the real-time generation module for the multiplication factors of the CS algorithm is 32bits, the bit width of the output factors is 32bits, the middle part of the module performs data processing by using the bit width of 64bits, and the module clock is 300MHz. The multiplication factor generation module structure is a 21-stage pipeline structure, each stage of pipeline has fixed first time delay, each stage of pipeline instantiates a large number of Floating Point IP cores and Cordic IP cores for mathematical operation, the Floating Point IP cores and the Cordic IP cores both adopt pipeline structures, and the first time delay of the whole system is the sum of the first time delay of each stage of the 21-stage pipeline. The Floating Point IP core is instantiated into Add, gather, divide, square-root, fixed-to-Float, float-to-Fixed, float-to-Float and other modes to realize functions of addition, subtraction, multiplication, division, squaring, fixed Point number and Floating Point number interconversion of data, and the Cordic IP core is instantiated into a Sin and Cos mode to realize sine and cosine solving function.
The method has the advantages that the real-time generation of the compensation factor of the CS algorithm is realized, and the problem that the traditional DSP scheme has long calculation time and cannot meet the real-time requirement of system imaging under a high-speed clock is solved.
Drawings
FIG. 1 is a flow chart of a method of the present invention;
FIG. 2 is a schematic diagram of a multiplicative factor generation module;
FIG. 3 is a schematic diagram of an output factor selection scheme;
FIG. 4 is a schematic diagram of a four-way factor generation module;
FIG. 5 is a schematic diagram of the multiplicative factor azimuth output sequence;
FIG. 6 is a schematic diagram of the multiplication factor distance to output sequence.
Detailed Description
The invention is described in detail below with reference to the accompanying drawings;
the invention provides an FPGA implementation mode for real-time generation of compensation factors based on a CS algorithm in radar imaging signal processing.
The specific flow is shown in fig. 1, the CS algorithm mainly includes four times of FFT and three times of phase multiplication, and the factor required for the three times of phase multiplication is generated by the multiplication factor real-time generation module, specifically:
after the data are transformed to a range-Doppler domain through the azimuth FFT, a Chirp Scaling phase factor is output by the multiplication factor real-time generation module, and Chirp Scaling operation is realized through phase multiplication, so that migration tracks of all targets are consistent. This is the first step phase multiplication.
Transforming the data into a two-dimensional frequency domain through distance direction FFT; and the multiplication factor real-time generation module outputs a second phase factor phase multiplication to finish the distance compression, the SRC and the consistent RCMC of the data. This is the second phase multiplication.
After the data is converted back to a range-Doppler domain through range-to-IFFT; and the multiplication factor real-time generation module outputs a third phase factor for phase multiplication to realize azimuth compression and phase correction, which is the final phase multiplication.
The multiplication factor generation module framework is shown in fig. 2, the whole multiplication factor generation module structure is a 21-stage pipeline structure, each stage of pipeline has a fixed first time delay, each stage of pipeline instantiates a large number of Floating Point IP cores and Cordic IP cores for mathematical operation, both the Floating Point IP cores and the Cordic IP cores adopt pipeline structures, and the first time delay of the whole system is the sum of the first time delays of each stage of the 21-stage pipeline. The Floating Point IP core is instantiated into Add, gather, divide, square-root, fixed-to-Float, float-to-Fixed, float-to-Float and other modes to realize functions of addition, subtraction, multiplication, division, squaring, fixed Point number and Floating Point number interconversion of data, and the Cordic IP core is instantiated into a Sin and Cos mode to realize sine and cosine solving function.
The multiplication factor generation module receives a scene center distance R _ nc, a radar effective speed Vr, a pulse transmission time width Tr, a radar working frequency f0, a distance direction sampling point Nr, an azimuth direction sampling point Na, a beam squint angle theta, a distance direction oversampling coefficient alpha, an azimuth direction oversampling coefficient belta, a bandwidth Bw and an antenna azimuth direction length La and is used for calculating three phase factors.
The phase factors required by the third phase multiplication are generated by a CS algorithm multiplication factor real-time generation module, an input port of the CS algorithm multiplication factor real-time generation module comprises a parameter input port and a control signal input port, the parameter input port is used for receiving radar parameters, the control signal port is used for receiving a valid signal zone bit output by the FFT module and is used for controlling the multiplication factor real-time generation module, when the control signal input port is valid, the parameter input port is enabled to receive the parameters, the first-stage flow structure is calculated, an enabling signal is output and serves as an input enabling signal of the next-stage flow structure. The output port of the last stage of pipeline structure, namely the output port of the CS algorithm multiplication factor real-time generation module, comprises a factor output port and a factor output effective signal flag bit, and four factors and effective signals thereof are output each time and are used for processing of subsequent modules.
The multiplication factor real-time generation module has the parameter input bit width of 32bits, the output factor bit width of 32bits, and the middle part of the module performs data processing with the bit width of 64 bits. The whole system is in a single-precision floating point number form when parameters are input and factors are output, and basically in a double-precision floating point number form at the middle processing flow part of the module.
The whole multiplication factor real-time generation module adopts a time-sharing multiplexing mode, corresponding factors are correspondingly output at the time of three-time phase multiplication, and the specific time-sharing multiplexing mode is shown in fig. 3:
after the data is subjected to the first azimuth FFT, when the output data is effective, the multiplication factor real-time generation module outputs a Chirp Scaling phase factor to carry out the first phase multiplication; after the data is subjected to first distance direction FFT, when the output data is effective, the multiplication factor real-time generation module outputs a distance compression correction factor and a distance migration correction factor to be subjected to second phase multiplication; and after the data is subjected to the first distance-to-IFFT, when the output data is effective, the real-time multiplication factor generation module outputs azimuth compression and a residual phase compensation factor to carry out third phase multiplication.
In the hardware implementation scheme of the CS algorithm, data streams are all transmitted and processed by four parallel data paths, so that corresponding multiplication factors are also output in the form of four factor streams, a fixed difference exists between two adjacent data paths, and a module architecture for generating idea factors by using the difference is shown in fig. 4: the submodule receives the first path factor and the fixed difference value, adds the difference value and the first path factor to obtain a next path factor, and beats the first path factor to be synchronous. Repeating the rule for four times to obtain four parallel factors.
The real-time multiplication factor generation module generates and outputs corresponding multiplication factors according to the data output sequence after FFT processing, and the specific sequence mainly comprises the following two modes:
the multiplication factors are output in azimuth order as shown in FIG. 5, where a is output first 1,1 、a 1,2 、a 1,3 、a 1,4 ；a 2,1 、a 2,2 、a 2,3 、a 2,4 ……a 8191,1 、a 8191,2 、a 8191,3 、a 8191,4 ；a 8192,1 、a 8192,2 、a 8192,3 、a 8192,4 Four-way factors, until the current four-column azimuth factor is output, the next four-column azimuth factor a is output 1,5 、a 1,6 、a 1,7 、a 1,8 ；a 2,5 、a 2,6 、a 2,7 、a 2,8 ……a 8191,5 、a 8191,6 、a 8191,7 、a 8191,8 ；a 8192,5 、a 8192,6 、a 8192,7 、a 8192,8 Until the factor output corresponding to one frame of data is completed.
The multiplication factors are output in distance-to-output order as shown in FIG. 6, where a is output first 1,1 、a 2,1 、a 3,1 、a 4,1 ；a 1,2 、a 2,2 、a 3,2 、a 4,2 ……a 1，8191 、a 2，8191 、a 3,8191 、a 4,8191 ；a 1，8192 、a 2，8192, 、a 3，8192, 、a 4，8192, Four-way factor, until the current four-column distance direction factor is completely output, the next four-column distance direction factor a is output 1,1 、a 2,1 、a 3,1 、a 4,1 ；a 1,2 、a 2,2 、a 3,2 、a 4,2 ……a 1，8191 、a 2，8191 、a 3,8191 、a 4,8191 ；a 1，8192 、a 2，8192 、a 3，8192 、a 4，8192 Until the factor output corresponding to one frame of data is completed.
Claims (2)
1. The FPGA implementation method for real-time generation of the CS algorithm compensation factor in radar imaging is characterized by comprising the following steps of:
s1, radar echo data are obtained;
s2, processing radar echo data by adopting a CS (circuit switched) algorithm to obtain a radar imaging image, wherein the processing process of the CS algorithm on the radar echo data comprises four times of FFT (fast Fourier transform) and three times of phase multiplication, the first time of FFT is an azimuth direction FFT, the data is converted into a range Doppler domain, and the first time of phase multiplication is carried out by adopting a Chirp Scaling phase factor to make migration tracks of all targets consistent; performing a second FFT, wherein the second FFT is a distance direction FFT, converting the data to a two-dimensional frequency domain, and performing a second phase multiplication by adopting an RCMC and a distance direction compression factor to complete distance compression, SRC and consistent RCMC; performing a third FFT which is a range-to-IFFT, converting the data back to a range-Doppler domain, and performing a third phase multiplication by using phase correction and a direction compression factor; performing a fourth FFT, wherein the fourth FFT is an azimuth IFFT to obtain an output image;
the Chirp Scaling phase factor, the RCMC, the distance direction compression factor, the phase correction and the orientation compression factor are CS algorithm multiplication factors, the CS algorithm multiplication factors are generated in real time through a CS algorithm compensation factor real-time generation module, and the CS algorithm compensation factor real-time generation module is realized in an FPGA-based mode, and specifically comprises the following steps: adopting a 21-stage pipeline structure, and calculating input radar signal parameters by using a Floating Point IP core and a Cordic IP core in each layer of water flow structure so as to obtain CS algorithm multiplication factors including a Chirp Scaling phase factor, an RCMC (remote control center) and a distance direction compression factor, a phase correction factor and a direction compression factor; the real-time generation control mode of the CS algorithm compensation factor real-time generation module is that the effective signal flag bit output by the FFT module is received through the control signal port, and the corresponding factor output effective signal flag bit is set at the output port, so that the corresponding CS algorithm multiplication factor required by the next phase multiplication is obtained according to the specific operation of the last FFT during each phase multiplication.
2. The FPGA implementation method for real-time generation of the CS algorithm compensation factor in radar imaging according to claim 1, wherein the CS algorithm multiplication factor comprises two data output sequences, respectively:
a. outputting in azimuth order:
a 1,1 、a 1,2 、a 1,3 、a 1,4 、
a 2,1 、a 2,2 、a 2,3 、a 2,4
……
a 8191,1 、a 8191,2 、a 8191,3 、a 8191,4
a 8192,1 、a 8192,2 、a 8192,3 、a 8192,4
and four-way factors, namely outputting the following four azimuth factors until the current four azimuth factors are output:
a 1,5 、a 1,6 、a 1,7 、a 1,8
a 2,5 、a 2,6 、a 2,7 、a 2,8
……
a 8191,5 、a 8191,6 、a 8191,7 、a 8191,8
a 8192,5 、a 8192,6 、a 8192,7 、a 8192,8
b. sequentially outputting in the distance direction:
a 1,1 、a 2,1 、a 3,1 、a 4,1
a 1,2 、a 2,2 、a 3,2 、a 4,2
……
a 1，8191 、a 2，8191 、a 3,8191 、a 4,8191
a 1，8192 、a 2，8192 、a 3，8192 、a 4，8192
and four-way factors, namely outputting the following four distance direction factors until the current four distance direction factors are output:
a 5,1 、a 6,1 、a 7,1 、a 8,1
a 5,2 、a 6,2 、a 7,2 、a 8,2
……
a 5，8191 、a 6，8191 、a 7,8191 、a 8,8191
a 5，8192 、a 6，8192 、a 7，8192 、a 8，8192
until the factor output corresponding to one frame of data is completed.
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