CN106936433B

CN106936433B - Charge domain phase error calibration circuit and DDS circuit adopting same

Info

Publication number: CN106936433B
Application number: CN201710135890.0A
Authority: CN
Inventors: 陈珍海; 万书芹; 周德金; 何宁业; 刘琦; 宁仁霞; 吕海江
Original assignee: Huangshan University
Current assignee: Huangshan University
Priority date: 2017-03-09
Filing date: 2017-03-09
Publication date: 2020-01-10
Anticipated expiration: 2037-03-09
Also published as: CN106936433A

Abstract

The invention provides a charge domain phase error calibration circuit and a DDS (direct digital synthesizer) adopting the same. The charge domain phase error calibration circuit comprises: the device comprises a charge domain phase error detection amplifying circuit, a K-bit charge domain analog-to-digital converter, a control circuit, a ROM module, an SRAM module, a first delay circuit and a second delay circuit. The DDS using the charge domain phase error calibration circuit comprises: the circuit comprises a phase accumulator, a phase amplitude converter, an N-bit current mode DAC, a charge domain phase error calibration circuit, a clock generation circuit and a mode control circuit. The charge domain phase error calibration circuit and the DDS adopting the calibration circuit can automatically compromise and select the calibration precision and speed according to the system precision and hardware overhead, and have the characteristic of low power consumption.

Description

Charge domain phase error calibration circuit and DDS circuit adopting same

Technical Field

The invention relates to an error calibration circuit, in particular to a DDS phase error calibration circuit adopting a charge domain signal processing technology and a DDS adopting the same.

Background

The direct digital frequency synthesis technology is a technology that synthesizes signals with various required frequencies by a digital means, and finally converts the signals into analog signals to be output by a digital-to-analog converter. The technology has the following characteristics: the advantages of programmability, fast frequency hopping, high resolution, high frequency modulation precision and the like become one of the main technologies in the current frequency synthesis technology, and the method is widely applied to the communication fields of mobile communication, military and commercial radar systems and the like.

A direct digital frequency synthesizer (DDS) is mainly composed of three modules: a phase accumulator, a phase-to-amplitude converter and a digital-to-analog converter (DAC). The overall DDS system typically has two inputs: a reference clock fs and a frequency control word X. The phase accumulator continuously performs linear phase accumulation on the frequency control word when each clock pulse is input under the control of a clock. The data output by the phase accumulator is the phase of the composite signal and the output frequency of the phase accumulator is the frequency of the signal output by the direct digital frequency synthesizer. The phase value output by the accumulator is intercepted and input into a phase amplitude converter, and the digitized amplitude value corresponding to the phase value is output through operation and conversion. The digital quantity is converted into analog quantity by a digital-to-analog converter, and the analog quantity is smoothed by a low-pass filter to filter out unnecessary sampling signals and output sine or cosine signals with pure frequency.

It can be seen from the working principle of the DDS that due to the influence of factors such as clock non-ideal characteristics, asynchronous DAC input signals, asynchronous DAC internal module timing, power supply, and signal crosstalk that may exist in circuit design, a phase error may exist in the output signal of the DAC. In practical application, due to fluctuation of a processing technology, change of a working environment and the like, certain phase errors of the DDS have certain randomness, and the specific expression is that the phase errors of different DDS chips are different. In applications such as phase control radars which require precise control of the consistency of the DDS phase errors, the DDS chips cannot meet the precision requirement due to the problem caused by the inconsistency of the phase errors among the DDS chips. Therefore, it is very practical to design a high-precision phase error calibration circuit integrated in a DDS chip.

Disclosure of Invention

The invention aims to overcome the defects in the prior art, provides a DDS phase error calibration circuit adopting a charge domain signal processing technology and a DDS adopting the same, and can realize high-precision phase error calibration.

The purpose of the invention can be realized by the following technical scheme: the charge domain phase error calibration circuit structurally comprises: the device comprises a charge domain phase error detection amplifying circuit, a K-bit charge domain analog-to-digital converter, a control circuit, a ROM module, an SRAM module, a first delay circuit and a second delay circuit;

the connection relationship of the circuits is as follows: the first input end and the second input end of the charge domain phase error detection amplifying circuit are respectively connected to a signal output differential port of an N-bit current mode DAC in the DDS chip, the control input end of the charge domain phase error detection amplifying circuit is connected to a K-bit selection code output port of the control circuit, and the differential voltage output end of the charge domain phase error detection amplifying circuit is connected to the differential voltage input end of a K-bit charge domain analog-to-digital converter; the K bit quantization code of the K bit charge domain analog-to-digital converter is output to an error input port of the control circuit; a ROM control port of the control circuit outputs a control signal to a ROM module, an SRAM control port of the control circuit outputs a control signal to an SRAM module, a first K bit delay code output end of the control circuit is connected to a second input port of the first delay circuit, a second K bit delay code output end of the control circuit is connected to a second input port of the second delay circuit, and a calibration control signal Ctrl output port of the control circuit is simultaneously connected to calibration control signal Ctrl input ports of the charge domain phase error detection and amplification circuit, the K bit charge domain analog-to-digital converter, the first delay circuit and the second delay circuit; a first input port of the first delay circuit is connected with a first N-bit calibration code output end of the ROM module, a third input port of the first delay circuit is connected with an X-bit phase control input code, and an output port of the first delay circuit outputs the X-bit conversion code to a phase amplitude converter in the DDS chip; a first input port of the second delay circuit is connected with a second N-bit calibration code output end of the ROM module, a third input port of the second delay circuit is connected with an N-bit amplitude control input code, and an output port of the second delay circuit outputs the N-bit conversion code to an N-bit current mode DAC in the DDS chip; wherein X and N are any positive integer, and K is a positive integer not greater than N.

The working mode of the charge domain phase error calibration circuit comprises a calibration mode and a compensation mode; when the circuit works, the circuit firstly enters a calibration mode and then enters a compensation mode;

when the DDS chip enters a calibration mode, an X-bit phase control input code, an N-bit amplitude control input code, a first K-bit delay code and a second K-bit delay code are invalid, a first N-bit calibration code is input into a first delay circuit, a second N-bit calibration code is input into a second delay circuit, and a charge domain phase error calibration circuit sequentially calibrates phase errors of an N-bit current mode DAC and a phase amplitude converter in the DDS chip;

when the DDS chip enters a compensation mode, an X-bit phase control input code and an N-bit amplitude control input code are respectively input into a first delay circuit and a second delay circuit, a first N-bit calibration code and a second N-bit calibration code are invalid, a first K-bit delay code and a second K-bit delay code are valid, and a charge domain phase error calibration circuit simultaneously carries out phase compensation on an N-bit current mode DAC and a phase amplitude converter in the DDS chip.

When entering the calibration mode, the circuit operates in the following sequence:

1. firstly, carrying out phase error calibration on an N-bit current mode DAC in a DDS chip:

the control circuit firstly controls the charge domain phase error detection amplifying circuit, the K-bit charge domain analog-to-digital converter and the second delay circuit to enter a calibration mode through a Ctrl signal, and simultaneously outputs a K-bit selection code to the charge domain phase error detection amplifying circuit to start phase error calibration on an N-bit current mode DAC in the DDS chip;

then the control circuit generates a first group of K bit selection codes, and simultaneously controls the ROM module to generate a first group of second N bit calibration codes, and the N bit current mode DAC obtains a first group of differential output current signals Iop and Ion corresponding to the first group of second N bit calibration codes; the charge domain phase error detection amplifying circuit detects the Iop-Ion amount and processes the Iop-Ion amount to obtain an error voltage; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the error voltage to obtain a first group of K-bit quantization codes and outputs the first group of K-bit quantization codes to the control circuit; the control circuit stores the received first group of K-bit quantization codes in an SRAM module to finish the phase error quantization of an N-bit current mode DAC circuit in the DDS chip to be calibrated under an input condition;

then, the control circuit generates a second group of K bit selection codes, and simultaneously controls the ROM module to generate a second group of second N bit calibration codes, and the second group of K bit quantization codes can be obtained and output to the control circuit after being processed by the N bit current mode DAC, the charge domain phase error detection amplifying circuit and the K bit charge domain analog-to-digital converter; the control circuit stores the received second group of K-bit quantization codes in an SRAM module to finish the phase error quantization of an N-bit current mode DAC circuit in the DDS chip to be calibrated under two input conditions;

according to the circulation, when an L-th group of second N-bit calibration codes and an L-th group of K-bit selection codes are generated, an L-th group of K-bit quantization codes are obtained and stored in the SRAM module, an operation circuit in the control circuit calculates the L-th group of K-bit quantization codes stored in the K-bit register group to obtain a second K-bit delay code; the control circuit outputs the second K bit delay code to the second delay circuit at the moment, keeps the second K bit delay code unchanged and finishes the phase error calibration of the N bit current mode DAC in the DDS chip;

2. and (3) carrying out phase error calibration on a phase amplitude converter in the DDS chip:

the control circuit controls the first delay circuit to enter a calibration mode through a Ctrl signal, and simultaneously outputs a K-bit selection code to the charge domain phase error detection amplifying circuit to start to carry out phase error calibration on a phase amplitude converter in the DDS chip;

the control circuit controls the ROM module to generate a first N-bit calibration code, the first delay circuit, the charge domain phase error detection amplifying circuit and the K-bit charge domain analog-to-digital converter are used for obtaining a first K-bit delay code and outputting the first K-bit delay code to the first delay circuit by adopting the same step and method as the phase error calibration of the N-bit current mode DAC in the DDS chip, and meanwhile, the first K-bit delay code is kept unchanged, so that the phase error calibration of the phase amplitude converter in the DDS chip is completed; at this time, the calibration mode of the charge domain phase error calibration circuit ends;

in the calibration process, each set of the first N-bit calibration code, the second N-bit calibration code and the K-bit selection code generated by the control circuit at the same time must correspond to one another, that is: the J-th group of the first N-bit calibration code and the second N-bit calibration code must be matched with the J-th group of the K-bit selection code for use; wherein L is not more than 2^KJ is a positive integer not greater than L.

Further, the charge domain phase error detection amplifying circuit includes: the circuit comprises a current detection resistor, a reference clock generating circuit, a phase discriminator, a loop filter and a charge domain voltage amplifying circuit;

as described aboveThe connection relationship of the circuit is as follows: two ends of the current detection resistor are respectively connected to a first input end and a second input end of the charge domain phase error detection amplifying circuit and are respectively connected to a first input end and a second input end of the phase discriminator; the reference clock generating circuit generates a reference clock and is connected to a third input end of the phase discriminator under the control of the K bit selection code; the phase discriminator further compares the phases of the signals of the 3 input ends to obtain a phase error signal; the phase error signal is filtered by a loop filter to obtain a voltage signal V_i；V_iThe error signals Vop and Von are obtained through the amplification of the charge domain voltage amplifying circuit.

Further, the K-bit charge domain analog-to-digital converter includes: the P-stage production line sub-stage circuit based on the charge domain signal processing technology is used for carrying out various processing on the charge packets obtained by sampling to complete analog-to-digital conversion and margin amplification, inputting the output digital code of each sub-stage circuit into a delay synchronous register, and enabling the charge packets output by each sub-stage circuit to enter the next stage to repeat the process; the P +1 stage, which is also the last stage of A-bit Flash analog-to-digital converter circuit, converts the charge packet transmitted from the P stage into a voltage signal again, performs the analog-to-digital conversion work of the last stage, and inputs the output digital code of the stage circuit into a delay synchronous register, and the stage circuit only completes the analog-to-digital conversion without margin amplification; the delay synchronous register is used for carrying out delay alignment on the digital code output by each sub-flow water level and inputting the aligned digital code into the digital correction module; the digital correction circuit module is used for receiving the output digital code of the synchronous register and carrying out shift addition on the received digital code to obtain an R-bit digital output code of the analog-to-digital converter; wherein R is a positive integer, and P and A are both positive integers not greater than R.

Further, the first delay circuit and the second delay circuit both use the same delay circuit, and the structure includes: n delay buffer units and N K-bit delay registers; the delay code input ends of the first K-bit delay register to the Nth K-bit delay register are all connected to the K-bit delay code, and the control signal input ends are all connected to the calibration control signal Ctrl; the input ends of delay codes of the first delay buffer unit to the Nth delay buffer unit are respectively connected to the output ends of the delay codes of the first K-bit delay register to the Nth K-bit delay register, the data output ends of the first delay buffer unit to the Nth delay buffer unit are respectively connected to the 1 st bit conversion code to the Nth bit conversion code and output, the input ends of first control signals of the first delay buffer unit to the Nth delay buffer unit are all connected to a reverse signal Ctrln of a calibration control signal Ctrl, and the input ends of second control signals of the first delay buffer unit to the Nth delay buffer unit are all connected to the signal Ctrl.

The delay circuit can work in two modes of calibration and compensation;

when in a calibration mode, a Ctrl signal is valid, a 1 st bit conversion code to an Nth bit input code are invalid, the input codes have no influence on the output of the N bit conversion code, the 1 st bit calibration code to the Nth bit calibration code respectively pass through a first delay buffer circuit to an Nth delay buffer circuit to obtain the 1 st bit conversion code to the Nth bit conversion code and output the 1 st bit conversion code to the Nth bit conversion code, and a K bit delay code is input into a first K bit delay register to an Nth K bit delay register and is latched and kept unchanged; in the compensation mode, the Ctrln signal is valid, the 1 st to Nth bit conversion codes are valid and output after passing through the delay buffer circuit, the 1 st to Nth bit conversion codes are invalid, and the K bit delay codes stored in the first to N K bit delay registers are input into the first to Nth delay buffer circuits for delay compensation.

Further, the control circuit includes: the circuit comprises a core control circuit, a Read Only Memory (ROM) read circuit, a first delay code generating circuit, a second delay code generating circuit, a selection code generating circuit, an arithmetic circuit, a Static Random Access Memory (SRAM) read-write circuit and a K-bit register;

the connection relationship of the circuits is as follows: a first output end of the core control circuit is connected to an input end of the ROM reading circuit, a second output end of the core control circuit is connected to a control input end of the first delay code generating circuit, a third output end of the core control circuit is connected to a control input end of the second delay code generating circuit, a fourth output end of the core control circuit is connected to a control input end of the arithmetic circuit, a fifth output end of the core control circuit is connected to a control input end of the selection code generating circuit, a sixth output end of the core control circuit generates a calibration control signal Ctrl, a seventh output end of the core control circuit is simultaneously connected to a K-bit register and a control input end of the SRAM reading and writing circuit, and an input end of the core control circuit is connected to a calibration start control; the ROM reading circuit generates a ROM address code according to a control instruction of the core control circuit; the data input end of the arithmetic circuit receives data sent by the output end of the SRAM read-write circuit and generates a first K-bit error code and a second K-bit error code according to a control instruction of the core control circuit; the data input end of the first delay code generating circuit receives a first K-bit error code sent by the data output end of the arithmetic circuit and generates a first K-bit delay code according to a control instruction of the core control circuit; the data input end of the second delay code generating circuit receives a second K-bit error code sent by the data output end of the arithmetic circuit and generates a second K-bit delay code according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the data input end of the K-bit register receives the K-bit quantization code sent by the output end of the K-bit charge domain analog-to-digital converter, and sends the data stored in the K-bit charge domain analog-to-digital converter to the SRAM read-write circuit according to a control instruction of the core control circuit; the SRAM read-write circuit generates an SRAM address data code according to a control instruction of the core control circuit, and reads and writes data into the SRAM module.

The DDS circuit using the above charge domain phase error calibration circuit structurally includes the charge domain phase error calibration circuit, and further includes: the device comprises a phase accumulator, a phase amplitude converter, an N-bit current mode DAC, a clock generation circuit and a mode control circuit;

the connection relationship of the circuit is as follows: a first calibration control signal output end of the mode control circuit is connected to a calibration signal control end of the phase accumulator, the phase amplitude converter and the N-bit current-mode DAC, a second calibration control signal output end of the mode control circuit is connected to a calibration signal control end of the clock generation circuit, and a third calibration control signal output end of the mode control circuit is connected to a calibration signal control end of the charge domain phase error calibration circuit; the output of the phase accumulator is connected to the input end of an X-phase control input code of the charge domain phase error calibration circuit; the phase control input end of the phase amplitude converter is connected to the output end of an X-bit conversion code of the charge domain phase error calibration circuit, and the N-bit amplitude control input code output by the phase amplitude converter is connected to the input end of an N-bit amplitude control input code of the charge domain phase error calibration circuit; the N-bit current mode DAC generates output differential current signals Iop and Ion according to the control of the first calibration control signal, the N-bit conversion code, the working clock f0 and the calibration clock fc; the charge domain phase error calibration circuit detects and processes differential current signals Iop and Ion under the control of a calibration clock fc and a third calibration control signal to obtain an X-bit conversion code and an N-bit conversion code which are subjected to phase compensation and output to a phase amplitude converter and an N-bit current mode DAC respectively; the clock generation circuit generates a calibration clock fc and a working clock f0 under the control of the second calibration control signal, the working clock f0 is used for controlling the calibration clock phase accumulator, the phase-amplitude converter and the N-bit current-mode DAC, and the calibration clock fc is used for controlling the phase-amplitude converter, the N-bit current-mode DAC and the charge domain phase error calibration circuit.

The DDS circuit has two working modes of a calibration mode and a compensation mode; when the circuit works, the circuit firstly enters a calibration mode and then enters a compensation mode;

when the circuit enters a calibration mode, the mode control circuit controls the clock generation circuit to close the working clock f0 through a second calibration control signal, and outputs a calibration clock fc; the mode control circuit also controls the charge domain phase error calibration circuit to start phase error calibration on the DDS circuit through a third calibration control signal; the mode control circuit also controls the phase accumulator, the phase amplitude converter and the N-bit current mode DAC to enter a calibration mode through the first calibration control signal; the phase amplitude converter, the charge domain phase error calibration circuit and the N-bit current mode DAC start the DDS phase error calibration work under the control of a calibration clock fc; firstly, calibrating a DDS phase error caused by a phase error of an N-bit current mode DAC, and then calibrating the DDS phase error caused by the phase error of a phase amplitude converter, wherein an X-bit phase control input code and an N-bit amplitude control input code are in an invalid state;

when entering the compensation mode, the mode control circuit controls the clock generation circuit to close the calibration clock fc through the second calibration control signal, and outputs a working clock f 0; the mode control circuit also controls the charge domain phase error calibration circuit to start phase error compensation on the DDS circuit through a third calibration control signal, and outputs the X-bit conversion code and the N-bit conversion code subjected to the phase compensation to the phase amplitude converter and the N-bit current mode DAC respectively; the mode control circuit also controls the phase accumulator, the phase-amplitude converter and the N-bit current-mode DAC to enter a normal working mode through the first calibration control signal, and the phase-amplitude converter and the N-bit current-mode DAC work under the control of the working clock f 0; the X-bit phase control input code and the N-bit amplitude control input code start to be valid.

The invention has the advantages that: the high-precision phase error calibration circuit can automatically compromise and select the calibration precision according to the system precision and the hardware overhead; by adopting a charge domain signal processing technology, an operational amplifier is not used in the aspect of error detection processing, and the power consumption is low; and the error signal is quantized by adopting a charge domain ADC (analog to digital converter), and the error compensation method completely adopts a digital signal processing technology, so that the minimization of power consumption is further realized.

Drawings

FIG. 1 is a block diagram of a charge domain phase error calibration circuit according to the present invention.

FIG. 2 is a block diagram of a charge domain phase error detection amplifying circuit according to the present invention.

FIG. 3 is a schematic diagram of a charge domain voltage amplifying circuit according to the present invention.

FIG. 4 is a waveform diagram illustrating the operation of the charge domain voltage amplifying circuit according to the present invention.

Fig. 5 is a block diagram of the circuit structure of the phase detector of the present invention.

FIG. 6 is a block diagram of a reference clock generating circuit according to the present invention.

Fig. 7 is a circuit block diagram of a charge domain analog-to-digital converter according to the present invention.

FIG. 8 is a block diagram of a charge domain pipeline sub-stage according to the present invention.

FIG. 9 is a block diagram of a delay circuit according to the present invention.

FIG. 10 is a block diagram of a control circuit according to the present invention.

Fig. 11 is a block diagram of a DDS circuit employing a charge domain phase error calibration circuit according to the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a charge domain phase error calibration circuit according to the present invention. The charge domain phase error calibration circuit comprises: a charge domain phase error detection amplifying circuit 10, a K-bit charge domain analog-to-digital converter 11, a control circuit 12, a ROM block 14, an SRAM block 13, and a first delay circuit 15 and a second delay circuit 16.

The connection relationship of the circuits is as follows: a first input end and a second input end of the charge domain phase error detection amplifying circuit 10 are respectively connected to a signal output differential port (corresponding to signals Iop and Ion) of an N-bit current mode DAC115 in the DDS chip, a control input end of the charge domain phase error detection amplifying circuit 10 is connected to a K-bit selection code output port of the control circuit 12, and a differential voltage output end of the charge domain phase error detection amplifying circuit 10 is connected to a differential voltage input end of a K-bit charge domain analog-to-digital converter 11; the K bit quantization code of the K bit charge domain analog-to-digital converter 11 is output to an error input port of the control circuit 12; a ROM control port of the control circuit 12 outputs a control signal to a ROM module 14, an SRAM control port of the control circuit 12 outputs a control signal to an SRAM module 13, a first K-bit delay code output end of the control circuit 12 is connected to a second input port of a first delay circuit 15, a second K-bit delay code output end of the control circuit 12 is connected to a second input port of a second delay circuit 16, and a calibration control signal Ctrl output port of the control circuit 12 is simultaneously connected to calibration control signal Ctrl input ports of the charge domain phase error detection amplifying circuit 10, the K-bit charge domain analog-to-digital converter 11, the first delay circuit 15 and the second delay circuit 16; a first input port of the first delay circuit 15 is connected to a first N-bit calibration code output port of the ROM module 14, a third input port of the first delay circuit 15 is connected to an X-bit phase control input code, and an output port of the first delay circuit 15 outputs the X-bit conversion code to the phase amplitude converter 114 in the DDS chip; a first input port of the second delay circuit 16 is connected to the second N-bit calibration code output port of the ROM module 14, a third input port of the second delay circuit 16 is connected to the N-bit amplitude control input code, and an output port of the second delay circuit 16 outputs the N-bit conversion code to the N-bit current-mode DAC115 in the DDS chip.

The charge domain phase error calibration circuit comprises two working modes, namely a calibration mode and a compensation mode. When the circuit works, firstly entering a calibration mode and then entering a compensation mode; when entering the calibration mode, the X-bit phase control input code, the N-bit amplitude control input code, the first K-bit delay code, and the second K-bit delay code are all invalid, the first N-bit calibration code is input to the first delay circuit 15, the second N-bit calibration code is input to the second delay circuit 16, and the charge domain phase error calibration circuit sequentially performs phase error calibration on the N-bit current-mode DAC115 and the phase amplitude converter 114 in the DDS chip; when entering the compensation mode, the X-bit phase control input code and the N-bit amplitude control input code are respectively input to the first delay circuit 15 and the second delay circuit 16, the first N-bit calibration code and the second N-bit calibration code are invalid, the first K-bit delay code and the second K-bit delay code are valid, and the charge domain phase error calibration circuit simultaneously performs phase compensation on the N-bit current-mode DAC115 and the phase-amplitude converter 114 in the DDS chip.

The working principle of the circuit is as follows: when the calibration mode is turned on, the control circuit 12 firstly controls the charge domain phase error detection amplifying circuit 10, the K-bit charge domain analog-to-digital converter 11 and the second delay circuit 16 to enter the calibration mode through the Ctrl signal, and simultaneously outputs the K-bit selection code to the charge domain phase error detection amplifying circuit 10 to start the phase error calibration of the N-bit current-mode DAC115 in the DDS chip.

The control circuit 12 then generates a first set of K-bit selection codes, while controlling the ROM module 14 to generate a first set of second N-bit calibration codes cali (1); the first group of second N-bit calibration codes cali (1) enter the second delay circuit 16 to obtain N-bit conversion codes, the N-bit conversion codes enter an N-bit current analog-to-digital converter (DAC) 115 circuit in the DDS chip to be calibrated, and a first group of differential output current signals Iop and Ion corresponding to the first group of second N-bit calibration codes are obtained through digital-to-analog conversion; the charge domain phase error detection amplifying circuit 10 detects the amount of Iop-Ion, processes the Iop-Ion and performs phase detection on the Iop-Ion and the first group of reference clocks generated by the internal reference clock generating circuit, and amplifies the phase difference value of the Iop-Ion and the first group of reference clocks to obtain error voltage Vop-Von; the K-bit charge domain analog-to-digital converter 11 performs analog-to-digital conversion on the error voltage Vop-Von to obtain a first group of K-bit quantization codes and outputs the first group of K-bit quantization codes to the control circuit 12; the control circuit 12 stores the received first group of K-bit quantization codes in the SRAM module 13, and completes the phase error quantization of the N-bit current-mode DAC115 circuit in the DDS chip to be calibrated under an input condition.

Subsequently, the control circuit 12 then generates a second set of K-bit selection codes, while controlling the ROM module 14 to generate a second set of second N-bit calibration codes cali (2); a second group of second N-bit calibration codes cali (2) enter the second delay circuit 16 to obtain N-bit conversion codes, the N-bit conversion codes enter an N-bit current-mode DAC115 circuit in the DDS chip to be calibrated, and second group of differential output current signals Iop and Ion corresponding to the second group of second N-bit calibration codes are obtained through digital-to-analog conversion; the charge domain phase error detection amplifying circuit 10 detects the amount of Iop-Ion, processes the Iop-Ion and performs phase detection on the Iop-Ion and the second group of reference clocks generated by the internal reference clock generating circuit, and amplifies the phase difference value of the Iop-Ion and the second group of reference clocks to obtain error voltage Vop-Von; the K-bit charge domain analog-to-digital converter 11 performs analog-to-digital conversion on the error voltage Vop-Von to obtain a second group of K-bit quantization codes and outputs the second group of K-bit quantization codes to the control circuit 12; the control circuit 12 stores the received second group of K-bit quantization codes in the SRAM module 13, and completes the phase error quantization of the N-bit current-mode DAC115 circuit in the DDS chip to be calibrated under two input conditions.

By repeating this procedure, when the L-th group of the second N-bit calibration code cali (L) and the L-th group of the K-bit selection code are generated, and the L-th group of the K-bit quantization code is obtained and stored in the SRAM module 13, the operation circuit inside the control circuit 12 calculates the L-group of the K-bit quantization code stored in the K-bit register group to obtain the second K-bit delay code. The control circuit 12 outputs the second K-bit delay code to the second delay circuit 16, and keeps the second K-bit delay code unchanged, thereby completing the phase error calibration of the N-bit current-mode DAC115 in the DDS chip.

Then, the control circuit 12 controls the first delay circuit 15 to enter the calibration mode through the Ctrl signal, and simultaneously outputs the K-bit selection code to the charge domain phase error detection amplifying circuit 10, to start the phase error calibration of the phase amplitude converter 114 in the DDS chip. The control circuit 12 controls the ROM module 14 to generate a first N-bit calibration code, and the first delay circuit 15, the charge domain phase error detection amplifying circuit 10 and the K-bit charge domain analog-to-digital converter 11 obtain a first K-bit delay code by using the same steps and methods as those for calibrating the phase error of the N-bit current-mode DAC115 in the DDS chip, and output the first K-bit delay code to the first delay circuit 15, while keeping the first K-bit delay code unchanged, thereby completing the phase error calibration of the phase-to-amplitude converter 114. The calibration mode of the charge domain phase error calibration circuit ends.

The control circuit 12 sets the first delay circuit 15 and the second delay circuit 16 to the compensation mode at the same time, and starts compensating for the phase error of the N-bit current-mode DAC115 and the phase-amplitude converter 114 within the DDS chip. The control circuit 12 turns off the first N-bit calibration code and the second N-bit calibration code, turns off the charge domain phase error detection amplifying circuit 10 and the K-bit charge domain analog-to-digital converter 11, and the charge domain phase error calibration circuit enters a compensation mode.

In the above description, N is any positive integer, K is a positive integer not greater than N, and L is not greater than 2^KIs a positive integer of (1). In the calibration process, each set of the first N-bit calibration code, the second N-bit calibration code and the K-bit selection code output to the reference clock generation circuit, which are generated by the control circuit 12 at the same time, must correspond to one another, that is: the J-th group of the first N-bit calibration code and the second N-bit calibration code must be matched with the J-th group of the K-bit selection code for use; wherein J is a positive integer not greater than L.

In the actual use process of the charge domain phase error calibration circuit, the accuracy of phase error calibration, the hardware overhead and the calibration time can be set according to different K and L values so as to meet the calibration accuracy and speed requirements of DDS chips with different accuracies and speeds.

Fig. 2 shows an embodiment of the charge domain phase error detection amplifying circuit 10 of the present invention, which includes: a current detection resistor Rd 20, a reference clock generation circuit 21, a phase detector 22, a loop filter 23 and a charge domain voltage amplification circuit 24. Two ends of the current detection resistor Rd are respectively connected to the first and second input terminals of the charge domain phase error detection amplifying circuit 10, and connected to the first and second input terminals Voutp and Voutn of the phase detector 22; the reference clock generating circuit 21 generates a reference clock Clkref and is connected to the third input terminal of the phase detector 22 under the control of the K-bit selection code; the phase detector 22 further compares the phase of the signals at the 3 input terminals to obtain a phase error signal Vp, and the phase error signal Vp is filtered by the loop filter 23 to obtain a voltage signal V_i(ii) a The error signals Vop and Von are obtained by amplification by the charge domain voltage amplifying circuit 24.

Fig. 3 is a schematic diagram of the charge domain voltage amplifying circuit 24 according to the present invention. The charge domain voltage amplifying circuit 24 includes: a first positive side charge storage node Nip, a first negative side charge storage node Nin, a second positive side charge storage node Nop and a second negative side charge storage node Non, a positive side charge transfer control switch 301 connected between the first and second positive side charge storage nodes Nip and Nop, a negative side charge transfer control switch 302 connected between the first and second negative side charge storage nodes Nin and Non, a positive side capacitor 303 connected to the first positive side charge storage node Nip, a positive capacitance value programmable capacitor 309 connected to the second positive side charge storage node Nop, a negative side capacitor 304 connected to the first negative side charge storage node Nin, a negative capacitance value programmable capacitor 310 connected to the second negative side charge storage node Non, a first positive side voltage transfer switch 305 connected to the first positive side charge storage node Nip, a second positive side voltage transfer switch 307 connected to the first positive side charge storage node Nip, A third positive side voltage transfer switch 313 connected to the second positive side charge storage node Nop and a fourth positive side voltage transfer switch 311 connected to the second positive side charge storage node Nop, a first negative side voltage transfer switch 306 connected to the first negative side charge storage node Nin, a second negative side voltage transfer switch 308 connected to the first negative side charge storage node Nin, a third negative side voltage transfer switch 314 connected to the second negative side charge storage node Non and a fourth negative side voltage transfer switch 312 connected to the second negative side charge storage node Non. For the embodiment of the present invention, any one of the two analog voltage input ends of the charge domain voltage amplifying circuit 24 is connected to Vi, and the other end is connected to the reference signal.

FIG. 4 is a waveform diagram illustrating the operation timing control of the circuit shown in FIG. 3. The control clocks Clk and Clkn are clocks of opposite phases, and the switch control signals Clkr, Clks, and Clkt are clocks of non-overlapping phases. The charge transmission control switch in the invention can be realized by the embodiment described in the invention patent with patent number 201010291245.6, and the voltage transmission switch can be realized by a general MOS transistor or a BJT switch.

Fig. 5 shows an embodiment of the circuit of the phase detector 22 according to the invention. The circuit is composed of a signal shaping module and a subtracter submodule. The signal shaping module shapes the input differential signals Voutp and Voutn to obtain an input phase, a reference clock output by the reference clock is used as a reference phase, and the subtractor submodule subtracts the input phase from the reference phase to obtain a phase error signal Vp.

Fig. 6 is a block diagram of the reference clock generating circuit 21 according to the present invention. The reference clock generation circuit 21 includes: a programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit. The programmable frequency adjusting circuit and the programmable duty cycle adjusting circuit are both controlled by a K-bit selection code. Under the control of the K bit selection code, the input clock with fixed frequency and duty ratio passes through the programmable frequency adjusting circuit and the programmable duty ratio adjusting circuit in sequence, and then the reference clock Clkref with different frequency and duty ratio can be obtained.

As shown in fig. 7, the K-bit charge domain analog-to-digital converter 11 of the present invention includes: the device comprises a P-stage pipeline sub-stage circuit based on a charge domain signal processing technology, a last stage (P +1 st stage) A-bit Flash analog-to-digital converter circuit, a delay synchronous register and a digital correction circuit module. In addition, the operation mode control module is also an auxiliary operation module necessary for the operation of the analog-to-digital converter, and is not identified in the figure. The operation of two adjacent stages of sub-stage circuits in the charge domain analog-to-digital converter circuit in fig. 7 is controlled by two groups of multiphase clocks, the operation states are completely complementary, and the stage number of the sub-stage circuits and the bit number k of each stage of circuit can be flexibly adjusted. For example, for a 14-bit analog-to-digital converter with K ═ 14, a structure with 13 stages of 12 stages, 1.5 bits/stage and 1 stage, 2 bits Flash, or a structure with 8 stages of 4 stages, 2.5 bits/stage and 3 stages, 1.5 bits/stage and 1 stage, 3 bits Flash, may be adopted.

The charge domain analog-to-digital converter 11 designed by the invention comprises the following contents: the P-stage charge domain pipeline sub-stage circuit based on the charge domain signal processing technology is used for carrying out various processing on the charge packets obtained by sampling to complete analog-to-digital conversion and margin amplification, inputting the output digital code of each sub-stage circuit into a delay synchronous register, and enabling the charge packets output by each sub-stage circuit to enter the next stage to repeat the process; the last stage (P +1 stage) A-bit Flash analog-to-digital converter circuit converts the charge packet transmitted by the P stage into a voltage signal again, performs analog-to-digital conversion work of the last stage, inputs the output digital code of the stage circuit into a delay synchronous register, and only completes analog-to-digital conversion without margin amplification; the delay synchronous register is used for carrying out delay alignment on the digital code output by each sub-flow water level and inputting the aligned digital code to the digital correction module; and the digital correction circuit module is used for receiving the output digital code of the synchronous register and carrying out shift addition on the received digital code to obtain an R-bit digital output code of the analog-to-digital converter. In the above description, R is a positive integer, and A and P are both positive integers not greater than R.

Fig. 8 is a schematic diagram of a charge domain pipeline sub-stage circuit. The circuit is formed by fully differential signal processing channels, and the whole circuit comprises: the circuit comprises 2 current-stage charge transfer control switches, 2 charge storage nodes, 6 charge storage capacitors connected to the charge storage nodes, C charge comparators, C reference signal selection circuits controlled by output results of the comparators and 2B +2 voltage transfer switches, wherein B is a positive integer. When the circuit normally works, a preceding stage differential charge packet is transmitted through a charge transmission control switch and stored in a current stage charge storage node, and a comparator compares the voltage difference variable quantity between the nodes caused by the input of the differential charge packet with a reference voltage 3 and a reference voltage 4 to obtain a current stage C bit quantized output digital code D1-DB; the digital output codes D1-DB are output to a delay synchronous register, and D1-DB respectively control the reference signal selection circuit of the stage to generate a pair of complementary reference signals to respectively control the positive and negative end charges of the stage to add and subtract the capacitor bottom plate, and carry out addition and subtraction processing with corresponding size on the differential charge packet transmitted to the stage from the previous stage to obtain the differential residual charge packet of the stage; and finally, the circuit completes transmission of the differential residual charge packet of the current stage from the current stage to the next stage, and the reference voltage 2 and the reference voltage 1 reset the differential charge storage node of the current stage so as to complete the work of one complete clock cycle of the charge domain pipeline sub-stage circuit. Wherein C is a positive integer. The reference voltages 1-4 shown in FIG. 8 are identical to the reference voltages 1-4 shown in FIG. 3.

For the last stage (the P +1 st stage) of the charge domain pipeline analog-to-digital converter designed in the invention in fig. 7, the pipeline sub-stage circuit A-bit Flash analog-to-digital converter circuit based on the charge domain signal processing technology only needs to perform the analog-to-digital conversion work of the last stage on the received charge packet, and inputs the digital code output by the sub-stage circuit into the delay synchronous register without performing margin processing. The reference signal selection circuit and the 4 capacitors controlled by the reference signal selection circuit in fig. 8 may be eliminated.

Fig. 9 is a block diagram of the delay circuit according to the present invention. The delay circuit internally includes: the circuit comprises N delay buffer units, N K-bit delay registers, a first delay buffer unit to an Nth delay buffer unit, and a first K-bit delay register to an Nth K-bit delay register. The input ends of delay codes of the first K-bit delay register to the Nth K-bit delay register are all connected to a K-bit delay code, and the input ends of control signals are all connected to Ctrl signals; the input ends of delay codes of the first delay buffer unit to the Nth delay buffer unit are respectively connected to the output ends of the delay codes of the first K-bit delay register to the Nth K-bit delay register, the data output ends of the first delay buffer unit to the Nth delay buffer unit are respectively connected to the 1 st bit conversion code to the Nth bit conversion code and output, the input ends of first control signals of the first delay buffer unit to the Nth delay buffer unit are all connected to Ctrln signals, and the input ends of second control signals of the first delay buffer unit to the Nth delay buffer unit are all connected to Ctrl signals. Where Ctrl and Ctrln are inverted clocks.

The delay circuit is operable in both calibration and compensation modes under control of the Ctrl signal. In the calibration mode, the Ctrl signal is valid, the 1 st-nth input codes are invalid, the input codes have no influence on the output of the N-th conversion codes, the 1 st-nth calibration codes pass through the delay buffer circuits 1-N respectively to obtain the 1 st-nth conversion codes and output the 1 st-nth conversion codes, and the K-th delay codes are input into the first-nth K-delay registers and latched and kept unchanged. In the compensation mode, the Ctrln signal is valid, the 1 st to Nth bit conversion codes are valid and output after passing through the delay buffer circuit, the 1 st to Nth bit conversion codes are invalid, and the K bit delay codes stored in the first to Nth K bit delay registers are input into the delay buffer circuit 1 to the delay buffer circuit N for delay compensation.

The first delay circuit 15 and the second delay circuit 16 according to the present invention each adopt the delay circuit structure shown in fig. 9.

Fig. 10 is a block diagram of the control circuit 12 according to the present invention. The control circuit 12 includes: the circuit comprises a core control circuit, a ROM reading circuit, a first delay code generating circuit, a second delay code generating circuit, a selection code generating circuit, an arithmetic circuit, an SRAM reading and writing circuit and a K-bit register.

The connection relationship is as follows: a first output end of the core control circuit is connected to an input end of the ROM reading circuit, a second output end of the core control circuit is connected to a control input end of the first delay code generating circuit, a third output end of the core control circuit is connected to a control input end of the second delay code generating circuit, a fourth output end of the core control circuit is connected to a control input end of the arithmetic circuit, a fifth output end of the core control circuit is connected to a control input end of the selection code generating circuit, a sixth output end of the core control circuit generates a calibration control signal Ctrl, a seventh output end of the core control circuit is simultaneously connected to a K-bit register and a control input end of the SRAM reading and writing circuit, and an input end of the core control circuit is connected to a calibration start control; the ROM reading circuit generates a ROM address code according to a control instruction of the core control circuit; the data input end of the arithmetic circuit receives data sent by the output end of the SRAM read-write circuit and generates a first K-bit error code and a second K-bit error code according to a control instruction of the core control circuit; the data input end of the first delay code generating circuit receives a first K-bit error code sent by the data output end of the arithmetic circuit and generates a first K-bit delay code according to a control instruction of the core control circuit; the data input end of the second delay code generating circuit receives a second K-bit error code sent by the data output end of the arithmetic circuit and generates a second K-bit delay code according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; a data input end of the K-bit register receives the K-bit quantization code sent by the output end of the K-bit charge domain analog-to-digital converter 11, and sends data stored in the K-bit charge domain analog-to-digital converter to an SRAM read-write circuit according to a control instruction of a core control circuit; the SRAM read/write circuit generates an SRAM address data code according to a control instruction of the core control circuit, and reads and writes data to the SRAM module 13.

Fig. 11 is a block diagram of a DDS circuit employing a charge domain phase error calibration circuit according to the present invention. The DDS circuit includes: a phase accumulator 113, a phase-to-amplitude converter 114, an N-bit current-mode DAC115, a charge domain phase error calibration circuit 110, a clock generation circuit 111, and a mode control circuit 112.

The connection relation of the DDS circuit is as follows: a first calibration control signal output terminal of the mode control circuit 112 is connected to the calibration signal control terminals of the phase accumulator 113, the phase-to-amplitude converter 114 and the N-bit current-to-analog DAC115, a second calibration control signal output terminal of the mode control circuit 112 is connected to the calibration signal control terminal of the clock generation circuit 111, and a third calibration control signal output terminal of the mode control circuit 112 is connected to the calibration signal control terminal of the charge domain phase error calibration circuit 110; the output of the phase accumulator 113 is connected to the X-phase control input code input of the charge domain phase error calibration circuit 110; the phase control input terminal of the phase amplitude converter 114 is connected to the X-bit conversion code output terminal of the charge domain phase error calibration circuit 110, and the N-bit amplitude control input code output by the phase amplitude converter 114 is connected to the N-bit amplitude control input code input terminal of the charge domain phase error calibration circuit 110; the N-bit current-mode DAC115 generates output differential current signals Iop and Ion under the control of the first calibration control signal, the N-bit conversion code, the operating clock f0, and the calibration clock fc; the charge domain phase error calibration circuit 110 detects and processes the differential current signals Iop and Ion under the control of the calibration clock fc and the third calibration control signal to obtain an X-bit conversion code and an N-bit conversion code which are subjected to phase compensation and output the X-bit conversion code and the N-bit conversion code to the phase amplitude converter 114 and the N-bit current mode DAC115 respectively; the clock generation circuit 111 generates a clock calibration clock fc and a working clock f0 under the control of the second calibration control signal, the working clock f0 is used for controlling the calibration clock phase accumulator 113, the phase-amplitude converter 114 and the N-bit current-mode DAC115, and the calibration clock fc is used for controlling the phase-amplitude converter 114, the N-bit current-mode DAC115 and the charge domain phase error calibration circuit 110.

The DDS circuit adopting the charge domain phase error calibration circuit comprises two working modes, namely a calibration mode and a compensation mode. When the DDS circuit adopting the charge domain phase error calibration circuit works, the DDS circuit firstly enters a calibration mode and then enters a compensation mode; when entering the calibration mode, the mode control circuit 112 controls the clock generation circuit 111 to turn off the operating clock f0 by the second calibration control signal, and outputs the calibration clock fc; the mode control circuit 112 further controls the charge domain phase error calibration circuit 110 to start phase error calibration on the DDS circuit through a third calibration control signal; the mode control circuit 112 also controls the phase accumulator 113, the phase-to-amplitude converter 114 and the N-bit current-mode DAC115 to enter a calibration mode via the first calibration control signal; the phase-amplitude converter 114, the charge domain phase error calibration circuit 110 and the N-bit current-mode DAC115 start the DDS phase error calibration under the control of the calibration clock fc; the calibration of the DDS phase error caused by the phase error of the N-bit current-mode DAC115 is performed first, and then the calibration of the DDS phase error caused by the phase error of the phase-to-amplitude converter 114 is performed, where the X-bit phase control input code and the N-bit amplitude control input code are in an invalid state.

When the DDS circuit employing the charge domain phase error calibration circuit 110 enters the compensation mode after the charge domain phase error calibration circuit 110 completes calibration of the DDS phase error caused by the phase error of the phase-to-amplitude converter 114, the mode control circuit 112 controls the clock generation circuit 111 to turn off the calibration clock fc via the second calibration control signal, and outputs the working clock f 0; the mode control circuit 112 further controls the charge domain phase error calibration circuit 110 to start phase error compensation for the DDS circuit through a third calibration control signal, and outputs the phase-compensated X-bit conversion code and N-bit conversion code to the phase amplitude converter 114 and the N-bit current-mode DAC115, respectively; the mode control circuit 112 also controls the phase accumulator 113, the phase-amplitude converter 114 and the N-bit current-mode DAC115 to enter the normal operation mode through the first calibration control signal, and the phase-amplitude converter 114 and the N-bit current-mode DAC115 will operate under the control of the operation clock f 0; and the X-bit phase control input code and the N-bit amplitude control input code start to be effective, and the DDS circuit adopting the charge domain phase error calibration circuit starts a normal frequency output synthesis working mode.

In practical applications, the selection of the frequencies of the calibration clock fc and the operating clock f0 can be chosen in a trade-off manner according to the application requirements of the system, and in order to realize low power consumption, the frequency of fc can be set to be a lower frequency, and the cost is that the calibration time is prolonged; to achieve faster calibration speed, the frequency of fc can be set to a higher frequency at the expense of increased circuit power consumption.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A charge domain phase error calibration circuit, comprising: the device comprises a charge domain phase error detection amplifying circuit (10), a K-bit charge domain analog-to-digital converter (11), a control circuit (12), a ROM module (14), an SRAM module (13), a first delay circuit (15) and a second delay circuit (16);

the connection relationship of the circuits is as follows: a first input end and a second input end of the charge domain phase error detection amplifying circuit (10) are respectively connected to a signal output differential port of an N-bit current-mode DAC (115) in the DDS chip, a control input end of the charge domain phase error detection amplifying circuit (10) is connected to a K-bit selection code output port of the control circuit (12), and a differential voltage output end of the charge domain phase error detection amplifying circuit (10) is connected to a differential voltage input end of a K-bit charge domain analog-to-digital converter (11); the K bit quantization code of the K bit charge domain analog-to-digital converter (11) is output to an error input port of the control circuit (12); a ROM control port of the control circuit (12) outputs a control signal to a ROM module (14), an SRAM control port of the control circuit (12) outputs a control signal to an SRAM module (13), a first K bit delay code output end of the control circuit (12) is connected to a second input port of the first delay circuit (15), a second K bit delay code output end of the control circuit (12) is connected to a second input port of the second delay circuit (16), and a calibration control signal Ctrl output port of the control circuit (12) is simultaneously connected to calibration control signal Ctrl input ports of the charge domain phase error detection amplifying circuit (10), the K bit charge domain analog-to-digital converter (11), the first delay circuit (15) and the second delay circuit (16); a first input port of the first delay circuit (15) is connected with a first N-bit calibration code output end of the ROM module (14), a third input port of the first delay circuit (15) is connected with an X-bit phase control input code, and an output port of the first delay circuit (15) outputs the X-bit conversion code to a phase amplitude converter (114) in the DDS chip; a first input port of the second delay circuit (16) is connected with a second N-bit calibration code output end of the ROM module (14), a third input port of the second delay circuit (16) is connected with an N-bit amplitude control input code, and an output port of the second delay circuit (16) outputs the N-bit conversion code to an N-bit current-mode DAC (115) in the DDS chip; wherein X and N are any positive integer, and K is a positive integer not greater than N.

2. The charge domain phase error calibration circuit of claim 1, wherein the operating mode comprises a calibration mode and a compensation mode; when the circuit works, the circuit firstly enters a calibration mode and then enters a compensation mode;

when entering a calibration mode, an X-bit phase control input code, an N-bit amplitude control input code, a first K-bit delay code and a second K-bit delay code are invalid, the first N-bit calibration code is input into a first delay circuit (15), the second N-bit calibration code is input into a second delay circuit (16), and a charge domain phase error calibration circuit sequentially performs phase error calibration on an N-bit current mode DAC (115) and a phase amplitude converter (114) in a DDS chip;

when entering a compensation mode, an X-bit phase control input code and an N-bit amplitude control input code are respectively input into a first delay circuit (15) and a second delay circuit (16), a first N-bit calibration code and a second N-bit calibration code are invalid, a first K-bit delay code and a second K-bit delay code are valid, and a charge domain phase error calibration circuit simultaneously carries out phase compensation on an N-bit current-mode DAC (115) and a phase amplitude converter (114) in a DDS chip.

3. The charge domain phase error calibration circuit of claim 2, wherein when entering the calibration mode, the circuit operates in the following sequence:

1. firstly, calibrating phase error of an N-bit current mode DAC (115) in a DDS chip:

the control circuit (12) firstly controls the charge domain phase error detection amplifying circuit (10), the K-bit charge domain analog-to-digital converter (11) and the second delay circuit (16) to enter a calibration mode through a Ctrl signal, and simultaneously outputs a K-bit selection code to the charge domain phase error detection amplifying circuit (10) to start phase error calibration on an N-bit current-mode DAC (115) in the DDS chip;

then the control circuit (12) generates a first group of K bit selection codes, and simultaneously controls the ROM module (14) to generate a first group of second N bit calibration codes, and the N bit current mode DAC (115) obtains a first group of differential output current signals Iop and Ion corresponding to the first group of second N bit calibration codes; the charge domain phase error detection amplifying circuit (10) detects an Iop-Ion amount and processes the Iop-Ion amount to obtain an error voltage; the K-bit charge domain analog-to-digital converter (11) performs analog-to-digital conversion on the error voltage to obtain a first group of K-bit quantization codes and outputs the first group of K-bit quantization codes to the control circuit (12); the control circuit (12) stores the received first group of K-bit quantization codes in an SRAM module (13) to finish the phase error quantization of an N-bit current mode DAC (115) circuit in the DDS chip to be calibrated under an input condition;

next, the control circuit (12) generates a second group of K bit selection codes, and simultaneously controls the ROM module (14) to generate a second group of second N bit calibration codes, and the second group of K bit quantization codes can be obtained and output to the control circuit (12) through the processing of the N bit current mode DAC (115), the charge domain phase error detection amplifying circuit (10) and the K bit charge domain analog-to-digital converter (11); the control circuit (12) stores the received second group of K-bit quantization codes in an SRAM module (13) to finish the phase error quantization of an N-bit current mode DAC (115) circuit in the DDS chip to be calibrated under two input conditions;

according to the circulation, when an L-th group of second N-bit calibration codes and an L-th group of K-bit selection codes are generated, an L-th group of K-bit quantization codes are obtained and stored in an SRAM module (13), an operation circuit in the control circuit (12) calculates the L-th group of K-bit quantization codes stored in the K-bit register group to obtain a second K-bit delay code; the control circuit (12) outputs the second K bit delay code to the second delay circuit (16) at the moment, keeps the second K bit delay code unchanged, and completes the phase error calibration of the N bit current mode DAC (115) in the DDS chip;

2. performing phase error calibration on a phase-to-amplitude converter (114) within the DDS chip:

the control circuit (12) controls the first delay circuit (15) to enter a calibration mode through a Ctrl signal, and simultaneously outputs a K-bit selection code to the charge domain phase error detection amplifying circuit (10) to start phase error calibration on a phase amplitude converter (114) in the DDS chip;

the control circuit (12) controls the ROM module (14) to generate a first N-bit calibration code, the first delay circuit (15), the charge domain phase error detection amplifying circuit (10) and the K-bit charge domain analog-to-digital converter (11) are used, the first K-bit delay code is obtained by adopting the same step and method as the phase error calibration of the N-bit current mode DAC (115) in the DDS chip and is output to the first delay circuit (15), meanwhile, the first K-bit delay code is kept unchanged, and the phase error calibration of the phase amplitude converter (114) in the DDS chip is completed; at this time, the calibration mode of the charge domain phase error calibration circuit ends;

in the calibration process, each set of the first N-bit calibration code, the second N-bit calibration code and the K-bit selection code generated by the control circuit (12) at the same time must correspond to one another, that is: the J-th group of the first N-bit calibration code and the second N-bit calibration code must be matched with the J-th group of the K-bit selection code for use; wherein L is not more than 2^KJ is a positive integer not greater than L.

4. The charge domain phase error calibration circuit of claim 1, wherein said charge domain phase error detection amplification circuit (10) comprises: the circuit comprises a current detection resistor (20), a reference clock generation circuit (21), a phase detector (22), a loop filter (23) and a charge domain voltage amplification circuit (24);

the connection relationship of the circuits is as follows: two ends of the current detection resistor (20) are respectively connected to a first input end and a second input end of the charge domain phase error detection amplifying circuit (10) and respectively connected to a first input end and a second input end of the phase discriminator (22); the reference clock generating circuit (21) generates a reference clock and is connected to a third input end of the phase discriminator (22) under the control of the K bit selection code; the phase discriminator (22) carries out further phase comparison on the signals of the 3 input ends to obtain a phase error signal; the phase error signal is filtered by a loop filter (23) to obtain a voltage signal V_i；V_iThe error signals Vop and Von are obtained by amplifying the error signals through a charge domain voltage amplifying circuit (24).

5. A charge domain phase error calibration circuit as claimed in claim 1 wherein said K-bit charge domain analog to digital converter (11) comprises: the P-stage production line sub-stage circuit based on the charge domain signal processing technology is used for carrying out various processing on the charge packets obtained by sampling to complete analog-to-digital conversion and margin amplification, inputting the output digital code of each sub-stage circuit into a delay synchronous register, and enabling the charge packets output by each sub-stage circuit to enter a next sub-stage circuit to repeat the working process of the previous stage; the P +1 stage, which is also the last stage of A-bit Flash analog-to-digital converter circuit, converts the charge packet transmitted from the P stage into a voltage signal again, performs the analog-to-digital conversion work of the last stage, and inputs the output digital code of the stage circuit into a delay synchronous register, and the stage circuit only completes the analog-to-digital conversion without margin amplification; the delay synchronous register is used for carrying out delay alignment on the digital code output by each sub-flow water level and inputting the aligned digital code into the digital correction module; the digital correction circuit module is used for receiving the output digital code of the synchronous register and carrying out shift addition on the received digital code to obtain an R-bit digital output code of the analog-to-digital converter; wherein R is a positive integer, and P and A are both positive integers not greater than R.

6. The charge domain phase error calibration circuit of claim 1, wherein said first delay circuit (15) and said second delay circuit (16) each employ the same delay circuit, the structure comprising: n delay buffer units and N K-bit delay registers; the delay code input ends of the first K-bit delay register to the Nth K-bit delay register are all connected to the K-bit delay code, and the control signal input ends are all connected to the calibration control signal Ctrl; the input ends of delay codes of the first delay buffer unit to the Nth delay buffer unit are respectively connected to the output ends of the delay codes of the first K-bit delay register to the Nth K-bit delay register, the data output ends of the first delay buffer unit to the Nth delay buffer unit are respectively connected to the 1 st bit conversion code to the Nth bit conversion code and output, the input ends of first control signals of the first delay buffer unit to the Nth delay buffer unit are all connected to a reverse signal Ctrln of a calibration control signal Ctrl, and the input ends of second control signals of the first delay buffer unit to the Nth delay buffer unit are all connected to the signal Ctrl.

7. The charge domain phase error calibration circuit of claim 6, wherein said delay circuit is capable of operating in both a calibration mode and a compensation mode;

8. The charge domain phase error calibration circuit of claim 1, wherein said control circuit (12) comprises: the circuit comprises a core control circuit, a Read Only Memory (ROM) read circuit, a first delay code generating circuit, a second delay code generating circuit, a selection code generating circuit, an arithmetic circuit, a Static Random Access Memory (SRAM) read-write circuit and a K-bit register;

the connection relationship of the circuits is as follows: a first output end of the core control circuit is connected to an input end of the ROM reading circuit, a second output end of the core control circuit is connected to a control input end of the first delay code generating circuit, a third output end of the core control circuit is connected to a control input end of the second delay code generating circuit, a fourth output end of the core control circuit is connected to a control input end of the arithmetic circuit, a fifth output end of the core control circuit is connected to a control input end of the selection code generating circuit, a sixth output end of the core control circuit generates a calibration control signal Ctrl, a seventh output end of the core control circuit is simultaneously connected to a K-bit register and a control input end of the SRAM reading and writing circuit, and an input end of the core control circuit is connected to a calibration start control; the ROM reading circuit generates a ROM address code according to a control instruction of the core control circuit; the data input end of the arithmetic circuit receives data sent by the output end of the SRAM read-write circuit and generates a first K-bit error code and a second K-bit error code according to a control instruction of the core control circuit; the data input end of the first delay code generating circuit receives a first K-bit error code sent by the data output end of the arithmetic circuit and generates a first K-bit delay code according to a control instruction of the core control circuit; the data input end of the second delay code generating circuit receives a second K-bit error code sent by the data output end of the arithmetic circuit and generates a second K-bit delay code according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the data input end of the K-bit register receives the K-bit quantization code sent by the output end of the K-bit charge domain analog-to-digital converter (11), and sends the data stored in the K-bit charge domain analog-to-digital converter to the SRAM read-write circuit according to the control instruction of the core control circuit; the SRAM read-write circuit generates an SRAM address data code according to a control instruction of the core control circuit, and data reading and writing are carried out on the SRAM module (13).

9. A DDS circuit employing the charge domain phase error calibration circuit of claim 1, comprising the charge domain phase error calibration circuit (110) of claim 1, further comprising: a phase accumulator (113), a phase-to-amplitude converter (114), an N-bit current-mode DAC (115), a clock generation circuit (111), and a mode control circuit (112);

the connection relationship of the circuit is as follows: a first calibration control signal output terminal of the mode control circuit (112) is connected to a calibration signal control terminal of the phase accumulator (113), the phase-amplitude converter (114) and the N-bit current-mode DAC (115), a second calibration control signal output terminal of the mode control circuit (112) is connected to a calibration signal control terminal of the clock generation circuit (111), and a third calibration control signal output terminal of the mode control circuit (112) is connected to a calibration signal control terminal of the charge domain phase error calibration circuit (110); the output of the phase accumulator (113) is connected to the X-phase control input code input of the charge domain phase error calibration circuit (110); the phase control input end of the phase amplitude converter (114) is connected to the X-bit conversion code output end of the charge domain phase error calibration circuit (110), and the N-bit amplitude control input code output by the phase amplitude converter (114) is connected to the N-bit amplitude control input code input end of the charge domain phase error calibration circuit (110); an N-bit current mode DAC (115) generates output differential current signals Iop and Ion according to the control of a first calibration control signal, an N-bit conversion code, a working clock f0 and a calibration clock fc; under the control of a calibration clock fc and a third calibration control signal, a charge domain phase error calibration circuit (110) detects and processes differential current signals Iop and Ion to obtain an X-bit conversion code and an N-bit conversion code which are subjected to phase compensation and output the X-bit conversion code and the N-bit conversion code to a phase amplitude converter (114) and an N-bit current mode DAC (115) respectively; the clock generation circuit (111) generates a calibration clock fc and a working clock f0 under the control of the second calibration control signal, the working clock f0 is used for controlling the calibration clock phase accumulator (113), the phase-amplitude converter (114) and the N-bit current-mode DAC (115), and the calibration clock fc is used for controlling the phase-amplitude converter (114), the N-bit current-mode DAC (115) and the charge domain phase error calibration circuit (110).

10. The DDS circuit of claim 9 wherein there are two modes of operation, a calibration mode and a compensation mode; when the circuit works, the circuit firstly enters a calibration mode and then enters a compensation mode;

when the circuit enters a calibration mode, the mode control circuit (112) controls the clock generation circuit (111) to close the working clock f0 through a second calibration control signal, and outputs a calibration clock fc; the mode control circuit (112) also controls the charge domain phase error calibration circuit to start phase error calibration on the DDS circuit through a third calibration control signal; the mode control circuit (112) also controls the phase accumulator (113), the phase-to-amplitude converter (114) and the N-bit current-mode DAC (115) to enter a calibration mode via the first calibration control signal; the phase amplitude converter (114), the charge domain phase error calibration circuit and the N-bit current mode DAC (115) start DDS phase error calibration under the control of a calibration clock fc; firstly, calibrating a DDS phase error caused by a phase error of an N-bit current mode DAC (115), and then calibrating a DDS phase error caused by a phase error of a phase amplitude converter (114), wherein an X-bit phase control input code and an N-bit amplitude control input code are in an invalid state;

when entering the compensation mode, the mode control circuit (112) controls the clock generation circuit (111) to close the calibration clock fc through the second calibration control signal, and outputs the working clock f 0; the mode control circuit (112) also controls the charge domain phase error calibration circuit (110) to start phase error compensation on the DDS circuit through a third calibration control signal, and outputs the phase-compensated X-bit conversion code and N-bit conversion code to the phase amplitude converter (114) and the N-bit current-mode DAC (115) respectively; the mode control circuit (112) also controls the phase accumulator (113), the phase-amplitude converter (114) and the N-bit current-mode DAC (115) to enter a normal operation mode through the first calibration control signal, the phase-amplitude converter (114) and the N-bit current-mode DAC (115) will operate under the control of the operation clock f 0; the X-bit phase control input code and the N-bit amplitude control input code start to be valid.